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plat: imx: add sdei support for i.MX8MM 

Add sdei support for i.MX8MM, this is to let jailhouse Hypervisor
could use SDEI to do hypervisor management, after physical IRQ
has been disabled routing.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Change-Id: I5fd697fee22df151e13d0f1335e8ac8a7bae6189
This commit is contained in:
Peng Fan 2020-07-27 21:22:14 +08:00 committed by Peng Fan
parent e4c837568c
commit 8567103ef9
5 changed files with 68 additions and 0 deletions
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22
plat/imx/common/imx_ehf.c Normal file
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@ -0,0 +1,22 @@
/*
* Copyright 2020 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <bl31/ehf.h>
#include <platform_def.h>
ehf_pri_desc_t imx_exceptions[] = {
#if SDEI_SUPPORT
/* Critical priority SDEI */
EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_SDEI_CRITICAL_PRI),
/* Normal priority SDEI */
EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_SDEI_NORMAL_PRI),
#endif
};
/* Plug in ARM exceptions to Exception Handling Framework. */
EHF_REGISTER_PRIORITIES(imx_exceptions, ARRAY_SIZE(imx_exceptions), PLAT_PRI_BITS);

32
plat/imx/common/imx_sdei.c Normal file
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@ -0,0 +1,32 @@
/*
* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
* Copyright 2020 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/* SDEI configuration for ARM platforms */
#include <bl31/ehf.h>
#include <common/debug.h>
#include <services/sdei.h>
#include <lib/utils_def.h>
#include <platform_def.h>
/* Private event mappings */
static sdei_ev_map_t imx_sdei_private[] = {
SDEI_DEFINE_EVENT_0(PLAT_SDEI_SGI_PRIVATE),
};
/* Shared event mappings */
static sdei_ev_map_t imx_sdei_shared[] = {
};
void plat_sdei_setup(void)
{
INFO("SDEI platform setup\n");
}
/* Export ARM SDEI events */
REGISTER_SDEI_MAP(imx_sdei_private, imx_sdei_shared);

4
plat/imx/common/plat_imx8_gic.c
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@ -22,6 +22,10 @@ uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
static const interrupt_prop_t g01s_interrupt_props[] = {
INTR_PROP_DESC(8, GIC_HIGHEST_SEC_PRIORITY,
INTR_GROUP0, GIC_INTR_CFG_LEVEL),
#if SDEI_SUPPORT
INTR_PROP_DESC(PLAT_SDEI_SGI_PRIVATE, PLAT_SDEI_NORMAL_PRI,
INTR_GROUP0, GIC_INTR_CFG_LEVEL),
#endif
};
static unsigned int plat_imx_mpidr_to_core_pos(unsigned long mpidr)

5
plat/imx/imx8m/imx8mm/include/platform_def.h
View File

@ -29,6 +29,11 @@
#define PLAT_WAIT_RET_STATE U(1)
#define PLAT_STOP_OFF_STATE U(3)
#define PLAT_PRI_BITS U(3)
#define PLAT_SDEI_CRITICAL_PRI 0x10
#define PLAT_SDEI_NORMAL_PRI 0x20
#define PLAT_SDEI_SGI_PRIVATE U(9)
#define BL31_BASE U(0x920000)
#define BL31_LIMIT U(0x940000)

5
plat/imx/imx8m/imx8mm/platform.mk
View File

@ -29,6 +29,8 @@ BL31_SOURCES += plat/imx/common/imx8_helpers.S \
plat/imx/common/imx_sip_handler.c \
plat/imx/common/imx_sip_svc.c \
plat/imx/common/imx_uart_console.S \
plat/imx/common/imx_ehf.c \
plat/imx/common/imx_sdei.c \
lib/xlat_tables/aarch64/xlat_tables.c \
lib/xlat_tables/xlat_tables_common.c \
lib/cpus/aarch64/cortex_a53.S \
@ -53,3 +55,6 @@ $(eval $(call add_define,BL32_SIZE))
IMX_BOOT_UART_BASE ?= 0x30890000
$(eval $(call add_define,IMX_BOOT_UART_BASE))
EL3_EXCEPTION_HANDLING := 1
SDEI_SUPPORT := 1