Merge pull request #523 from jcastillo-arm/jc/genfw-791
ARM platforms: rationalise memory attributes of shared memory
This commit is contained in:
commit
85df7e44ce
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@ -194,6 +194,8 @@ DEFINE_SYSOP_FUNC(wfe)
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DEFINE_SYSOP_FUNC(sev)
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DEFINE_SYSOP_TYPE_FUNC(dsb, sy)
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DEFINE_SYSOP_TYPE_FUNC(dmb, sy)
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DEFINE_SYSOP_TYPE_FUNC(dmb, st)
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DEFINE_SYSOP_TYPE_FUNC(dmb, ld)
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DEFINE_SYSOP_TYPE_FUNC(dsb, ish)
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DEFINE_SYSOP_TYPE_FUNC(dmb, ish)
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DEFINE_SYSOP_FUNC(isb)
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@ -151,14 +151,10 @@
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#define ARM_G0_IRQS ARM_IRQ_SEC_SGI_0, \
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ARM_IRQ_SEC_SGI_6
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#define ARM_SHARED_RAM_ATTR ((PLAT_ARM_SHARED_RAM_CACHED ? \
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MT_MEMORY : MT_DEVICE) \
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| MT_RW | MT_SECURE)
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#define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \
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ARM_SHARED_RAM_BASE, \
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ARM_SHARED_RAM_SIZE, \
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ARM_SHARED_RAM_ATTR)
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MT_DEVICE | MT_RW | MT_SECURE)
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#define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \
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ARM_NS_DRAM1_BASE, \
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@ -37,8 +37,6 @@
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/*************************************************************************
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* Definitions common to all ARM Compute SubSystems (CSS)
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*************************************************************************/
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#define MHU_PAYLOAD_CACHED 0
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#define NSROM_BASE 0x1f000000
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#define NSROM_SIZE 0x00001000
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@ -141,8 +139,6 @@
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#define SCP_BL2U_BASE BL31_BASE
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#endif /* CSS_LOAD_SCP_IMAGES */
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#define PLAT_ARM_SHARED_RAM_CACHED MHU_PAYLOAD_CACHED
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/* Load address of Non-Secure Image for CSS platform ports */
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#define PLAT_ARM_NS_IMAGE_OFFSET 0xE0000000
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@ -64,8 +64,6 @@
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#define PLAT_ARM_DRAM2_SIZE MAKE_ULL(0x780000000)
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#define PLAT_ARM_SHARED_RAM_CACHED 1
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/*
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* Load address of BL33 for this platform port
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*/
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@ -192,11 +192,6 @@ void arm_program_trusted_mailbox(uintptr_t address)
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assert((PLAT_ARM_TRUSTED_MAILBOX_BASE >= ARM_SHARED_RAM_BASE) &&
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((PLAT_ARM_TRUSTED_MAILBOX_BASE + sizeof(*mailbox)) <= \
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(ARM_SHARED_RAM_BASE + ARM_SHARED_RAM_SIZE)));
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/* Flush data cache if the mail box shared RAM is cached */
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#if PLAT_ARM_SHARED_RAM_CACHED
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flush_dcache_range((uintptr_t) mailbox, sizeof(*mailbox));
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#endif
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}
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/*******************************************************************************
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@ -77,10 +77,10 @@ static void scp_boot_message_start(void)
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static void scp_boot_message_send(size_t payload_size)
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{
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/* Make sure payload can be seen by SCP */
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if (MHU_PAYLOAD_CACHED)
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flush_dcache_range(BOM_SHARED_MEM,
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sizeof(bom_cmd_t) + payload_size);
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/* Ensure that any write to the BOM payload area is seen by SCP before
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* we write to the MHU register. If these 2 writes were reordered by
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* the CPU then SCP would read stale payload data */
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dmbst();
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/* Send command to SCP */
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mhu_secure_message_send(BOM_MHU_SLOT_ID);
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@ -99,9 +99,10 @@ static uint32_t scp_boot_message_wait(size_t size)
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panic();
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}
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/* Make sure we see the reply from the SCP and not any stale data */
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if (MHU_PAYLOAD_CACHED)
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inv_dcache_range(BOM_SHARED_MEM, size);
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/* Ensure that any read to the BOM payload area is done after reading
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* the MHU register. If these 2 reads were reordered then the CPU would
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* read invalid payload data */
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dmbld();
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return *(uint32_t *) BOM_SHARED_MEM;
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}
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@ -56,10 +56,10 @@ static void scpi_secure_message_start(void)
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static void scpi_secure_message_send(size_t payload_size)
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{
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/* Make sure payload can be seen by SCP */
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if (MHU_PAYLOAD_CACHED)
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flush_dcache_range(SCPI_SHARED_MEM_AP_TO_SCP,
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sizeof(scpi_cmd_t) + payload_size);
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/* Ensure that any write to the SCPI payload area is seen by SCP before
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* we write to the MHU register. If these 2 writes were reordered by
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* the CPU then SCP would read stale payload data */
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dmbst();
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mhu_secure_message_send(SCPI_MHU_SLOT_ID);
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}
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@ -79,9 +79,10 @@ static void scpi_secure_message_receive(scpi_cmd_t *cmd)
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panic();
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}
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/* Make sure we don't read stale data */
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if (MHU_PAYLOAD_CACHED)
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inv_dcache_range(SCPI_SHARED_MEM_SCP_TO_AP, sizeof(*cmd));
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/* Ensure that any read to the SCPI payload area is done after reading
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* the MHU register. If these 2 reads were reordered then the CPU would
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* read invalid payload data */
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dmbld();
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memcpy(cmd, (void *) SCPI_SHARED_MEM_SCP_TO_AP, sizeof(*cmd));
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}
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