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Disable secure self-hosted debug via MDCR_EL3/SDCR 

Trusted Firmware currently has no support for secure self-hosted
debug.  To avoid unexpected exceptions, disable software debug
exceptions, other than software breakpoint instruction exceptions,
from all exception levels in secure state.  This applies to both
AArch32 and AArch64 EL3 initialization.

Change-Id: Id097e54a6bbcd0ca6a2be930df5d860d8d09e777
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
This commit is contained in:
dp-arm 2017-02-08 11:51:50 +00:00
parent 4d07e7821e
commit 85e93ba093
4 changed files with 26 additions and 2 deletions
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5
include/common/aarch32/el3_common_macros.S
View File

@ -98,6 +98,11 @@
orr r0, r0, #FPEXC_EN_BIT
vmsr FPEXC, r0
isb
/* Disable secure self-hosted invasive debug. */
ldr r0, =SDCR_DEF_VAL
stcopr r0, SDCR
.endm
/* -----------------------------------------------------------------------------

5
include/common/aarch64/el3_common_macros.S
View File

@ -79,10 +79,11 @@
msr scr_el3, x0
/* ---------------------------------------------------------------------
* Reset registers that may have architecturally unknown reset values
* Disable secure self-hosted invasive debug.
* ---------------------------------------------------------------------
*/
msr mdcr_el3, xzr
mov_imm x0, MDCR_DEF_VAL
msr mdcr_el3, x0
/* ---------------------------------------------------------------------
* Enable External Aborts and SError Interrupts now that the exception

9
include/lib/aarch32/arch.h
View File

@ -125,6 +125,14 @@
#define SCTLR_AFE_BIT (1 << 29)
#define SCTLR_TE_BIT (1 << 30)
/* SDCR definitions */
#define SDCR_SPD(x) ((x) << 14)
#define SDCR_SPD_LEGACY 0x0
#define SDCR_SPD_DISABLE 0x2
#define SDCR_SPD_ENABLE 0x3
#define SDCR_DEF_VAL SDCR_SPD(SDCR_SPD_DISABLE)
/* HSCTLR definitions */
#define HSCTLR_RES1 ((1 << 29) | (1 << 28) | (1 << 23) | (1 << 22) \
| (1 << 18) | (1 << 16) | (1 << 11) | (1 << 4) \
@ -345,6 +353,7 @@
/* System register defines The format is: coproc, opt1, CRn, CRm, opt2 */
#define SCR p15, 0, c1, c1, 0
#define SCTLR p15, 0, c1, c0, 0
#define SDCR p15, 0, c1, c3, 1
#define MPIDR p15, 0, c0, c0, 5
#define MIDR p15, 0, c0, c0, 0
#define VBAR p15, 0, c12, c0, 0

9
include/lib/aarch64/arch.h
View File

@ -195,6 +195,15 @@
#define SCR_NS_BIT (1 << 0)
#define SCR_VALID_BIT_MASK 0x2f8f
/* MDCR definitions */
#define MDCR_SPD32(x) ((x) << 14)
#define MDCR_SPD32_LEGACY 0x0
#define MDCR_SPD32_DISABLE 0x2
#define MDCR_SPD32_ENABLE 0x3
#define MDCR_SDD_BIT (1 << 16)
#define MDCR_DEF_VAL (MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE))
/* HCR definitions */
#define HCR_RW_BIT (1ull << 31)
#define HCR_AMO_BIT (1 << 5)