rockchip: enable or disable auto power down base on frequency
add auto_pd_dis_freq parameter, we can pass a frequency from kernel to disable or enable ddr auto power down function. Change-Id: Ie30914701336c59047c380381c6b75dd76a89562
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fe877779ee
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863edcea43
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@ -90,6 +90,7 @@ static struct rk3399_ddr_publ_regs *const rk3399_ddr_publ[2] = {
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struct rk3399_dram_status {
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uint32_t current_index;
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uint32_t index_freq[2];
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uint32_t low_power_stat;
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struct timing_related_config timing_config;
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struct drv_odt_lp_config drv_odt_lp_cfg;
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};
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@ -2215,9 +2216,6 @@ uint32_t exit_low_power(void)
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continue;
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/* exit stdby mode */
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low_power |=
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((read_32(&rk3399_ddr_cic->cic_ctrl1) >>
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channel) & 0x1) << (3 + 8 * channel);
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write_32(&rk3399_ddr_cic->cic_ctrl1,
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(1 << (channel + 16)) | (0 << channel));
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/* exit external self-refresh */
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@ -2229,9 +2227,7 @@ uint32_t exit_low_power(void)
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(1 << channel)))
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;
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/* exit auto low-power */
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low_power |= (read_32(&ddr_pctl_regs->denali_ctl[101]) &
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0xf) << (8 * channel);
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clrbits_32(&ddr_pctl_regs->denali_ctl[101], 0xf);
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clrbits_32(&ddr_pctl_regs->denali_ctl[101], 0x7);
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/* lp_cmd to exit */
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if (((read_32(&ddr_pctl_regs->denali_ctl[100]) >> 24) &
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0x7f) != 0x40) {
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@ -2266,7 +2262,7 @@ void resume_low_power(uint32_t low_power)
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val = (low_power >> (4 + 8 * channel)) & 0x1;
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setbits_32(PMU_BASE + PMU_SFT_CON, val << tmp);
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/* resume auto low-power */
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val = (low_power >> (8 * channel)) & 0xf;
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val = (low_power >> (8 * channel)) & 0x7;
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setbits_32(&ddr_pctl_regs->denali_ctl[101], val);
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/* resume stdby mode */
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val = (low_power >> (3 + 8 * channel)) & 0x1;
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@ -2329,6 +2325,7 @@ static void dram_low_power_config(struct drv_odt_lp_config *lp_config)
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uint32_t tmp, tmp1, i;
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uint32_t ch_cnt = rk3399_dram_status.timing_config.ch_cnt;
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uint32_t dram_type = rk3399_dram_status.timing_config.dram_type;
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uint32_t *low_power = &rk3399_dram_status.low_power_stat;
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if (dram_type == LPDDR4)
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tmp = (lp_config->srpd_lite_idle << 16) |
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@ -2341,6 +2338,8 @@ static void dram_low_power_config(struct drv_odt_lp_config *lp_config)
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else
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tmp1 = (3 << 16) | (0x7 << 8) | 7;
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*low_power = 0;
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for (i = 0; i < ch_cnt; i++) {
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write_32(&rk3399_ddr_pctl[i]->denali_ctl[102], tmp);
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clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[103], 0xffff,
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@ -2348,6 +2347,7 @@ static void dram_low_power_config(struct drv_odt_lp_config *lp_config)
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lp_config->sr_idle);
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clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[101],
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0x70f0f, tmp1);
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*low_power |= (7 << (8 * i));
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}
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/* standby idle */
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@ -2358,20 +2358,24 @@ static void dram_low_power_config(struct drv_odt_lp_config *lp_config)
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write_32(GRF_BASE + GRF_DDRC1_CON1,
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(((0x1<<4) | (0x1<<5) | (0x1<<6) | (0x1<<7)) << 16) |
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((0x1<<4) | (0x0<<5) | (0x1<<6) | (0x1<<7)));
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if (lp_config->standby_idle)
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if (lp_config->standby_idle) {
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tmp = 0x002a002a;
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else
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*low_power |= (1 << 11);
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} else {
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tmp = 0;
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}
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write_32(&rk3399_ddr_cic->cic_ctrl1, tmp);
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}
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write_32(GRF_BASE + GRF_DDRC0_CON1,
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(((0x1<<4) | (0x1<<5) | (0x1<<6) | (0x1<<7)) << 16) |
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((0x1<<4) | (0x0<<5) | (0x1<<6) | (0x1<<7)));
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if (lp_config->standby_idle)
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if (lp_config->standby_idle) {
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tmp = 0x00150015;
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else
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*low_power |= (1 << 3);
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} else {
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tmp = 0;
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}
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write_32(&rk3399_ddr_cic->cic_ctrl1, tmp);
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}
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@ -2513,6 +2517,10 @@ uint64_t ddr_set_rate(uint64_t hz)
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gen_rk3399_set_odt(0);
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rk3399_dram_status.current_index = index;
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if (mhz < dts_parameter.auto_pd_dis_freq)
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low_power |= rk3399_dram_status.low_power_stat;
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resume_low_power(low_power);
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out:
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return mhz;
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@ -229,34 +229,35 @@ struct rk3399_sdram_default_config {
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};
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struct ddr_dts_config_timing {
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uint32_t ddr3_speed_bin;
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uint32_t pd_idle;
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uint32_t sr_idle;
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uint32_t sr_mc_gate_idle;
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uint32_t srpd_lite_idle;
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uint32_t standby_idle;
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uint32_t ddr3_dll_dis_freq;
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uint32_t phy_dll_dis_freq;
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uint32_t ddr3_odt_dis_freq;
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uint32_t ddr3_drv;
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uint32_t ddr3_odt;
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uint32_t phy_ddr3_ca_drv;
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uint32_t phy_ddr3_dq_drv;
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uint32_t phy_ddr3_odt;
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uint32_t lpddr3_odt_dis_freq;
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uint32_t lpddr3_drv;
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uint32_t lpddr3_odt;
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uint32_t phy_lpddr3_ca_drv;
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uint32_t phy_lpddr3_dq_drv;
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uint32_t phy_lpddr3_odt;
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uint32_t lpddr4_odt_dis_freq;
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uint32_t lpddr4_drv;
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uint32_t lpddr4_dq_odt;
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uint32_t lpddr4_ca_odt;
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uint32_t phy_lpddr4_ca_drv;
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uint32_t phy_lpddr4_ck_cs_drv;
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uint32_t phy_lpddr4_dq_drv;
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uint32_t phy_lpddr4_odt;
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unsigned int ddr3_speed_bin;
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unsigned int pd_idle;
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unsigned int sr_idle;
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unsigned int sr_mc_gate_idle;
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unsigned int srpd_lite_idle;
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unsigned int standby_idle;
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unsigned int auto_pd_dis_freq;
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unsigned int ddr3_dll_dis_freq;
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unsigned int phy_dll_dis_freq;
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unsigned int ddr3_odt_dis_freq;
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unsigned int ddr3_drv;
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unsigned int ddr3_odt;
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unsigned int phy_ddr3_ca_drv;
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unsigned int phy_ddr3_dq_drv;
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unsigned int phy_ddr3_odt;
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unsigned int lpddr3_odt_dis_freq;
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unsigned int lpddr3_drv;
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unsigned int lpddr3_odt;
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unsigned int phy_lpddr3_ca_drv;
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unsigned int phy_lpddr3_dq_drv;
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unsigned int phy_lpddr3_odt;
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unsigned int lpddr4_odt_dis_freq;
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unsigned int lpddr4_drv;
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unsigned int lpddr4_dq_odt;
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unsigned int lpddr4_ca_odt;
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unsigned int phy_lpddr4_ca_drv;
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unsigned int phy_lpddr4_ck_cs_drv;
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unsigned int phy_lpddr4_dq_drv;
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unsigned int phy_lpddr4_odt;
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uint32_t available;
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};
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