nxp: add dcfg driver
NXP SoC needs Device Configuration driver to fetch the current SoC configuration. Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: Ie17cca01a8eb9a6f5feebb093756f577692432bf
This commit is contained in:
Pankaj Gupta
parent
0499215e1d
commit
86b1b89fbf
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/*
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* Copyright 2020 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#include <common/debug.h>
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#include "dcfg.h"
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#include <lib/mmio.h>
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#ifdef NXP_SFP_ENABLED
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#include <sfp.h>
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#endif
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static soc_info_t soc_info = {0};
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static devdisr5_info_t devdisr5_info = {0};
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static dcfg_init_info_t *dcfg_init_info;
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/* Read the PORSR1 register */
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uint32_t read_reg_porsr1(void)
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{
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unsigned int *porsr1_addr = NULL;
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if (dcfg_init_info->porsr1 != 0U) {
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return dcfg_init_info->porsr1;
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}
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porsr1_addr = (void *)
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(dcfg_init_info->g_nxp_dcfg_addr + DCFG_PORSR1_OFFSET);
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dcfg_init_info->porsr1 = gur_in32(porsr1_addr);
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return dcfg_init_info->porsr1;
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}
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const soc_info_t *get_soc_info(void)
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{
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uint32_t reg;
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if (soc_info.is_populated == true) {
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return (const soc_info_t *) &soc_info;
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}
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reg = gur_in32(dcfg_init_info->g_nxp_dcfg_addr + DCFG_SVR_OFFSET);
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soc_info.mfr_id = (reg & SVR_MFR_ID_MASK) >> SVR_MFR_ID_SHIFT;
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#if defined(CONFIG_CHASSIS_3_2)
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soc_info.family = (reg & SVR_FAMILY_MASK) >> SVR_FAMILY_SHIFT;
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soc_info.dev_id = (reg & SVR_DEV_ID_MASK) >> SVR_DEV_ID_SHIFT;
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#endif
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/* zero means SEC enabled. */
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soc_info.sec_enabled =
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(((reg & SVR_SEC_MASK) >> SVR_SEC_SHIFT) == 0) ? true : false;
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soc_info.personality = (reg & SVR_PERSONALITY_MASK)
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>> SVR_PERSONALITY_SHIFT;
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soc_info.maj_ver = (reg & SVR_MAJ_VER_MASK) >> SVR_MAJ_VER_SHIFT;
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soc_info.min_ver = reg & SVR_MIN_VER_MASK;
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soc_info.is_populated = true;
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return (const soc_info_t *) &soc_info;
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}
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void dcfg_init(dcfg_init_info_t *dcfg_init_data)
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{
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dcfg_init_info = dcfg_init_data;
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read_reg_porsr1();
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get_soc_info();
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}
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bool is_sec_enabled(void)
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{
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return soc_info.sec_enabled;
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}
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const devdisr5_info_t *get_devdisr5_info(void)
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{
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uint32_t reg;
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if (devdisr5_info.is_populated == true)
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return (const devdisr5_info_t *) &devdisr5_info;
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reg = gur_in32(dcfg_init_info->g_nxp_dcfg_addr + DCFG_DEVDISR5_OFFSET);
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#if defined(CONFIG_CHASSIS_3_2)
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devdisr5_info.ddrc1_present = (reg & DISR5_DDRC1_MASK) ? 0 : 1;
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devdisr5_info.ddrc2_present = (reg & DISR5_DDRC2_MASK) ? 0 : 1;
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devdisr5_info.ocram_present = (reg & DISR5_OCRAM_MASK) ? 0 : 1;
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#elif defined(CONFIG_CHASSIS_2)
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devdisr5_info.ddrc1_present = (reg & DISR5_DDRC1_MASK) ? 0 : 1;
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devdisr5_info.ocram_present = (reg & DISR5_OCRAM_MASK) ? 0 : 1;
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#endif
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devdisr5_info.is_populated = true;
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return (const devdisr5_info_t *) &devdisr5_info;
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}
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int get_clocks(struct sysinfo *sys)
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{
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unsigned int *rcwsr0 = NULL;
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const unsigned long sysclk = dcfg_init_info->nxp_sysclk_freq;
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const unsigned long ddrclk = dcfg_init_info->nxp_ddrclk_freq;
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rcwsr0 = (void *)(dcfg_init_info->g_nxp_dcfg_addr + RCWSR0_OFFSET);
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sys->freq_platform = sysclk;
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sys->freq_ddr_pll0 = ddrclk;
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sys->freq_ddr_pll1 = ddrclk;
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sys->freq_platform *= (gur_in32(rcwsr0) >>
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RCWSR0_SYS_PLL_RAT_SHIFT) &
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RCWSR0_SYS_PLL_RAT_MASK;
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sys->freq_platform /= dcfg_init_info->nxp_plat_clk_divider;
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sys->freq_ddr_pll0 *= (gur_in32(rcwsr0) >>
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RCWSR0_MEM_PLL_RAT_SHIFT) &
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RCWSR0_MEM_PLL_RAT_MASK;
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sys->freq_ddr_pll1 *= (gur_in32(rcwsr0) >>
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RCWSR0_MEM2_PLL_RAT_SHIFT) &
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RCWSR0_MEM2_PLL_RAT_MASK;
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if (sys->freq_platform == 0) {
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return 1;
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} else {
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return 0;
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}
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}
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#ifdef NXP_SFP_ENABLED
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/*******************************************************************************
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* Returns true if secur eboot is enabled on board
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* mode = 0 (development mode - sb_en = 1)
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* mode = 1 (production mode - ITS = 1)
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******************************************************************************/
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bool check_boot_mode_secure(uint32_t *mode)
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{
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uint32_t val = 0U;
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uint32_t *rcwsr = NULL;
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*mode = 0U;
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if (sfp_check_its() == 1) {
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/* ITS =1 , Production mode */
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*mode = 1U;
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return true;
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}
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rcwsr = (void *)(dcfg_init_info->g_nxp_dcfg_addr + RCWSR_SB_EN_OFFSET);
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val = (gur_in32(rcwsr) >> RCWSR_SBEN_SHIFT) &
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RCWSR_SBEN_MASK;
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if (val == RCWSR_SBEN_MASK) {
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*mode = 0U;
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return true;
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}
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return false;
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}
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#endif
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void error_handler(int error_code)
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{
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/* Dump error code in SCRATCH4 register */
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INFO("Error in Fuse Provisioning: %x\n", error_code);
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gur_out32((void *)
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(dcfg_init_info->g_nxp_dcfg_addr + DCFG_SCRATCH4_OFFSET),
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error_code);
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}
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@ -0,0 +1,85 @@
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/*
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* Copyright 2018-2020 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef DCFG_H
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#define DCFG_H
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#include <endian.h>
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#if defined(CONFIG_CHASSIS_2)
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#include <dcfg_lsch2.h>
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#elif defined(CONFIG_CHASSIS_3_2)
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#include <dcfg_lsch3.h>
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#endif
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#ifdef NXP_GUR_BE
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#define gur_in32(a) bswap32(mmio_read_32((uintptr_t)(a)))
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#define gur_out32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v))
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#elif defined(NXP_GUR_LE)
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#define gur_in32(a) mmio_read_32((uintptr_t)(a))
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#define gur_out32(a, v) mmio_write_32((uintptr_t)(a), v)
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#else
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#error Please define CCSR GUR register endianness
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#endif
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typedef struct {
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bool is_populated;
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uint8_t mfr_id;
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#if defined(CONFIG_CHASSIS_3_2)
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uint8_t family;
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uint8_t dev_id;
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#endif
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uint8_t personality;
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bool sec_enabled;
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uint8_t maj_ver;
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uint8_t min_ver;
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} soc_info_t;
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typedef struct {
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bool is_populated;
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uint8_t ocram_present;
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uint8_t ddrc1_present;
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#if defined(CONFIG_CHASSIS_3_2)
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uint8_t ddrc2_present;
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#endif
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} devdisr5_info_t;
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typedef struct {
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uint32_t porsr1;
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uintptr_t g_nxp_dcfg_addr;
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unsigned long nxp_sysclk_freq;
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unsigned long nxp_ddrclk_freq;
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unsigned int nxp_plat_clk_divider;
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} dcfg_init_info_t;
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struct sysinfo {
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unsigned long freq_platform;
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unsigned long freq_ddr_pll0;
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unsigned long freq_ddr_pll1;
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};
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int get_clocks(struct sysinfo *sys);
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/* Read the PORSR1 register */
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uint32_t read_reg_porsr1(void);
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/*******************************************************************************
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* Returns true if secur eboot is enabled on board
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* mode = 0 (development mode - sb_en = 1)
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* mode = 1 (production mode - ITS = 1)
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******************************************************************************/
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bool check_boot_mode_secure(uint32_t *mode);
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const soc_info_t *get_soc_info();
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const devdisr5_info_t *get_devdisr5_info();
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void dcfg_init(dcfg_init_info_t *dcfg_init_data);
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bool is_sec_enabled(void);
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void error_handler(int error_code);
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#endif /* DCFG_H */
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@ -0,0 +1,28 @@
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#
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# Copyright 2020 NXP
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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ifeq (${ADD_DCFG},)
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ADD_DCFG := 1
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DCFG_DRIVERS_PATH := ${PLAT_DRIVERS_PATH}/dcfg
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PLAT_INCLUDES += -I$(DCFG_DRIVERS_PATH)
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DCFG_SOURCES += $(DCFG_DRIVERS_PATH)/dcfg.c
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ifeq (${BL_COMM_DCFG_NEEDED},yes)
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BL_COMMON_SOURCES += ${DCFG_SOURCES}
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else
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ifeq (${BL2_DCFG_NEEDED},yes)
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BL2_SOURCES += ${DCFG_SOURCES}
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endif
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ifeq (${BL31_DCFG_NEEDED},yes)
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BL31_SOURCES += ${DCFG_SOURCES}
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endif
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endif
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endif
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@ -0,0 +1,79 @@
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/*
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* Copyright 2020 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef DCFG_LSCH2_H
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#define DCFG_LSCH2_H
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/* dcfg block register offsets and bitfields */
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#define DCFG_PORSR1_OFFSET 0x00
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#define DCFG_DEVDISR1_OFFSET 0x070
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#define DCFG_DEVDISR4_OFFSET 0x07C
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#define DCFG_DEVDISR5_OFFSET 0x080
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#define DCFG_COREDISR_OFFSET 0x094
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#define RCWSR0_OFFSET 0x100
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#define RCWSR5_OFFSET 0x118
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#define DCFG_BOOTLOCPTRL_OFFSET 0x400
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#define DCFG_BOOTLOCPTRH_OFFSET 0x404
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#define DCFG_COREDISABLEDSR_OFFSET 0x990
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#define DCFG_SCRATCH4_OFFSET 0x20C
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#define DCFG_SVR_OFFSET 0x0A4
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#define DCFG_BRR_OFFSET 0x0E4
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#define DCFG_RSTCR_OFFSET 0x0B0
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#define RSTCR_RESET_REQ 0x2
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#define DCFG_RSTRQSR1_OFFSET 0x0C8
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#define DCFG_RSTRQMR1_OFFSET 0x0C0
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/* DCFG DCSR Macros */
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#define DCFG_DCSR_PORCR1_OFFSET 0x0
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#define SVR_MFR_ID_MASK 0xF0000000
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#define SVR_MFR_ID_SHIFT 28
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#define SVR_FAMILY_MASK 0xF000000
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#define SVR_FAMILY_SHIFT 24
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#define SVR_DEV_ID_MASK 0x3F0000
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#define SVR_DEV_ID_SHIFT 16
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#define SVR_PERSONALITY_MASK 0x3E00
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#define SVR_PERSONALITY_SHIFT 9
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#define SVR_SEC_MASK 0x100
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#define SVR_SEC_SHIFT 8
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#define SVR_MAJ_VER_MASK 0xF0
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#define SVR_MAJ_VER_SHIFT 4
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#define SVR_MIN_VER_MASK 0xF
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#define DISR5_DDRC1_MASK 0x1
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#define DISR5_OCRAM_MASK 0x40
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/* DCFG regsiters bit masks */
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#define RCWSR0_SYS_PLL_RAT_SHIFT 25
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#define RCWSR0_SYS_PLL_RAT_MASK 0x1f
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#define RCWSR0_MEM_PLL_RAT_SHIFT 16
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#define RCWSR0_MEM_PLL_RAT_MASK 0x3f
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#define RCWSR0_MEM2_PLL_RAT_SHIFT 18
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#define RCWSR0_MEM2_PLL_RAT_MASK 0x3f
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#define RCWSR_SB_EN_OFFSET RCWSR5_OFFSET
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#define RCWSR_SBEN_MASK 0x1
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#define RCWSR_SBEN_SHIFT 21
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/* RCW SRC NAND */
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#define RCW_SRC_NAND_MASK (0x100)
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#define RCW_SRC_NAND_VAL (0x100)
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#define NAND_RESERVED_MASK (0xFC)
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#define NAND_RESERVED_1 (0x0)
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#define NAND_RESERVED_2 (0x80)
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/* RCW SRC NOR */
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#define RCW_SRC_NOR_MASK (0x1F0)
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#define NOR_8B_VAL (0x10)
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#define NOR_16B_VAL (0x20)
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#define SD_VAL (0x40)
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#define QSPI_VAL1 (0x44)
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#define QSPI_VAL2 (0x45)
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#endif /* DCFG_LSCH2_H */
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@ -0,0 +1,77 @@
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/*
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* Copyright 2020 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef DCFG_LSCH3_H
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#define DCFG_LSCH3_H
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/* dcfg block register offsets and bitfields */
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#define DCFG_PORSR1_OFFSET 0x00
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#define DCFG_DEVDISR1_OFFSET 0x70
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#define DCFG_DEVDISR1_SEC (1 << 22)
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#define DCFG_DEVDISR2_OFFSET 0x74
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#define DCFG_DEVDISR3_OFFSET 0x78
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#define DCFG_DEVDISR3_QBMAIN (1 << 12)
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#define DCFG_DEVDISR4_OFFSET 0x7C
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#define DCFG_DEVDISR4_SPI_QSPI (1 << 4 | 1 << 5)
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#define DCFG_DEVDISR5_OFFSET 0x80
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#define DISR5_DDRC1_MASK 0x1
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#define DISR5_DDRC2_MASK 0x2
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#define DISR5_OCRAM_MASK 0x1000
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#define DEVDISR5_MASK_ALL_MEM 0x00001003
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#define DEVDISR5_MASK_DDR 0x00000003
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#define DEVDISR5_MASK_DBG 0x00000400
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#define DCFG_DEVDISR6_OFFSET 0x84
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//#define DEVDISR6_MASK 0x00000001
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#define DCFG_COREDISR_OFFSET 0x94
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#define DCFG_SVR_OFFSET 0x0A4
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#define SVR_MFR_ID_MASK 0xF0000000
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#define SVR_MFR_ID_SHIFT 28
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#define SVR_FAMILY_MASK 0xF000000
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#define SVR_FAMILY_SHIFT 24
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#define SVR_DEV_ID_MASK 0x3F0000
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#define SVR_DEV_ID_SHIFT 16
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#define SVR_PERSONALITY_MASK 0x3E00
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#define SVR_PERSONALITY_SHIFT 9
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#define SVR_SEC_MASK 0x100
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#define SVR_SEC_SHIFT 8
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#define SVR_MAJ_VER_MASK 0xF0
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#define SVR_MAJ_VER_SHIFT 4
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#define SVR_MIN_VER_MASK 0xF
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#define RCWSR0_OFFSET 0x100
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#define RCWSR0_SYS_PLL_RAT_SHIFT 2
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#define RCWSR0_SYS_PLL_RAT_MASK 0x1f
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#define RCWSR0_MEM_PLL_RAT_SHIFT 10
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#define RCWSR0_MEM_PLL_RAT_MASK 0x3f
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#define RCWSR0_MEM2_PLL_RAT_SHIFT 18
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#define RCWSR0_MEM2_PLL_RAT_MASK 0x3f
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#define RCWSR5_OFFSET 0x110
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#define RCWSR9_OFFSET 0x120
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#define RCWSR_SB_EN_OFFSET RCWSR9_OFFSET
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#define RCWSR_SBEN_MASK 0x1
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#define RCWSR_SBEN_SHIFT 10
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#define RCW_SR27_OFFSET 0x168
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/* DCFG register to dump error code */
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#define DCFG_SCRATCH4_OFFSET 0x20C
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#define DCFG_SCRATCHRW5_OFFSET 0x210
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#define DCFG_SCRATCHRW6_OFFSET 0x214
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#define DCFG_SCRATCHRW7_OFFSET 0x218
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#define DCFG_BOOTLOCPTRL_OFFSET 0x400
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#define DCFG_BOOTLOCPTRH_OFFSET 0x404
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#define DCFG_COREDISABLEDSR_OFFSET 0x990
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#endif /* DCFG_LSCH3_H */
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
/*
|
||||
* Copyright 2020 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef SCFG_H
|
||||
#define SCFG_H
|
||||
|
||||
#ifdef CONFIG_CHASSIS_2
|
||||
|
||||
/* SCFG register offsets */
|
||||
#define SCFG_CORE0_SFT_RST_OFFSET 0x0130
|
||||
#define SCFG_SNPCNFGCR_OFFSET 0x01A4
|
||||
#define SCFG_CORESRENCR_OFFSET 0x0204
|
||||
#define SCFG_RVBAR0_0_OFFSET 0x0220
|
||||
#define SCFG_RVBAR0_1_OFFSET 0x0224
|
||||
#define SCFG_COREBCR_OFFSET 0x0680
|
||||
#define SCFG_RETREQCR_OFFSET 0x0424
|
||||
|
||||
#define SCFG_COREPMCR_OFFSET 0x042C
|
||||
#define COREPMCR_WFIL2 0x1
|
||||
|
||||
#define SCFG_GIC400_ADDR_ALIGN_OFFSET 0x0188
|
||||
#define SCFG_BOOTLOCPTRH_OFFSET 0x0600
|
||||
#define SCFG_BOOTLOCPTRL_OFFSET 0x0604
|
||||
#define SCFG_SCRATCHRW2_OFFSET 0x0608
|
||||
#define SCFG_SCRATCHRW3_OFFSET 0x060C
|
||||
|
||||
/* SCFG bit fields */
|
||||
#define SCFG_SNPCNFGCR_SECRDSNP 0x80000000
|
||||
#define SCFG_SNPCNFGCR_SECWRSNP 0x40000000
|
||||
#endif /* CONFIG_CHASSIS_2 */
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
#include <endian.h>
|
||||
#include <lib/mmio.h>
|
||||
|
||||
#ifdef NXP_SCFG_BE
|
||||
#define scfg_in32(a) bswap32(mmio_read_32((uintptr_t)(a)))
|
||||
#define scfg_out32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v))
|
||||
#define scfg_setbits32(a, v) mmio_setbits_32((uintptr_t)(a), v)
|
||||
#define scfg_clrbits32(a, v) mmio_clrbits_32((uintptr_t)(a), v)
|
||||
#define scfg_clrsetbits32(a, clear, set) \
|
||||
mmio_clrsetbits_32((uintptr_t)(a), clear, set)
|
||||
#elif defined(NXP_GUR_LE)
|
||||
#define scfg_in32(a) mmio_read_32((uintptr_t)(a))
|
||||
#define scfg_out32(a, v) mmio_write_32((uintptr_t)(a), v)
|
||||
#define scfg_setbits32(a, v) mmio_setbits_32((uintptr_t)(a), v)
|
||||
#define scfg_clrbits32(a, v) mmio_clrbits_32((uintptr_t)(a), v)
|
||||
#define scfg_clrsetbits32(a, clear, set) \
|
||||
mmio_clrsetbits_32((uintptr_t)(a), clear, set)
|
||||
#else
|
||||
#error Please define CCSR SCFG register endianness
|
||||
#endif
|
||||
#endif /* __ASSEMBLER__ */
|
||||
|
||||
#endif /* SCFG_H */
|
||||
Loading…
Reference in New Issue