diff --git a/plat/nvidia/tegra/include/t210/tegra_def.h b/plat/nvidia/tegra/include/t210/tegra_def.h index 8d71cae83..cdd7ce79b 100644 --- a/plat/nvidia/tegra/include/t210/tegra_def.h +++ b/plat/nvidia/tegra/include/t210/tegra_def.h @@ -153,6 +153,10 @@ #define MC_VIDEO_PROTECT_BASE_LO U(0x648) #define MC_VIDEO_PROTECT_SIZE_MB U(0x64c) +/* SMMU configuration registers*/ +#define MC_SMMU_PPCS_ASID_0 0x270UL +#define PPCS_SMMU_ENABLE (0x1U << 31) + /******************************************************************************* * Tegra SE constants ******************************************************************************/ diff --git a/plat/nvidia/tegra/soc/t210/drivers/se/security_engine.c b/plat/nvidia/tegra/soc/t210/drivers/se/security_engine.c index c59ec75f1..64c17364b 100644 --- a/plat/nvidia/tegra/soc/t210/drivers/se/security_engine.c +++ b/plat/nvidia/tegra/soc/t210/drivers/se/security_engine.c @@ -401,6 +401,14 @@ void tegra_se_init(void) int32_t tegra_se_suspend(void) { int32_t ret = 0; + uint32_t val = 0; + + /* SE does not use SMMU in EL3, disable SMMU. + * This will be re-enabled by kernel on resume */ + val = mmio_read_32(TEGRA_MC_BASE + MC_SMMU_PPCS_ASID_0); + val &= ~PPCS_SMMU_ENABLE; + mmio_write_32(TEGRA_MC_BASE + MC_SMMU_PPCS_ASID_0, val); + /* Atomic context save se2 and pka1 */ INFO("%s: SE2/PKA1 atomic context save\n", __func__);