nxp: adding support of soc lx2160a
* NXP SoC is 16 A-72 core SoC. * SoC specific defines are defined in: - soc.def - soc.h * Called for BL2 and BL31 setup, SoC specific setup are implemented in: - soc.c * platform specific helper functions implemented at: - aarch64/lx2160a_helpers.S * platform specific functions used by 'plat/nxp/commpon/psci', etc. are implemented at: - aarch64/lx2160a.S * platform specific implementation for handling PSCI_SYSTEM_RESET2: - aarch64/lx2160a_warm_rst.S Signed-off-by: rocket <rod.dorris@nxp.com> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: Ib40086f9d9079ed9b22967baff518c6df9f408b8
This commit is contained in:
Pankaj Gupta
parent
dc05e50b8d
commit
87056d3193
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/*
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* Copyright 2018-2020 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <platform_def.h>
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.globl plat_secondary_cold_boot_setup
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.globl plat_is_my_cpu_primary
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.globl plat_reset_handler
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.globl platform_mem_init
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func platform_mem1_init
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ret
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endfunc platform_mem1_init
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func platform_mem_init
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ret
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endfunc platform_mem_init
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func apply_platform_errata
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ret
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endfunc apply_platform_errata
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func plat_reset_handler
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mov x29, x30
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bl apply_platform_errata
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#if defined(IMAGE_BL31)
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ldr x0, =POLICY_SMMU_PAGESZ_64K
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cbz x0, 1f
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/* Set the SMMU page size in the sACR register */
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bl _set_smmu_pagesz_64
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#endif
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1:
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mov x30, x29
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ret
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endfunc plat_reset_handler
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/* void plat_secondary_cold_boot_setup (void);
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*
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* This function performs any platform specific actions
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* needed for a secondary cpu after a cold reset e.g
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* mark the cpu's presence, mechanism to place it in a
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* holding pen etc.
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*/
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func plat_secondary_cold_boot_setup
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/* lx2160a does not do cold boot for secondary CPU */
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cb_panic:
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b cb_panic
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endfunc plat_secondary_cold_boot_setup
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/* unsigned int plat_is_my_cpu_primary (void);
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*
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* Find out whether the current cpu is the primary
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* cpu.
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*/
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func plat_is_my_cpu_primary
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mrs x0, mpidr_el1
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and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
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cmp x0, 0x0
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cset w0, eq
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ret
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endfunc plat_is_my_cpu_primary
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@ -0,0 +1,229 @@
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/*
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* Copyright 2020 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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.section .text, "ax"
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#include <asm_macros.S>
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#ifndef NXP_COINED_BB
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#include <flash_info.h>
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#include <fspi.h>
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#endif
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#include <regs.h>
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#ifdef NXP_COINED_BB
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#include <snvs.h>
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#endif
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#include <plat_warm_rst.h>
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#include <platform_def.h>
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#define SDRAM_CFG 0x110
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#define SDRAM_CFG_2 0x114
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#define SDRAM_MD_CNTL 0x120
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#define SDRAM_INTERVAL 0x124
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#define TIMING_CFG_10 0x258
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#define DEBUG_2 0xF04
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#define DEBUG_26 0xF64
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#define DDR_DSR2 0xB24
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#define DDR_CNTRLR_2 0x2
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#define COUNT_100 1000
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.globl _soc_sys_warm_reset
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.align 12
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func _soc_sys_warm_reset
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mov x3, xzr
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b touch_line0
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start_line0:
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mov x3, #1
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mov x2, #NUM_OF_DDRC
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ldr x1, =NXP_DDR_ADDR
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1:
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ldr w0, [x1, #SDRAM_CFG]
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orr w0, w0, #SDRAM_CFG_MEM_HLT
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str w0, [x1, #SDRAM_CFG]
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2:
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ldr w0, [x1, #DEBUG_2]
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and w0, w0, #DDR_DBG_2_MEM_IDLE
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cbz w0, 2b
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ldr w0, [x1, #DEBUG_26]
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orr w0, w0, #DDR_DEBUG_26_BIT_12
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orr w0, w0, #DDR_DEBUG_26_BIT_13
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orr w0, w0, #DDR_DEBUG_26_BIT_14
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touch_line0:
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cbz x3, touch_line1
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orr w0, w0, #DDR_DEBUG_26_BIT_15
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orr w0, w0, #DDR_DEBUG_26_BIT_16
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str w0, [x1, #DEBUG_26]
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ldr w0, [x1, #SDRAM_CFG_2]
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orr w0, w0, #SDRAM_CFG2_FRC_SR
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str w0, [x1, #SDRAM_CFG_2]
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3:
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ldr w0, [x1, #DDR_DSR2]
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orr w0, w0, #DDR_DSR_2_PHY_INIT_CMPLT
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str w0, [x1, #DDR_DSR2]
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ldr w0, [x1, #DDR_DSR2]
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and w0, w0, #DDR_DSR_2_PHY_INIT_CMPLT
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cbnz w0, 3b
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ldr w0, [x1, #SDRAM_INTERVAL]
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and w0, w0, #SDRAM_INTERVAL_REFINT_CLEAR
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str w0, [x1, #SDRAM_INTERVAL]
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touch_line1:
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cbz x3, touch_line2
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ldr w0, [x1, #SDRAM_MD_CNTL]
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orr w0, w0, #MD_CNTL_CKE(1)
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orr w0, w0, #MD_CNTL_MD_EN
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str w0, [x1, #SDRAM_MD_CNTL]
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ldr w0, [x1, #TIMING_CFG_10]
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orr w0, w0, #DDR_TIMING_CFG_10_T_STAB
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str w0, [x1, #TIMING_CFG_10]
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ldr w0, [x1, #SDRAM_CFG_2]
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and w0, w0, #SDRAM_CFG2_FRC_SR_CLEAR
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str w0, [x1, #SDRAM_CFG_2]
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4:
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ldr w0, [x1, #DDR_DSR2]
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and w0, w0, #DDR_DSR_2_PHY_INIT_CMPLT
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cbz w0, 4b
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nop
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touch_line2:
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cbz x3, touch_line3
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ldr w0, [x1, #DEBUG_26]
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orr w0, w0, #DDR_DEBUG_26_BIT_25
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and w0, w0, #DDR_DEBUG_26_BIT_24_CLEAR
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str w0, [x1, #DEBUG_26]
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cmp x2, #DDR_CNTRLR_2
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b.ne 5f
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ldr x1, =NXP_DDR2_ADDR
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mov x2, xzr
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b 1b
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5:
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mov x5, xzr
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6:
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add x5, x5, #1
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cmp x5, #COUNT_100
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b.ne 6b
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nop
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touch_line3:
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cbz x3, touch_line4
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#ifdef NXP_COINED_BB
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ldr x1, =NXP_SNVS_ADDR
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ldr w0, [x1, #NXP_APP_DATA_LP_GPR_OFFSET]
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/* On Warm Boot is enabled, then zeroth bit
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* of SNVS LP GPR register 0 will used
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* to save the status of warm-reset as a cause.
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*/
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orr w0, w0, #(1 << NXP_LPGPR_ZEROTH_BIT)
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/* write back */
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str w0, [x1, #NXP_APP_DATA_LP_GPR_OFFSET]
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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touch_line4:
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cbz x3, touch_line6
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#elif !(ERLY_WRM_RST_FLG_FLSH_UPDT)
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ldr x1, =NXP_FLEXSPI_ADDR
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ldr w0, [x1, #FSPI_IPCMD]
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orr w0, w0, #FSPI_IPCMD_TRG_MASK
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str w0, [x1, #FSPI_IPCMD]
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7:
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ldr w0, [x1, #FSPI_INTR]
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and w0, w0, #FSPI_INTR_IPCMDDONE_MASK
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cmp w0, #0
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b.eq 7b
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ldr w0, [x1, #FSPI_IPTXFCR]
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orr w0, w0, #FSPI_IPTXFCR_CLR
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str w0, [x1, #FSPI_IPTXFCR]
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ldr w0, [x1, #FSPI_INTR]
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orr w0, w0, #FSPI_INTR_IPCMDDONE_MASK
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str w0, [x1, #FSPI_INTR]
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nop
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touch_line4:
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cbz x3, touch_line5
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/* flexspi driver has an api
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* is_flash_busy().
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* Impelementation of the api will not
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* fit-in in 1 cache line.
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* instead a nop-cycles are introduced to
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* simulate the wait time for flash write
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* completion.
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*
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* Note: This wait time varies from flash to flash.
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*/
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mov x0, #FLASH_WR_COMP_WAIT_BY_NOP_COUNT
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8:
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sub x0, x0, #1
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nop
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cmp x0, #0
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b.ne 8b
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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touch_line5:
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cbz x3, touch_line6
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#endif
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ldr x2, =NXP_RST_ADDR
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/* clear the RST_REQ_MSK and SW_RST_REQ */
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mov w0, #0x00000000
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str w0, [x2, #RSTCNTL_OFFSET]
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/* initiate the sw reset request */
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mov w0, #SW_RST_REQ_INIT
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str w0, [x2, #RSTCNTL_OFFSET]
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/* In case this address range is mapped as cacheable,
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* flush the write out of the dcaches.
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*/
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add x2, x2, #RSTCNTL_OFFSET
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dc cvac, x2
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dsb st
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isb
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/* Function does not return */
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b .
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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touch_line6:
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cbz x3, start_line0
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endfunc _soc_sys_warm_reset
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@ -0,0 +1,142 @@
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/*
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* Copyright 2018-2020 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef _SOC_H
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#define _SOC_H
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/* Chassis specific defines - common across SoC's of a particular platform */
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#include <dcfg_lsch3.h>
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#include <soc_default_base_addr.h>
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#include <soc_default_helper_macros.h>
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#define NUM_DRAM_REGIONS 3
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#define NXP_DRAM0_ADDR 0x80000000
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#define NXP_DRAM0_MAX_SIZE 0x80000000 /* 2 GB */
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#define NXP_DRAM1_ADDR 0x2080000000
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#define NXP_DRAM1_MAX_SIZE 0x1F80000000 /* 126 G */
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#define NXP_DRAM2_ADDR 0x6000000000
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#define NXP_DRAM2_MAX_SIZE 0x2000000000 /* 128G */
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/*DRAM0 Size defined in platform_def.h */
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#define NXP_DRAM0_SIZE PLAT_DEF_DRAM0_SIZE
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#define DDR_PLL_FIX
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#define NXP_DDR_PHY1_ADDR 0x01400000
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#define NXP_DDR_PHY2_ADDR 0x01600000
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#if defined(IMAGE_BL31)
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#define LS_SYS_TIMCTL_BASE 0x2890000
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#ifdef LS_SYS_TIMCTL_BASE
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#define PLAT_LS_NSTIMER_FRAME_ID 0
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#define LS_CONFIG_CNTACR 1
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#endif
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#endif
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/* Start: Macros used by soc.c: get_boot_dev */
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#define PORSR1_RCW_MASK 0x07800000
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#define PORSR1_RCW_SHIFT 23
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#define SDHC1_VAL 0x8
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#define SDHC2_VAL 0x9
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#define I2C1_VAL 0xa
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#define FLEXSPI_NAND2K_VAL 0xc
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#define FLEXSPI_NAND4K_VAL 0xd
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#define FLEXSPI_NOR 0xf
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/* End: Macros used by soc.c: get_boot_dev */
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/* bits */
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/* SVR Definition */
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#define SVR_LX2160A 0x04
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#define SVR_LX2120A 0x14
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#define SVR_LX2080A 0x05
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/* Number of cores in platform */
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/* Used by common code for array initialization */
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#define NUMBER_OF_CLUSTERS 8
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#define CORES_PER_CLUSTER 2
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#define PLATFORM_CORE_COUNT NUMBER_OF_CLUSTERS * CORES_PER_CLUSTER
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/*
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* Required LS standard platform porting definitions
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* for CCN-508
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*/
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#define PLAT_CLUSTER_TO_CCN_ID_MAP 11, 15, 27, 31, 12, 28, 16, 0
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#define PLAT_6CLUSTER_TO_CCN_ID_MAP 11, 15, 27, 31, 12, 28
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/* Defines required for using XLAT tables from ARM common code */
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 40)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 40)
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/* Clock Divisors */
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#define NXP_PLATFORM_CLK_DIVIDER 2
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#define NXP_UART_CLK_DIVIDER 4
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/* Start: Macros used by lx2160a.S */
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#define MPIDR_AFFINITY0_MASK 0x00FF
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#define MPIDR_AFFINITY1_MASK 0xFF00
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#define CPUECTLR_DISABLE_TWALK_PREFETCH 0x4000000000
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#define CPUECTLR_INS_PREFETCH_MASK 0x1800000000
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#define CPUECTLR_DAT_PREFETCH_MASK 0x0300000000
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#define CPUECTLR_RET_8CLK 0x2
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#define OSDLR_EL1_DLK_LOCK 0x1
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#define CNTP_CTL_EL0_EN 0x1
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#define CNTP_CTL_EL0_IMASK 0x2
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/* set to 0 if the clusters are not symmetrical */
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#define SYMMETRICAL_CLUSTERS 1
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/* End: Macros used by lx2160a.S */
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/* Start: Macros used by lib/psci files */
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#define SYSTEM_PWR_DOMAINS 1
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#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \
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NUMBER_OF_CLUSTERS + \
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SYSTEM_PWR_DOMAINS)
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/* Power state coordination occurs at the system level */
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#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
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/* define retention state */
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#define PLAT_MAX_RET_STATE (PSCI_LOCAL_STATE_RUN + 1)
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/* define power-down state */
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#define PLAT_MAX_OFF_STATE (PLAT_MAX_RET_STATE + 1)
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/* End: Macros used by lib/psci files */
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/* Some data must be aligned on the biggest cache line size in the platform.
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* This is known only to the platform as it might have a combination of
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* integrated and external caches.
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*
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* CACHE_WRITEBACK_GRANULE is defined in soc.def
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*
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* One cache line needed for bakery locks on ARM platforms
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*/
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#define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE)
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#ifndef WDOG_RESET_FLAG
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#define WDOG_RESET_FLAG DEFAULT_SET_VALUE
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#endif
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#ifndef WARM_BOOT_SUCCESS
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#define WARM_BOOT_SUCCESS DEFAULT_SET_VALUE
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#endif
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#ifndef __ASSEMBLER__
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void set_base_freq_CNTFID0(void);
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void soc_init_start(void);
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void soc_init_finish(void);
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void soc_init_percpu(void);
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void _soc_set_start_addr(unsigned long addr);
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void _set_platform_security(void);
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#endif
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#endif /* _SOC_H */
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@ -0,0 +1,528 @@
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/*
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* Copyright 2018-2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#include <assert.h>
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#include <arch.h>
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#include <bl31/interrupt_mgmt.h>
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#include <caam.h>
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#include <cassert.h>
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#include <ccn.h>
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#include <common/debug.h>
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#include <dcfg.h>
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#ifdef I2C_INIT
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#include <i2c.h>
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#endif
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#include <lib/mmio.h>
|
||||
#include <lib/xlat_tables/xlat_tables_v2.h>
|
||||
#include <ls_interconnect.h>
|
||||
#ifdef POLICY_FUSE_PROVISION
|
||||
#include <nxp_gpio.h>
|
||||
#endif
|
||||
#if TRUSTED_BOARD_BOOT
|
||||
#include <nxp_smmu.h>
|
||||
#endif
|
||||
#include <nxp_timer.h>
|
||||
#include <plat_console.h>
|
||||
#include <plat_gic.h>
|
||||
#include <plat_tzc400.h>
|
||||
#include <pmu.h>
|
||||
#if defined(NXP_SFP_ENABLED)
|
||||
#include <sfp.h>
|
||||
#endif
|
||||
|
||||
#include <errata.h>
|
||||
#include <ls_interrupt_mgmt.h>
|
||||
#include "plat_common.h"
|
||||
#ifdef NXP_NV_SW_MAINT_LAST_EXEC_DATA
|
||||
#include <plat_nv_storage.h>
|
||||
#endif
|
||||
#ifdef NXP_WARM_BOOT
|
||||
#include <plat_warm_rst.h>
|
||||
#endif
|
||||
#include "platform_def.h"
|
||||
#include "soc.h"
|
||||
|
||||
static struct soc_type soc_list[] = {
|
||||
SOC_ENTRY(LX2160A, LX2160A, 8, 2),
|
||||
SOC_ENTRY(LX2080A, LX2080A, 8, 1),
|
||||
SOC_ENTRY(LX2120A, LX2120A, 6, 2),
|
||||
};
|
||||
|
||||
static dcfg_init_info_t dcfg_init_data = {
|
||||
.g_nxp_dcfg_addr = NXP_DCFG_ADDR,
|
||||
.nxp_sysclk_freq = NXP_SYSCLK_FREQ,
|
||||
.nxp_ddrclk_freq = NXP_DDRCLK_FREQ,
|
||||
.nxp_plat_clk_divider = NXP_PLATFORM_CLK_DIVIDER,
|
||||
};
|
||||
static const unsigned char master_to_6rn_id_map[] = {
|
||||
PLAT_6CLUSTER_TO_CCN_ID_MAP
|
||||
};
|
||||
|
||||
static const unsigned char master_to_rn_id_map[] = {
|
||||
PLAT_CLUSTER_TO_CCN_ID_MAP
|
||||
};
|
||||
|
||||
CASSERT(ARRAY_SIZE(master_to_rn_id_map) == NUMBER_OF_CLUSTERS,
|
||||
assert_invalid_cluster_count_for_ccn_variant);
|
||||
|
||||
static const ccn_desc_t plat_six_cluster_ccn_desc = {
|
||||
.periphbase = NXP_CCN_ADDR,
|
||||
.num_masters = ARRAY_SIZE(master_to_6rn_id_map),
|
||||
.master_to_rn_id_map = master_to_6rn_id_map
|
||||
};
|
||||
|
||||
static const ccn_desc_t plat_ccn_desc = {
|
||||
.periphbase = NXP_CCN_ADDR,
|
||||
.num_masters = ARRAY_SIZE(master_to_rn_id_map),
|
||||
.master_to_rn_id_map = master_to_rn_id_map
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* This function returns the number of clusters in the SoC
|
||||
******************************************************************************/
|
||||
static unsigned int get_num_cluster(void)
|
||||
{
|
||||
const soc_info_t *soc_info = get_soc_info();
|
||||
uint32_t num_clusters = NUMBER_OF_CLUSTERS;
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0U; i < ARRAY_SIZE(soc_list); i++) {
|
||||
if (soc_list[i].personality == soc_info->personality) {
|
||||
num_clusters = soc_list[i].num_clusters;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
VERBOSE("NUM of cluster = 0x%x\n", num_clusters);
|
||||
|
||||
return num_clusters;
|
||||
}
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* Function returns the base counter frequency
|
||||
* after reading the first entry at CNTFID0 (0x20 offset).
|
||||
*
|
||||
* Function is used by:
|
||||
* 1. ARM common code for PSCI management.
|
||||
* 2. ARM Generic Timer init.
|
||||
*
|
||||
*****************************************************************************/
|
||||
unsigned int plat_get_syscnt_freq2(void)
|
||||
{
|
||||
unsigned int counter_base_frequency;
|
||||
/*
|
||||
* Below register specifies the base frequency of the system counter.
|
||||
* As per NXP Board Manuals:
|
||||
* The system counter always works with SYS_REF_CLK/4 frequency clock.
|
||||
*
|
||||
*
|
||||
*/
|
||||
counter_base_frequency = mmio_read_32(NXP_TIMER_ADDR + CNTFID_OFF);
|
||||
|
||||
return counter_base_frequency;
|
||||
}
|
||||
|
||||
#ifdef IMAGE_BL2
|
||||
|
||||
#ifdef POLICY_FUSE_PROVISION
|
||||
static gpio_init_info_t gpio_init_data = {
|
||||
.gpio1_base_addr = NXP_GPIO1_ADDR,
|
||||
.gpio2_base_addr = NXP_GPIO2_ADDR,
|
||||
.gpio3_base_addr = NXP_GPIO3_ADDR,
|
||||
.gpio4_base_addr = NXP_GPIO4_ADDR,
|
||||
};
|
||||
#endif
|
||||
|
||||
static void soc_interconnect_config(void)
|
||||
{
|
||||
unsigned long long val = 0x0U;
|
||||
|
||||
uint32_t num_clusters = get_num_cluster();
|
||||
|
||||
if (num_clusters == 6U) {
|
||||
ccn_init(&plat_six_cluster_ccn_desc);
|
||||
} else {
|
||||
ccn_init(&plat_ccn_desc);
|
||||
}
|
||||
|
||||
/*
|
||||
* Enable Interconnect coherency for the primary CPU's cluster.
|
||||
*/
|
||||
plat_ls_interconnect_enter_coherency(num_clusters);
|
||||
|
||||
val = ccn_read_node_reg(NODE_TYPE_HNI, 13, PCIeRC_RN_I_NODE_ID_OFFSET);
|
||||
val |= (1 << 17);
|
||||
ccn_write_node_reg(NODE_TYPE_HNI, 13, PCIeRC_RN_I_NODE_ID_OFFSET, val);
|
||||
|
||||
/* PCIe is Connected to RN-I 17 which is connected to HN-I 13. */
|
||||
val = ccn_read_node_reg(NODE_TYPE_HNI, 30, PCIeRC_RN_I_NODE_ID_OFFSET);
|
||||
val |= (1 << 17);
|
||||
ccn_write_node_reg(NODE_TYPE_HNI, 30, PCIeRC_RN_I_NODE_ID_OFFSET, val);
|
||||
|
||||
val = ccn_read_node_reg(NODE_TYPE_HNI, 13, SA_AUX_CTRL_REG_OFFSET);
|
||||
val |= SERIALIZE_DEV_nGnRnE_WRITES;
|
||||
ccn_write_node_reg(NODE_TYPE_HNI, 13, SA_AUX_CTRL_REG_OFFSET, val);
|
||||
|
||||
val = ccn_read_node_reg(NODE_TYPE_HNI, 30, SA_AUX_CTRL_REG_OFFSET);
|
||||
val &= ~(ENABLE_RESERVE_BIT53);
|
||||
val |= SERIALIZE_DEV_nGnRnE_WRITES;
|
||||
ccn_write_node_reg(NODE_TYPE_HNI, 30, SA_AUX_CTRL_REG_OFFSET, val);
|
||||
|
||||
val = ccn_read_node_reg(NODE_TYPE_HNI, 13, PoS_CONTROL_REG_OFFSET);
|
||||
val &= ~(HNI_POS_EN);
|
||||
ccn_write_node_reg(NODE_TYPE_HNI, 13, PoS_CONTROL_REG_OFFSET, val);
|
||||
|
||||
val = ccn_read_node_reg(NODE_TYPE_HNI, 30, PoS_CONTROL_REG_OFFSET);
|
||||
val &= ~(HNI_POS_EN);
|
||||
ccn_write_node_reg(NODE_TYPE_HNI, 30, PoS_CONTROL_REG_OFFSET, val);
|
||||
|
||||
val = ccn_read_node_reg(NODE_TYPE_HNI, 13, SA_AUX_CTRL_REG_OFFSET);
|
||||
val &= ~(POS_EARLY_WR_COMP_EN);
|
||||
ccn_write_node_reg(NODE_TYPE_HNI, 13, SA_AUX_CTRL_REG_OFFSET, val);
|
||||
|
||||
val = ccn_read_node_reg(NODE_TYPE_HNI, 30, SA_AUX_CTRL_REG_OFFSET);
|
||||
val &= ~(POS_EARLY_WR_COMP_EN);
|
||||
ccn_write_node_reg(NODE_TYPE_HNI, 30, SA_AUX_CTRL_REG_OFFSET, val);
|
||||
|
||||
#if POLICY_PERF_WRIOP
|
||||
uint16_t wriop_rni = 0U;
|
||||
|
||||
if (POLICY_PERF_WRIOP == 1) {
|
||||
wriop_rni = 7U;
|
||||
} else if (POLICY_PERF_WRIOP == 2) {
|
||||
wriop_rni = 23U;
|
||||
} else {
|
||||
ERROR("Incorrect WRIOP selected.\n");
|
||||
panic();
|
||||
}
|
||||
|
||||
val = ccn_read_node_reg(NODE_TYPE_RNI, wriop_rni,
|
||||
SA_AUX_CTRL_REG_OFFSET);
|
||||
val |= ENABLE_WUO;
|
||||
ccn_write_node_reg(NODE_TYPE_HNI, wriop_rni, SA_AUX_CTRL_REG_OFFSET,
|
||||
val);
|
||||
#else
|
||||
val = ccn_read_node_reg(NODE_TYPE_RNI, 17, SA_AUX_CTRL_REG_OFFSET);
|
||||
val |= ENABLE_WUO;
|
||||
ccn_write_node_reg(NODE_TYPE_RNI, 17, SA_AUX_CTRL_REG_OFFSET, val);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
void soc_preload_setup(void)
|
||||
{
|
||||
dram_regions_info_t *info_dram_regions = get_dram_regions_info();
|
||||
#if defined(NXP_WARM_BOOT)
|
||||
bool warm_reset = is_warm_boot();
|
||||
#endif
|
||||
info_dram_regions->total_dram_size =
|
||||
#if defined(NXP_WARM_BOOT)
|
||||
init_ddr(warm_reset);
|
||||
#else
|
||||
init_ddr();
|
||||
#endif
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* This function implements soc specific erratas
|
||||
* This is called before DDR is initialized or MMU is enabled
|
||||
******************************************************************************/
|
||||
void soc_early_init(void)
|
||||
{
|
||||
dcfg_init(&dcfg_init_data);
|
||||
#ifdef POLICY_FUSE_PROVISION
|
||||
gpio_init(&gpio_init_data);
|
||||
sec_init(NXP_CAAM_ADDR);
|
||||
#endif
|
||||
#if LOG_LEVEL > 0
|
||||
/* Initialize the console to provide early debug support */
|
||||
plat_console_init(NXP_CONSOLE_ADDR,
|
||||
NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE);
|
||||
#endif
|
||||
|
||||
enable_timer_base_to_cluster(NXP_PMU_ADDR);
|
||||
soc_interconnect_config();
|
||||
|
||||
enum boot_device dev = get_boot_dev();
|
||||
/* Mark the buffer for SD in OCRAM as non secure.
|
||||
* The buffer is assumed to be at end of OCRAM for
|
||||
* the logic below to calculate TZPC programming
|
||||
*/
|
||||
if (dev == BOOT_DEVICE_EMMC || dev == BOOT_DEVICE_SDHC2_EMMC) {
|
||||
/* Calculate the region in OCRAM which is secure
|
||||
* The buffer for SD needs to be marked non-secure
|
||||
* to allow SD to do DMA operations on it
|
||||
*/
|
||||
uint32_t secure_region = (NXP_OCRAM_SIZE
|
||||
- NXP_SD_BLOCK_BUF_SIZE);
|
||||
uint32_t mask = secure_region/TZPC_BLOCK_SIZE;
|
||||
|
||||
mmio_write_32(NXP_OCRAM_TZPC_ADDR, mask);
|
||||
|
||||
/* Add the entry for buffer in MMU Table */
|
||||
mmap_add_region(NXP_SD_BLOCK_BUF_ADDR, NXP_SD_BLOCK_BUF_ADDR,
|
||||
NXP_SD_BLOCK_BUF_SIZE,
|
||||
MT_DEVICE | MT_RW | MT_NS);
|
||||
}
|
||||
|
||||
#ifdef ERRATA_SOC_A050426
|
||||
erratum_a050426();
|
||||
#endif
|
||||
|
||||
#if (TRUSTED_BOARD_BOOT) || defined(POLICY_FUSE_PROVISION)
|
||||
sfp_init(NXP_SFP_ADDR);
|
||||
#endif
|
||||
|
||||
#if TRUSTED_BOARD_BOOT
|
||||
uint32_t mode;
|
||||
|
||||
/* For secure boot disable SMMU.
|
||||
* Later when platform security policy comes in picture,
|
||||
* this might get modified based on the policy
|
||||
*/
|
||||
if (check_boot_mode_secure(&mode) == true) {
|
||||
bypass_smmu(NXP_SMMU_ADDR);
|
||||
}
|
||||
|
||||
/* For Mbedtls currently crypto is not supported via CAAM
|
||||
* enable it when that support is there. In tbbr.mk
|
||||
* the CAAM_INTEG is set as 0.
|
||||
*/
|
||||
|
||||
#ifndef MBEDTLS_X509
|
||||
/* Initialize the crypto accelerator if enabled */
|
||||
if (is_sec_enabled() == false)
|
||||
INFO("SEC is disabled.\n");
|
||||
else
|
||||
sec_init(NXP_CAAM_ADDR);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Initialize system level generic timer for Layerscape Socs.
|
||||
*/
|
||||
delay_timer_init(NXP_TIMER_ADDR);
|
||||
i2c_init(NXP_I2C_ADDR);
|
||||
}
|
||||
|
||||
void soc_bl2_prepare_exit(void)
|
||||
{
|
||||
#if defined(NXP_SFP_ENABLED) && defined(DISABLE_FUSE_WRITE)
|
||||
set_sfp_wr_disable();
|
||||
#endif
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* This function returns the boot device based on RCW_SRC
|
||||
****************************************************************************/
|
||||
enum boot_device get_boot_dev(void)
|
||||
{
|
||||
enum boot_device src = BOOT_DEVICE_NONE;
|
||||
uint32_t porsr1;
|
||||
uint32_t rcw_src;
|
||||
|
||||
porsr1 = read_reg_porsr1();
|
||||
|
||||
rcw_src = (porsr1 & PORSR1_RCW_MASK) >> PORSR1_RCW_SHIFT;
|
||||
|
||||
switch (rcw_src) {
|
||||
case FLEXSPI_NOR:
|
||||
src = BOOT_DEVICE_FLEXSPI_NOR;
|
||||
INFO("RCW BOOT SRC is FLEXSPI NOR\n");
|
||||
break;
|
||||
case FLEXSPI_NAND2K_VAL:
|
||||
case FLEXSPI_NAND4K_VAL:
|
||||
INFO("RCW BOOT SRC is FLEXSPI NAND\n");
|
||||
src = BOOT_DEVICE_FLEXSPI_NAND;
|
||||
break;
|
||||
case SDHC1_VAL:
|
||||
src = BOOT_DEVICE_EMMC;
|
||||
INFO("RCW BOOT SRC is SD\n");
|
||||
break;
|
||||
case SDHC2_VAL:
|
||||
src = BOOT_DEVICE_SDHC2_EMMC;
|
||||
INFO("RCW BOOT SRC is EMMC\n");
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return src;
|
||||
}
|
||||
|
||||
|
||||
void soc_mem_access(void)
|
||||
{
|
||||
const devdisr5_info_t *devdisr5_info = get_devdisr5_info();
|
||||
dram_regions_info_t *info_dram_regions = get_dram_regions_info();
|
||||
struct tzc400_reg tzc400_reg_list[MAX_NUM_TZC_REGION];
|
||||
int dram_idx, index = 0U;
|
||||
|
||||
for (dram_idx = 0U; dram_idx < info_dram_regions->num_dram_regions;
|
||||
dram_idx++) {
|
||||
if (info_dram_regions->region[dram_idx].size == 0) {
|
||||
ERROR("DDR init failure, or");
|
||||
ERROR("DRAM regions not populated correctly.\n");
|
||||
break;
|
||||
}
|
||||
|
||||
index = populate_tzc400_reg_list(tzc400_reg_list,
|
||||
dram_idx, index,
|
||||
info_dram_regions->region[dram_idx].addr,
|
||||
info_dram_regions->region[dram_idx].size,
|
||||
NXP_SECURE_DRAM_SIZE, NXP_SP_SHRD_DRAM_SIZE);
|
||||
}
|
||||
|
||||
if (devdisr5_info->ddrc1_present != 0) {
|
||||
INFO("DDR Controller 1.\n");
|
||||
mem_access_setup(NXP_TZC_ADDR, index,
|
||||
tzc400_reg_list);
|
||||
mem_access_setup(NXP_TZC3_ADDR, index,
|
||||
tzc400_reg_list);
|
||||
}
|
||||
if (devdisr5_info->ddrc2_present != 0) {
|
||||
INFO("DDR Controller 2.\n");
|
||||
mem_access_setup(NXP_TZC2_ADDR, index,
|
||||
tzc400_reg_list);
|
||||
mem_access_setup(NXP_TZC4_ADDR, index,
|
||||
tzc400_reg_list);
|
||||
}
|
||||
}
|
||||
|
||||
#else
|
||||
const unsigned char _power_domain_tree_desc[] = {1, 8, 2, 2, 2, 2, 2, 2, 2, 2};
|
||||
|
||||
CASSERT(NUMBER_OF_CLUSTERS && NUMBER_OF_CLUSTERS <= 256,
|
||||
assert_invalid_lx2160a_cluster_count);
|
||||
|
||||
/******************************************************************************
|
||||
* This function returns the SoC topology
|
||||
****************************************************************************/
|
||||
|
||||
const unsigned char *plat_get_power_domain_tree_desc(void)
|
||||
{
|
||||
|
||||
return _power_domain_tree_desc;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* This function returns the core count within the cluster corresponding to
|
||||
* `mpidr`.
|
||||
******************************************************************************/
|
||||
unsigned int plat_ls_get_cluster_core_count(u_register_t mpidr)
|
||||
{
|
||||
return CORES_PER_CLUSTER;
|
||||
}
|
||||
|
||||
|
||||
void soc_early_platform_setup2(void)
|
||||
{
|
||||
dcfg_init(&dcfg_init_data);
|
||||
/*
|
||||
* Initialize system level generic timer for Socs
|
||||
*/
|
||||
delay_timer_init(NXP_TIMER_ADDR);
|
||||
|
||||
#if LOG_LEVEL > 0
|
||||
/* Initialize the console to provide early debug support */
|
||||
plat_console_init(NXP_CONSOLE_ADDR,
|
||||
NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE);
|
||||
#endif
|
||||
}
|
||||
|
||||
void soc_platform_setup(void)
|
||||
{
|
||||
/* Initialize the GIC driver, cpu and distributor interfaces */
|
||||
static uintptr_t target_mask_array[PLATFORM_CORE_COUNT];
|
||||
static interrupt_prop_t ls_interrupt_props[] = {
|
||||
PLAT_LS_G1S_IRQ_PROPS(INTR_GROUP1S),
|
||||
PLAT_LS_G0_IRQ_PROPS(INTR_GROUP0)
|
||||
};
|
||||
|
||||
plat_ls_gic_driver_init(NXP_GICD_ADDR, NXP_GICR_ADDR,
|
||||
PLATFORM_CORE_COUNT,
|
||||
ls_interrupt_props,
|
||||
ARRAY_SIZE(ls_interrupt_props),
|
||||
target_mask_array,
|
||||
plat_core_pos);
|
||||
|
||||
plat_ls_gic_init();
|
||||
enable_init_timer();
|
||||
#ifdef LS_SYS_TIMCTL_BASE
|
||||
ls_configure_sys_timer(LS_SYS_TIMCTL_BASE,
|
||||
LS_CONFIG_CNTACR,
|
||||
PLAT_LS_NSTIMER_FRAME_ID);
|
||||
#endif
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* This function initializes the soc from the BL31 module
|
||||
******************************************************************************/
|
||||
void soc_init(void)
|
||||
{
|
||||
/* low-level init of the soc */
|
||||
soc_init_start();
|
||||
soc_init_percpu();
|
||||
_init_global_data();
|
||||
_initialize_psci();
|
||||
|
||||
if (ccn_get_part0_id(NXP_CCN_ADDR) != CCN_508_PART0_ID) {
|
||||
ERROR("Unrecognized CCN variant detected.");
|
||||
ERROR("Only CCN-508 is supported\n");
|
||||
panic();
|
||||
}
|
||||
|
||||
uint32_t num_clusters = get_num_cluster();
|
||||
|
||||
if (num_clusters == 6U) {
|
||||
ccn_init(&plat_six_cluster_ccn_desc);
|
||||
} else {
|
||||
ccn_init(&plat_ccn_desc);
|
||||
}
|
||||
|
||||
plat_ls_interconnect_enter_coherency(num_clusters);
|
||||
|
||||
/* Set platform security policies */
|
||||
_set_platform_security();
|
||||
|
||||
/* make sure any parallel init tasks are finished */
|
||||
soc_init_finish();
|
||||
|
||||
/* Initialize the crypto accelerator if enabled */
|
||||
if (is_sec_enabled() == false) {
|
||||
INFO("SEC is disabled.\n");
|
||||
} else {
|
||||
sec_init(NXP_CAAM_ADDR);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
#ifdef NXP_WDOG_RESTART
|
||||
static uint64_t wdog_interrupt_handler(uint32_t id, uint32_t flags,
|
||||
void *handle, void *cookie)
|
||||
{
|
||||
uint8_t data = WDOG_RESET_FLAG;
|
||||
|
||||
wr_nv_app_data(WDT_RESET_FLAG_OFFSET,
|
||||
(uint8_t *)&data, sizeof(data));
|
||||
|
||||
mmio_write_32(NXP_RST_ADDR + RSTCNTL_OFFSET, SW_RST_REQ_INIT);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
void soc_runtime_setup(void)
|
||||
{
|
||||
|
||||
#ifdef NXP_WDOG_RESTART
|
||||
request_intr_type_el3(BL31_NS_WDOG_WS1, wdog_interrupt_handler);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,201 @@
|
|||
#
|
||||
# Copyright (c) 2015, 2016 Freescale Semiconductor, Inc.
|
||||
# Copyright 2017-2020 NXP Semiconductors
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
#
|
||||
#------------------------------------------------------------------------------
|
||||
#
|
||||
# This file contains the basic architecture definitions that drive the build
|
||||
#
|
||||
# -----------------------------------------------------------------------------
|
||||
|
||||
CORE_TYPE := a72
|
||||
|
||||
CACHE_LINE := 6
|
||||
|
||||
# set to GIC400 or GIC500
|
||||
GIC := GIC500
|
||||
|
||||
# set to CCI400 or CCN504 or CCN508
|
||||
INTERCONNECT := CCN508
|
||||
|
||||
# indicate layerscape chassis level - set to 3=LSCH3 or 2=LSCH2
|
||||
CHASSIS := 3_2
|
||||
|
||||
# TZC IP Details TZC used is TZC380 or TZC400
|
||||
TZC_ID := TZC400
|
||||
|
||||
# CONSOLE Details available is NS16550 or PL011
|
||||
CONSOLE := PL011
|
||||
|
||||
# Select the DDR PHY generation to be used
|
||||
PLAT_DDR_PHY := PHY_GEN2
|
||||
|
||||
PHYS_SYS := 64
|
||||
|
||||
# Area of OCRAM reserved by ROM code
|
||||
NXP_ROM_RSVD := 0xa000
|
||||
|
||||
# Max Size of CSF header. Required to define BL2 TEXT LIMIT in soc.def
|
||||
# Input to CST create_hdr_esbc tool
|
||||
CSF_HDR_SZ := 0x3000
|
||||
|
||||
NXP_SFP_VER := 3_4
|
||||
|
||||
# In IMAGE_BL2, compile time flag for handling Cache coherency
|
||||
# with CAAM for BL2 running from OCRAM
|
||||
SEC_MEM_NON_COHERENT := yes
|
||||
|
||||
# Defining the endianness for NXP ESDHC
|
||||
NXP_ESDHC_ENDIANNESS := LE
|
||||
|
||||
# Defining the endianness for NXP SFP
|
||||
NXP_SFP_ENDIANNESS := LE
|
||||
|
||||
# Defining the endianness for NXP GPIO
|
||||
NXP_GPIO_ENDIANNESS := LE
|
||||
|
||||
# Defining the endianness for NXP SNVS
|
||||
NXP_SNVS_ENDIANNESS := LE
|
||||
|
||||
# Defining the endianness for NXP CCSR GUR register
|
||||
NXP_GUR_ENDIANNESS := LE
|
||||
|
||||
# Defining the endianness for NXP FSPI register
|
||||
NXP_FSPI_ENDIANNESS := LE
|
||||
|
||||
# Defining the endianness for NXP SEC
|
||||
NXP_SEC_ENDIANNESS := LE
|
||||
|
||||
# Defining the endianness for NXP DDR
|
||||
NXP_DDR_ENDIANNESS := LE
|
||||
|
||||
NXP_DDR_INTLV_256B := 1
|
||||
|
||||
# OCRAM MAP for BL2
|
||||
# Before BL2
|
||||
# 0x18000000 - 0x18009fff -> Used by ROM code
|
||||
# 0x1800a000 - 0x1800dfff -> CSF header for BL2
|
||||
# (The above area i.e 0x18000000 - 0x1800dfff is available
|
||||
# for DDR PHY images scratch pad region during BL2 run time)
|
||||
# For FlexSPI boot
|
||||
# 0x1800e000 - 0x18040000 -> Reserved for BL2 binary
|
||||
# For SD boot
|
||||
# 0x1800e000 - 0x18030000 -> Reserved for BL2 binary
|
||||
# 0x18030000 - 0x18040000 -> Reserved for SD buffer
|
||||
OCRAM_START_ADDR := 0x18000000
|
||||
OCRAM_SIZE := 0x40000
|
||||
|
||||
# Location of BL2 on OCRAM
|
||||
BL2_BASE_ADDR := $(shell echo $$(( $(OCRAM_START_ADDR) + $(NXP_ROM_RSVD) + $(CSF_HDR_SZ) )))
|
||||
# Covert to HEX to be used by create_pbl.mk
|
||||
BL2_BASE := $$(echo "obase=16; ${BL2_BASE_ADDR}" | bc)
|
||||
|
||||
# BL2_HDR_LOC is at (OCRAM_ADDR + NXP_ROM_RSVD)
|
||||
# This value BL2_HDR_LOC + CSF_HDR_SZ should not overalp with BL2_BASE
|
||||
BL2_HDR_LOC_HDR ?= $(shell echo $$(( $(OCRAM_START_ADDR) + $(NXP_ROM_RSVD) )))
|
||||
# Covert to HEX to be used by create_pbl.mk
|
||||
BL2_HDR_LOC := $$(echo "obase=16; ${BL2_HDR_LOC_HDR}" | bc)
|
||||
|
||||
# SoC ERRATAS to be enabled
|
||||
#
|
||||
# Core Errata
|
||||
ERRATA_A72_859971 := 1
|
||||
|
||||
# SoC Errata
|
||||
ERRATA_SOC_A050426 := 1
|
||||
|
||||
ifneq (${CACHE_LINE},)
|
||||
$(eval $(call add_define_val,PLATFORM_CACHE_LINE_SHIFT,${CACHE_LINE}))
|
||||
$(eval CACHE_WRITEBACK_GRANULE=$(shell echo $$((1 << $(CACHE_LINE)))))
|
||||
$(eval $(call add_define_val,CACHE_WRITEBACK_GRANULE,$(CACHE_WRITEBACK_GRANULE)))
|
||||
endif
|
||||
|
||||
ifneq (${INTERCONNECT},)
|
||||
$(eval $(call add_define,NXP_HAS_CCN508))
|
||||
endif
|
||||
|
||||
ifneq (${CHASSIS},)
|
||||
$(eval $(call add_define,CONFIG_CHASSIS_${CHASSIS}))
|
||||
endif
|
||||
|
||||
ifneq (${PLAT_DDR_PHY},)
|
||||
$(eval $(call add_define,NXP_DDR_${PLAT_DDR_PHY}))
|
||||
endif
|
||||
|
||||
ifneq (${PHYS_SYS},)
|
||||
$(eval $(call add_define,CONFIG_PHYS_64BIT))
|
||||
endif
|
||||
|
||||
ifneq (${CSF_HDR_SZ},)
|
||||
$(eval $(call add_define_val,CSF_HDR_SZ,${CSF_HDR_SZ}))
|
||||
endif
|
||||
|
||||
ifneq (${OCRAM_START_ADDR},)
|
||||
$(eval $(call add_define_val,NXP_OCRAM_ADDR,${OCRAM_START_ADDR}))
|
||||
endif
|
||||
|
||||
ifneq (${OCRAM_SIZE},)
|
||||
$(eval $(call add_define_val,NXP_OCRAM_SIZE,${OCRAM_SIZE}))
|
||||
endif
|
||||
|
||||
ifneq (${NXP_ROM_RSVD},)
|
||||
$(eval $(call add_define_val,NXP_ROM_RSVD,${NXP_ROM_RSVD}))
|
||||
endif
|
||||
|
||||
ifneq (${BL2_BASE_ADDR},)
|
||||
$(eval $(call add_define_val,BL2_BASE,${BL2_BASE_ADDR}))
|
||||
endif
|
||||
|
||||
ifeq (${SEC_MEM_NON_COHERENT},yes)
|
||||
$(eval $(call add_define,SEC_MEM_NON_COHERENT))
|
||||
endif
|
||||
|
||||
ifneq (${NXP_ESDHC_ENDIANNESS},)
|
||||
$(eval $(call add_define,NXP_ESDHC_${NXP_ESDHC_ENDIANNESS}))
|
||||
endif
|
||||
|
||||
ifneq (${NXP_SFP_VER},)
|
||||
$(eval $(call add_define,NXP_SFP_VER_${NXP_SFP_VER}))
|
||||
endif
|
||||
|
||||
ifneq (${NXP_SFP_ENDIANNESS},)
|
||||
$(eval $(call add_define,NXP_SFP_${NXP_SFP_ENDIANNESS}))
|
||||
endif
|
||||
|
||||
ifneq (${NXP_GPIO_ENDIANNESS},)
|
||||
$(eval $(call add_define,NXP_GPIO_${NXP_GPIO_ENDIANNESS}))
|
||||
endif
|
||||
|
||||
ifneq (${NXP_SNVS_ENDIANNESS},)
|
||||
$(eval $(call add_define,NXP_SNVS_${NXP_SNVS_ENDIANNESS}))
|
||||
endif
|
||||
|
||||
ifneq (${NXP_GUR_ENDIANNESS},)
|
||||
$(eval $(call add_define,NXP_GUR_${NXP_GUR_ENDIANNESS}))
|
||||
endif
|
||||
|
||||
ifneq (${NXP_FSPI_ENDIANNESS},)
|
||||
$(eval $(call add_define,NXP_FSPI_${NXP_FSPI_ENDIANNESS}))
|
||||
endif
|
||||
|
||||
# enable dynamic memory mapping
|
||||
PLAT_XLAT_TABLES_DYNAMIC := 1
|
||||
|
||||
ifneq (${NXP_SEC_ENDIANNESS},)
|
||||
$(eval $(call add_define,NXP_SEC_${NXP_SEC_ENDIANNESS}))
|
||||
endif
|
||||
|
||||
ifneq (${NXP_DDR_ENDIANNESS},)
|
||||
$(eval $(call add_define,NXP_DDR_${NXP_DDR_ENDIANNESS}))
|
||||
endif
|
||||
|
||||
ifneq (${NXP_DDR_INTLV_256B},)
|
||||
$(eval $(call add_define,NXP_DDR_INTLV_256B))
|
||||
endif
|
||||
|
||||
ifneq (${PLAT_XLAT_TABLES_DYNAMIC},)
|
||||
$(eval $(call add_define,PLAT_XLAT_TABLES_DYNAMIC))
|
||||
endif
|
||||
|
|
@ -0,0 +1,173 @@
|
|||
#
|
||||
# Copyright 2018-2020 NXP
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
|
||||
# SoC-specific build parameters
|
||||
SOC := lx2160a
|
||||
PLAT_PATH := plat/nxp
|
||||
PLAT_COMMON_PATH:= plat/nxp/common
|
||||
PLAT_DRIVERS_PATH:= drivers/nxp
|
||||
PLAT_SOC_PATH := ${PLAT_PATH}/soc-${SOC}
|
||||
BOARD_PATH := ${PLAT_SOC_PATH}/${BOARD}
|
||||
|
||||
# get SoC-specific defnitions
|
||||
include ${PLAT_SOC_PATH}/soc.def
|
||||
|
||||
include ${PLAT_COMMON_PATH}/plat_make_helper/plat_build_macros.mk
|
||||
|
||||
# SoC-specific
|
||||
NXP_WDOG_RESTART := yes
|
||||
|
||||
|
||||
# Selecting dependent module,
|
||||
# Selecting dependent drivers, and
|
||||
# Adding defines.
|
||||
|
||||
# for features enabled above.
|
||||
ifeq (${NXP_WDOG_RESTART}, yes)
|
||||
NXP_NV_SW_MAINT_LAST_EXEC_DATA := yes
|
||||
LS_EL3_INTERRUPT_HANDLER := yes
|
||||
$(eval $(call add_define, NXP_WDOG_RESTART))
|
||||
endif
|
||||
|
||||
|
||||
# For Security Features
|
||||
DISABLE_FUSE_WRITE := 1
|
||||
ifeq (${TRUSTED_BOARD_BOOT}, 1)
|
||||
ifeq (${GENERATE_COT},1)
|
||||
# Save Keys to be used by DDR FIP image
|
||||
SAVE_KEYS=1
|
||||
endif
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,SMMU_NEEDED,BL2))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,SFP_NEEDED,BL2))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,SNVS_NEEDED,BL2))
|
||||
# Used by create_pbl tool to
|
||||
# create bl2_<boot_mode>_sec.pbl image
|
||||
SECURE_BOOT := yes
|
||||
endif
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,CRYPTO_NEEDED,BL_COMM))
|
||||
|
||||
|
||||
# Selecting Drivers for SoC
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,DCFG_NEEDED,BL_COMM))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,TIMER_NEEDED,BL_COMM))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,INTERCONNECT_NEEDED,BL_COMM))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,GIC_NEEDED,BL31))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,CONSOLE_NEEDED,BL_COMM))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,PMU_NEEDED,BL_COMM))
|
||||
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,DDR_DRIVER_NEEDED,BL2))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,TZASC_NEEDED,BL2))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,I2C_NEEDED,BL2))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,IMG_LOADR_NEEDED,BL2))
|
||||
|
||||
|
||||
# Selecting PSCI & SIP_SVC support
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,PSCI_NEEDED,BL31))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,SIPSVC_NEEDED,BL31))
|
||||
|
||||
|
||||
# Selecting Boot Source for the TFA images.
|
||||
ifeq (${BOOT_MODE}, flexspi_nor)
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,XSPI_NEEDED,BL2))
|
||||
$(eval $(call add_define,FLEXSPI_NOR_BOOT))
|
||||
else
|
||||
ifeq (${BOOT_MODE}, sd)
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,SD_MMC_NEEDED,BL2))
|
||||
$(eval $(call add_define,SD_BOOT))
|
||||
else
|
||||
ifeq (${BOOT_MODE}, emmc)
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,SD_MMC_NEEDED,BL2))
|
||||
$(eval $(call add_define,EMMC_BOOT))
|
||||
else
|
||||
$(error Un-supported Boot Mode = ${BOOT_MODE})
|
||||
endif
|
||||
endif
|
||||
endif
|
||||
|
||||
|
||||
# Separate DDR-FIP image to be loaded.
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,DDR_FIP_IO_NEEDED,BL2))
|
||||
|
||||
|
||||
# Source File Addition
|
||||
# #####################
|
||||
|
||||
PLAT_INCLUDES += -I${PLAT_COMMON_PATH}/include/default\
|
||||
-I${BOARD_PATH}\
|
||||
-I${PLAT_COMMON_PATH}/include/default/ch_${CHASSIS}\
|
||||
-I${PLAT_SOC_PATH}/include
|
||||
|
||||
ifeq (${SECURE_BOOT},yes)
|
||||
include ${PLAT_COMMON_PATH}/tbbr/tbbr.mk
|
||||
endif
|
||||
|
||||
ifeq ($(WARM_BOOT),yes)
|
||||
include ${PLAT_COMMON_PATH}/warm_reset/warm_reset.mk
|
||||
endif
|
||||
|
||||
ifeq (${NXP_NV_SW_MAINT_LAST_EXEC_DATA}, yes)
|
||||
include ${PLAT_COMMON_PATH}/nv_storage/nv_storage.mk
|
||||
endif
|
||||
|
||||
ifeq (${PSCI_NEEDED}, yes)
|
||||
include ${PLAT_COMMON_PATH}/psci/psci.mk
|
||||
endif
|
||||
|
||||
ifeq (${SIPSVC_NEEDED}, yes)
|
||||
include ${PLAT_COMMON_PATH}/sip_svc/sipsvc.mk
|
||||
endif
|
||||
|
||||
ifeq (${DDR_FIP_IO_NEEDED}, yes)
|
||||
include ${PLAT_COMMON_PATH}/fip_handler/ddr_fip/ddr_fip_io.mk
|
||||
endif
|
||||
|
||||
# for fuse-fip & fuse-programming
|
||||
ifeq (${FUSE_PROG}, 1)
|
||||
include ${PLAT_COMMON_PATH}/fip_handler/fuse_fip/fuse.mk
|
||||
endif
|
||||
|
||||
ifeq (${IMG_LOADR_NEEDED},yes)
|
||||
include $(PLAT_COMMON_PATH)/img_loadr/img_loadr.mk
|
||||
endif
|
||||
|
||||
# Adding source files for the above selected drivers.
|
||||
include ${PLAT_DRIVERS_PATH}/drivers.mk
|
||||
|
||||
# Adding SoC specific files
|
||||
include ${PLAT_SOC_PATH}/erratas_soc.mk
|
||||
|
||||
PLAT_INCLUDES += ${NV_STORAGE_INCLUDES}\
|
||||
${WARM_RST_INCLUDES}
|
||||
|
||||
BL31_SOURCES += ${PLAT_SOC_PATH}/$(ARCH)/${SOC}.S\
|
||||
${WARM_RST_BL31_SOURCES}\
|
||||
${PSCI_SOURCES}\
|
||||
${SIPSVC_SOURCES}\
|
||||
${PLAT_COMMON_PATH}/$(ARCH)/bl31_data.S
|
||||
|
||||
PLAT_BL_COMMON_SOURCES += ${PLAT_COMMON_PATH}/$(ARCH)/ls_helpers.S\
|
||||
${PLAT_SOC_PATH}/aarch64/${SOC}_helpers.S\
|
||||
${NV_STORAGE_SOURCES}\
|
||||
${WARM_RST_BL_COMM_SOURCES}\
|
||||
${PLAT_SOC_PATH}/soc.c
|
||||
|
||||
ifeq (${TEST_BL31}, 1)
|
||||
BL31_SOURCES += ${PLAT_SOC_PATH}/$(ARCH)/bootmain64.S\
|
||||
${PLAT_SOC_PATH}/$(ARCH)/nonboot64.S
|
||||
endif
|
||||
|
||||
BL2_SOURCES += ${DDR_CNTLR_SOURCES}\
|
||||
${TBBR_SOURCES}\
|
||||
${FUSE_SOURCES}
|
||||
|
||||
|
||||
# Adding TFA setup files
|
||||
include ${PLAT_PATH}/common/setup/common.mk
|
||||
|
||||
|
||||
# Adding source files to generate separate DDR FIP image
|
||||
include ${PLAT_SOC_PATH}/ddr_fip.mk
|
||||
Loading…
Reference in New Issue