feat(morello): expose scmi protocols in fdts
Add 'firmware' node in morello-soc.dts to expose SCMI support to the kernel. The SCMI protocols supported at the moment are SCMI Base, Clock and Perf (DVFS). The current mailbox memory region in MHU SRAM has an issue with any access not aligned to a 4-byte boundary. So, the SCMI mailbox memory region has been relocated to AP non-trusted RAM to get around the problem. Signed-off-by: Anurag Koul <anurag.koul@arm.com> Change-Id: Ibcbce8823b751a0fc3be7e9bc3588c1dc47ae024
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07302a23ec
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@ -32,24 +32,28 @@
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reg = <0x0 0x0>;
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device_type = "cpu";
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enable-method = "psci";
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clocks = <&scmi_dvfs 0>;
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};
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cpu1@100 {
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compatible = "arm,armv8";
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reg = <0x0 0x100>;
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device_type = "cpu";
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enable-method = "psci";
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clocks = <&scmi_dvfs 0>;
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};
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cpu2@10000 {
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compatible = "arm,armv8";
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reg = <0x0 0x10000>;
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device_type = "cpu";
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enable-method = "psci";
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clocks = <&scmi_dvfs 1>;
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};
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cpu3@10100 {
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compatible = "arm,armv8";
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reg = <0x0 0x10100>;
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device_type = "cpu";
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enable-method = "psci";
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clocks = <&scmi_dvfs 1>;
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};
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};
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@ -166,7 +170,7 @@
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pl0: pipeline@0 {
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reg = <0>;
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clocks = <&dpu_pixel_clk>;
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clocks = <&scmi_clk 1>;
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clock-names = "pxclk";
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pl_id = <0>;
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ports {
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@ -212,11 +216,23 @@
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clock-output-names = "aclk";
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};
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dpu_pixel_clk: dpu-pixel-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <148500000>;
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clock-output-names = "pxclk";
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firmware {
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scmi {
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compatible = "arm,scmi";
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mbox-names = "tx", "rx";
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mboxes = <&mailbox 1 0 &mailbox 1 1>;
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shmem = <&cpu_scp_hpri0 &cpu_scp_hpri1>;
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#address-cells = <1>;
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#size-cells = <0>;
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scmi_dvfs: protocol@13 {
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reg = <0x13>;
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#clock-cells = <1>;
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};
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scmi_clk: protocol@14 {
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reg = <0x14>;
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#clock-cells = <1>;
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};
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};
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};
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};
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@ -64,11 +64,11 @@
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sram: sram@45200000 {
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compatible = "mmio-sram";
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reg = <0x0 0x45200000 0x0 0x8000>;
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reg = <0x0 0x06000000 0x0 0x8000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x0 0x45200000 0x8000>;
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ranges = <0 0x0 0x06000000 0x8000>;
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cpu_scp_hpri0: scp-shmem@0 {
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compatible = "arm,scmi-shmem";
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