Merge changes from topic "tegra-downstream-02092020" into integration
* changes: Tegra: spe: uninit console on a timeout Tegra: handler to check support for System Suspend Tegra: bpmp_ipc: improve cyclomatic complexity Tegra: platform handler to relocate BL32 image Tegra: common: improve cyclomatic complexity Tegra210: secure PMC hardware block Tegra: delay_timer: support for physical secure timer include: move MHZ_TICKS_PER_SEC to utils_def.h Tegra194: memctrl: lock mc stream id security config Tegra210: resume PMC hardware block for all platforms Tegra: macro for legacy WDT FIQ handling Tegra186: enable higher performance non-cacheable load forwarding Tegra210: enable higher performance non-cacheable load forwarding cpus: higher performance non-cacheable load forwarding
This commit is contained in:
joanna.farley
TrustedFirmware Code Review
commit
876b38497e
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@ -324,6 +324,13 @@ architecture that can be enabled by the platform as desired.
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as recommended in section "4.7 Non-Temporal Loads/Stores" of the
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`Cortex-A57 Software Optimization Guide`_.
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- ''A57_ENABLE_NON_CACHEABLE_LOAD_FWD'': This flag enables non-cacheable
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streaming enhancement feature for Cortex-A57 CPUs. Platforms can set
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this bit only if their memory system meets the requirement that cache
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line fill requests from the Cortex-A57 processor are atomic. Each
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Cortex-A57 based platform must make its own decision on whether to use
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the optimization. This flag is disabled by default.
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- ``NEOVERSE_N1_EXTERNAL_LLC``: This flag indicates that an external last
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level cache(LLC) is present in the system, and that the DataSource field
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on the master CHI interface indicates when data is returned from the LLC.
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@ -1,5 +1,6 @@
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/*
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* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -12,11 +13,9 @@
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <drivers/generic_delay_timer.h>
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#include <lib/utils_def.h>
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#include <plat/common/platform.h>
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/* Ticks elapsed in one second by a signal of 1 MHz */
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#define MHZ_TICKS_PER_SEC 1000000
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static timer_ops_t ops;
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static uint32_t get_timer_value(void)
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@ -1,5 +1,6 @@
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/*
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* Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -597,6 +598,10 @@
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#define CNTP_CTL_IMASK_MASK U(1)
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#define CNTP_CTL_ISTATUS_MASK U(1)
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/* Physical timer control macros */
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#define CNTP_CTL_ENABLE_BIT (U(1) << CNTP_CTL_ENABLE_SHIFT)
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#define CNTP_CTL_IMASK_BIT (U(1) << CNTP_CTL_IMASK_SHIFT)
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/* Exception Syndrome register bits and bobs */
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#define ESR_EC_SHIFT U(26)
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#define ESR_EC_MASK U(0x3f)
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@ -1,5 +1,6 @@
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/*
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* Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -54,6 +55,7 @@
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#define CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH (ULL(1) << 38)
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#define CORTEX_A57_CPUACTLR_EL1_DIS_INSTR_PREFETCH (ULL(1) << 32)
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#define CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING (ULL(3) << 27)
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#define CORTEX_A57_CPUACTLR_EL1_EN_NC_LOAD_FWD (ULL(1) << 24)
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#define CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING (ULL(3) << 25)
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#define CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR (ULL(1) << 4)
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@ -1,5 +1,6 @@
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/*
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* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -157,4 +158,9 @@
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# define SPECULATION_SAFE_VALUE(var) var
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#endif
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/*
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* Ticks elapsed in one second with a signal of 1 MHz
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*/
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#define MHZ_TICKS_PER_SEC U(1000000)
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#endif /* UTILS_DEF_H */
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@ -1,5 +1,6 @@
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/*
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* Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -469,6 +470,17 @@ func cortex_a57_reset_func
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dsb sy
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#endif
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#if A57_ENABLE_NONCACHEABLE_LOAD_FWD
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/* ---------------------------------------------
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* Enable higher performance non-cacheable load
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* forwarding
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* ---------------------------------------------
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*/
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mrs x0, CORTEX_A57_CPUACTLR_EL1
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orr x0, x0, #CORTEX_A57_CPUACTLR_EL1_EN_NC_LOAD_FWD
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msr CORTEX_A57_CPUACTLR_EL1, x0
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#endif
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/* ---------------------------------------------
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* Enable the SMP bit.
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* ---------------------------------------------
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@ -1,5 +1,6 @@
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#
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# Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
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# Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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@ -16,6 +17,10 @@ A53_DISABLE_NON_TEMPORAL_HINT ?=1
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# It is enabled by default.
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A57_DISABLE_NON_TEMPORAL_HINT ?=1
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# Flag to enable higher performance non-cacheable load forwarding.
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# It is disabled by default.
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A57_ENABLE_NONCACHEABLE_LOAD_FWD ?= 0
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WORKAROUND_CVE_2017_5715 ?=1
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WORKAROUND_CVE_2018_3639 ?=1
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DYNAMIC_WORKAROUND_CVE_2018_3639 ?=0
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@ -24,6 +29,10 @@ DYNAMIC_WORKAROUND_CVE_2018_3639 ?=0
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# By default internal
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NEOVERSE_N1_EXTERNAL_LLC ?=0
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# Process A57_ENABLE_NONCACHEABLE_LOAD_FWD flag
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$(eval $(call assert_boolean,A57_ENABLE_NONCACHEABLE_LOAD_FWD))
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$(eval $(call add_define,A57_ENABLE_NONCACHEABLE_LOAD_FWD))
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# Process SKIP_A57_L1_FLUSH_PWR_DWN flag
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$(eval $(call assert_boolean,SKIP_A57_L1_FLUSH_PWR_DWN))
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$(eval $(call add_define,SKIP_A57_L1_FLUSH_PWR_DWN))
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@ -1,5 +1,6 @@
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/*
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* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -9,6 +10,7 @@
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#include <arch.h>
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#include <lib/pmf/pmf.h>
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#include <lib/psci/psci.h>
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#include <lib/utils_def.h>
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#include <plat/common/platform.h>
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#if ENABLE_PSCI_STAT && ENABLE_PMF
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@ -16,9 +18,6 @@
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#pragma weak plat_psci_stat_accounting_stop
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#pragma weak plat_psci_stat_get_residency
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/* Ticks elapsed in one second by a signal of 1 MHz */
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#define MHZ_TICKS_PER_SEC 1000000U
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/* Maximum time-stamp value read from architectural counters */
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#ifdef __aarch64__
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#define MAX_TS UINT64_MAX
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@ -175,44 +175,39 @@ static int32_t tegra_bpmp_ipc_send_req_atomic(uint32_t mrq, void *p_out,
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if ((p_out == NULL) || (size_out > IVC_DATA_SZ_BYTES) ||
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(frame == NULL)) {
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ERROR("%s: invalid parameters, exiting\n", __func__);
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ret = -EINVAL;
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return -EINVAL;
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}
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if (ret == 0) {
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/* prepare the command frame */
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frame->mrq = mrq;
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frame->flags = FLAG_DO_ACK;
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p_fdata = frame->data;
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(void)memcpy(p_fdata, p_out, (size_t)size_out);
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/* prepare the command frame */
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frame->mrq = mrq;
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frame->flags = FLAG_DO_ACK;
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p_fdata = frame->data;
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(void)memcpy(p_fdata, p_out, (size_t)size_out);
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/* signal the slave */
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tegra_bpmp_signal_slave();
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/* signal the slave */
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tegra_bpmp_signal_slave();
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/* wait for slave to ack */
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ret = tegra_bpmp_wait_for_slave_ack();
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if (ret < 0) {
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ERROR("%s: wait for slave failed (%d)\n", __func__, ret);
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return ret;
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}
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/* wait for slave to ack */
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ret = tegra_bpmp_wait_for_slave_ack();
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if (ret != 0) {
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ERROR("failed waiting for the slave to ack\n");
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/* retrieve the response frame */
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if ((size_in <= IVC_DATA_SZ_BYTES) && (p_in != NULL)) {
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f_in = tegra_bpmp_get_cur_in_frame();
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if (f_in != NULL) {
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ERROR("Failed to get next input frame!\n");
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} else {
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(void)memcpy(p_in, p_fdata, (size_t)size_in);
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}
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}
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/* retrieve the response frame */
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if ((size_in <= IVC_DATA_SZ_BYTES) && (p_in != NULL) &&
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(ret == 0)) {
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f_in = tegra_bpmp_get_cur_in_frame();
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if (f_in != NULL) {
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ERROR("Failed to get next input frame!\n");
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} else {
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(void)memcpy(p_in, p_fdata, (size_t)size_in);
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}
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}
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if (ret == 0) {
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ret = tegra_bpmp_free_master();
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if (ret != 0) {
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ERROR("Failed to free master\n");
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}
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}
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ret = tegra_bpmp_free_master();
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if (ret < 0) {
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ERROR("%s: free master failed (%d)\n", __func__, ret);
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}
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return ret;
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@ -1,5 +1,6 @@
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/*
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* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -10,6 +11,7 @@
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#define CONSOLE_FLUSH_DATA_TO_PORT (1 << 26)
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#define CONSOLE_RING_DOORBELL (1 << 31)
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#define CONSOLE_IS_BUSY (1 << 31)
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#define CONSOLE_TIMEOUT 0xC000 /* approx. 50 ms */
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#define CONSOLE_WRITE (CONSOLE_RING_DOORBELL | CONSOLE_FLUSH_DATA_TO_PORT)
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/*
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@ -30,6 +32,20 @@
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.globl console_spe_flush
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.globl console_spe_register
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.macro check_if_console_is_ready base, tmp1, tmp2, label
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/* wait until spe is ready or timeout expires */
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mrs \tmp2, cntps_tval_el1
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1: ldr \tmp1, [\base]
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and \tmp1, \tmp1, #CONSOLE_IS_BUSY
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cbz \tmp1, 2f
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mrs \tmp1, cntps_tval_el1
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sub \tmp1, \tmp2, \tmp1
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cmp \tmp1, #CONSOLE_TIMEOUT
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b.lt 1b
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b \label
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2:
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.endm
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/* -------------------------------------------------
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* int console_spe_register(uintptr_t baseaddr,
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* uint32_t clock, uint32_t baud,
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@ -46,6 +62,12 @@
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* -------------------------------------------------
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*/
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func console_spe_register
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/* Check the input base address */
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cbz x0, register_fail
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/* Dont use clock or baud rate, so ok to overwrite them */
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check_if_console_is_ready x0, x1, x2, register_fail
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cbz x3, register_fail
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str x0, [x3, #CONSOLE_T_DRVDATA]
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mov x0, x3
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@ -63,7 +85,7 @@ endfunc console_spe_register
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* In : w0 - character to be printed
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* x1 - console base address
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* Out : return -1 on error else return character.
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* Clobber list : x2
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* Clobber list : x2, x3
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* --------------------------------------------------------
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*/
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func console_spe_core_putc
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@ -72,12 +94,9 @@ func console_spe_core_putc
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/* Prepend '\r' to '\n' */
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cmp w0, #0xA
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b.ne 2f
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b.ne not_eol
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/* wait until spe is ready */
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1: ldr w2, [x1]
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and w2, w2, #CONSOLE_IS_BUSY
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cbnz w2, 1b
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check_if_console_is_ready x1, x2, x3, putc_error
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/* spe is ready */
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mov w2, #0xD /* '\r' */
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@ -86,10 +105,8 @@ func console_spe_core_putc
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orr w2, w2, w3
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str w2, [x1]
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/* wait until spe is ready */
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2: ldr w2, [x1]
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and w2, w2, #CONSOLE_IS_BUSY
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cbnz w2, 2b
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not_eol:
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check_if_console_is_ready x1, x2, x3, putc_error
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/* spe is ready */
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mov w2, w0
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|
|
|
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|
@ -1,5 +1,6 @@
|
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/*
|
||||
* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
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|
|
@ -34,8 +35,6 @@
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/* length of Trusty's input parameters (in bytes) */
|
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#define TRUSTY_PARAMS_LEN_BYTES (4096*2)
|
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|
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extern void memcpy16(void *dest, const void *src, unsigned int length);
|
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|
||||
/*******************************************************************************
|
||||
* Declarations of linker defined symbols which will help us find the layout
|
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* of trusted SRAM
|
||||
|
|
@ -101,8 +100,6 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
|
|||
{
|
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struct tegra_bl31_params *arg_from_bl2 = (struct tegra_bl31_params *) arg0;
|
||||
plat_params_from_bl2_t *plat_params = (plat_params_from_bl2_t *)arg1;
|
||||
image_info_t bl32_img_info = { {0} };
|
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uint64_t tzdram_start, tzdram_end, bl32_start, bl32_end;
|
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int32_t ret;
|
||||
|
||||
/*
|
||||
|
|
@ -163,20 +160,17 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
|
|||
* location to store the boot profiler logs. Sanity check the
|
||||
* address and initialise the profiler library, if it looks ok.
|
||||
*/
|
||||
if (plat_params->boot_profiler_shmem_base != 0ULL) {
|
||||
ret = bl31_check_ns_address(plat_params->boot_profiler_shmem_base,
|
||||
PROFILER_SIZE_BYTES);
|
||||
if (ret == (int32_t)0) {
|
||||
|
||||
ret = bl31_check_ns_address(plat_params->boot_profiler_shmem_base,
|
||||
PROFILER_SIZE_BYTES);
|
||||
if (ret == (int32_t)0) {
|
||||
/* store the membase for the profiler lib */
|
||||
plat_bl31_params_from_bl2.boot_profiler_shmem_base =
|
||||
plat_params->boot_profiler_shmem_base;
|
||||
|
||||
/* store the membase for the profiler lib */
|
||||
plat_bl31_params_from_bl2.boot_profiler_shmem_base =
|
||||
plat_params->boot_profiler_shmem_base;
|
||||
|
||||
/* initialise the profiler library */
|
||||
boot_profiler_init(plat_params->boot_profiler_shmem_base,
|
||||
TEGRA_TMRUS_BASE);
|
||||
}
|
||||
/* initialise the profiler library */
|
||||
boot_profiler_init(plat_params->boot_profiler_shmem_base,
|
||||
TEGRA_TMRUS_BASE);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -198,41 +192,14 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
|
|||
tegra_memctrl_tzdram_setup(plat_bl31_params_from_bl2.tzdram_base,
|
||||
(uint32_t)plat_bl31_params_from_bl2.tzdram_size);
|
||||
|
||||
#if RELOCATE_BL32_IMAGE
|
||||
/*
|
||||
* The previous bootloader might not have placed the BL32 image
|
||||
* inside the TZDRAM. We check the BL32 image info to find out
|
||||
* the base/PC values and relocate the image if necessary.
|
||||
* inside the TZDRAM. Platform handler to allow relocation of BL32
|
||||
* image to TZDRAM memory. This behavior might change per platform.
|
||||
*/
|
||||
if (arg_from_bl2->bl32_image_info != NULL) {
|
||||
|
||||
bl32_img_info = *arg_from_bl2->bl32_image_info;
|
||||
|
||||
/* Relocate BL32 if it resides outside of the TZDRAM */
|
||||
tzdram_start = plat_bl31_params_from_bl2.tzdram_base;
|
||||
tzdram_end = plat_bl31_params_from_bl2.tzdram_base +
|
||||
plat_bl31_params_from_bl2.tzdram_size;
|
||||
bl32_start = bl32_img_info.image_base;
|
||||
bl32_end = bl32_img_info.image_base + bl32_img_info.image_size;
|
||||
|
||||
assert(tzdram_end > tzdram_start);
|
||||
assert(bl32_end > bl32_start);
|
||||
assert(bl32_image_ep_info.pc > tzdram_start);
|
||||
assert(bl32_image_ep_info.pc < tzdram_end);
|
||||
|
||||
/* relocate BL32 */
|
||||
if ((bl32_start >= tzdram_end) || (bl32_end <= tzdram_start)) {
|
||||
|
||||
INFO("Relocate BL32 to TZDRAM\n");
|
||||
|
||||
(void)memcpy16((void *)(uintptr_t)bl32_image_ep_info.pc,
|
||||
(void *)(uintptr_t)bl32_start,
|
||||
bl32_img_info.image_size);
|
||||
|
||||
/* clean up non-secure intermediate buffer */
|
||||
zeromem((void *)(uintptr_t)bl32_start,
|
||||
bl32_img_info.image_size);
|
||||
}
|
||||
}
|
||||
plat_relocate_bl32_image(arg_from_bl2->bl32_image_info);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Add timestamp for platform early setup exit.
|
||||
|
|
|
|||
|
|
@ -1,31 +1,59 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <arch.h>
|
||||
|
||||
#include <drivers/delay_timer.h>
|
||||
#include <lib/mmio.h>
|
||||
#include <lib/utils_def.h>
|
||||
#include <plat/common/platform.h>
|
||||
|
||||
#include <tegra_def.h>
|
||||
#include <tegra_private.h>
|
||||
|
||||
static uint32_t tegra_timerus_get_value(void)
|
||||
static uint32_t tegra_timer_get_value(void)
|
||||
{
|
||||
return mmio_read_32(TEGRA_TMRUS_BASE);
|
||||
/* enable cntps_tval_el1 timer, mask interrupt */
|
||||
write_cntps_ctl_el1(CNTP_CTL_IMASK_BIT | CNTP_CTL_ENABLE_BIT);
|
||||
|
||||
/*
|
||||
* Generic delay timer implementation expects the timer to be a down
|
||||
* counter. We apply bitwise NOT operator to the tick values returned
|
||||
* by read_cntps_tval_el1() to simulate the down counter. The value is
|
||||
* clipped from 64 to 32 bits.
|
||||
*/
|
||||
return (uint32_t)(~read_cntps_tval_el1());
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialise the on-chip free rolling us counter as the delay
|
||||
* timer.
|
||||
* Initialise the architecture provided counter as the delay timer.
|
||||
*/
|
||||
void tegra_delay_timer_init(void)
|
||||
{
|
||||
static const timer_ops_t tegra_timer_ops = {
|
||||
.get_timer_value = tegra_timerus_get_value,
|
||||
.clk_mult = 1,
|
||||
.clk_div = 1,
|
||||
};
|
||||
static timer_ops_t tegra_timer_ops;
|
||||
|
||||
/* Value in ticks */
|
||||
uint32_t multiplier = MHZ_TICKS_PER_SEC;
|
||||
|
||||
/* Value in ticks per second (Hz) */
|
||||
uint32_t divider = plat_get_syscnt_freq2();
|
||||
|
||||
/* Reduce multiplier and divider by dividing them repeatedly by 10 */
|
||||
while (((multiplier % 10U) == 0U) && ((divider % 10U) == 0U)) {
|
||||
multiplier /= 10U;
|
||||
divider /= 10U;
|
||||
}
|
||||
|
||||
/* enable cntps_tval_el1 timer, mask interrupt */
|
||||
write_cntps_ctl_el1(CNTP_CTL_IMASK_BIT | CNTP_CTL_ENABLE_BIT);
|
||||
|
||||
/* register the timer */
|
||||
tegra_timer_ops.get_timer_value = tegra_timer_get_value;
|
||||
tegra_timer_ops.clk_mult = multiplier;
|
||||
tegra_timer_ops.clk_div = divider;
|
||||
timer_init(&tegra_timer_ops);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -259,7 +259,7 @@ int32_t tegra_validate_ns_entrypoint(uintptr_t entrypoint)
|
|||
/*******************************************************************************
|
||||
* Export the platform handlers to enable psci to invoke them
|
||||
******************************************************************************/
|
||||
static const plat_psci_ops_t tegra_plat_psci_ops = {
|
||||
static plat_psci_ops_t tegra_plat_psci_ops = {
|
||||
.cpu_standby = tegra_cpu_standby,
|
||||
.pwr_domain_on = tegra_pwr_domain_on,
|
||||
.pwr_domain_off = tegra_pwr_domain_off,
|
||||
|
|
@ -295,6 +295,14 @@ int plat_setup_psci_ops(uintptr_t sec_entrypoint,
|
|||
*/
|
||||
(void)tegra_soc_pwr_domain_on_finish(&target_state);
|
||||
|
||||
/*
|
||||
* Disable System Suspend if the platform does not
|
||||
* support it
|
||||
*/
|
||||
if (!plat_supports_system_suspend()) {
|
||||
tegra_plat_psci_ops.get_sys_suspend_power_state = NULL;
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize PSCI ops struct
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@
|
|||
#define TEGRA_PRIVATE_H
|
||||
|
||||
#include <platform_def.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#include <arch.h>
|
||||
#include <arch_helpers.h>
|
||||
|
|
@ -77,6 +78,8 @@ struct tegra_bl31_params *plat_get_bl31_params(void);
|
|||
plat_params_from_bl2_t *plat_get_bl31_plat_params(void);
|
||||
void plat_early_platform_setup(void);
|
||||
void plat_late_platform_setup(void);
|
||||
void plat_relocate_bl32_image(const image_info_t *bl32_img_info);
|
||||
bool plat_supports_system_suspend(void);
|
||||
|
||||
/* Declarations for plat_secondary.c */
|
||||
void plat_secondary_setup(void);
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
#
|
||||
# Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
|
||||
# Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
|
@ -37,9 +38,19 @@ WARMBOOT_ENABLE_DCACHE_EARLY := 1
|
|||
# remove the standard libc
|
||||
OVERRIDE_LIBC := 1
|
||||
|
||||
# Flag to enable WDT FIQ interrupt handling for Tegra SoCs
|
||||
# prior to Tegra186
|
||||
ENABLE_WDT_LEGACY_FIQ_HANDLING ?= 0
|
||||
|
||||
# Flag to allow relocation of BL32 image to TZDRAM during boot
|
||||
RELOCATE_BL32_IMAGE ?= 0
|
||||
|
||||
include plat/nvidia/tegra/common/tegra_common.mk
|
||||
include ${SOC_DIR}/platform_${TARGET_SOC}.mk
|
||||
|
||||
$(eval $(call add_define,ENABLE_WDT_LEGACY_FIQ_HANDLING))
|
||||
$(eval $(call add_define,RELOCATE_BL32_IMAGE))
|
||||
|
||||
# modify BUILD_PLAT to point to SoC specific build directory
|
||||
BUILD_PLAT := ${BUILD_BASE}/${PLAT}/${TARGET_SOC}/${BUILD_TYPE}
|
||||
|
||||
|
|
|
|||
|
|
@ -154,3 +154,11 @@ void plat_late_platform_setup(void)
|
|||
{
|
||||
; /* do nothing */
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Handler to indicate support for System Suspend
|
||||
******************************************************************************/
|
||||
bool plat_supports_system_suspend(void)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@
|
|||
#include <bl31/interrupt_mgmt.h>
|
||||
#include <common/bl_common.h>
|
||||
#include <common/debug.h>
|
||||
#include <common/ep_info.h>
|
||||
#include <common/interrupt_props.h>
|
||||
#include <context.h>
|
||||
#include <cortex_a57.h>
|
||||
|
|
@ -20,6 +21,7 @@
|
|||
#include <drivers/arm/gicv2.h>
|
||||
#include <drivers/console.h>
|
||||
#include <lib/el3_runtime/context_mgmt.h>
|
||||
#include <lib/utils.h>
|
||||
#include <lib/xlat_tables/xlat_tables_v2.h>
|
||||
#include <plat/common/platform.h>
|
||||
|
||||
|
|
@ -28,6 +30,8 @@
|
|||
#include <tegra_platform.h>
|
||||
#include <tegra_private.h>
|
||||
|
||||
extern void memcpy16(void *dest, const void *src, unsigned int length);
|
||||
|
||||
/*******************************************************************************
|
||||
* Tegra186 CPU numbers in cluster #0
|
||||
*******************************************************************************
|
||||
|
|
@ -286,3 +290,50 @@ int32_t plat_core_pos_by_mpidr(u_register_t mpidr)
|
|||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Handler to relocate BL32 image to TZDRAM
|
||||
******************************************************************************/
|
||||
void plat_relocate_bl32_image(const image_info_t *bl32_img_info)
|
||||
{
|
||||
const plat_params_from_bl2_t *plat_bl31_params = plat_get_bl31_plat_params();
|
||||
const entry_point_info_t *bl32_ep_info = bl31_plat_get_next_image_ep_info(SECURE);
|
||||
uint64_t tzdram_start, tzdram_end, bl32_start, bl32_end;
|
||||
|
||||
if ((bl32_img_info != NULL) && (bl32_ep_info != NULL)) {
|
||||
|
||||
/* Relocate BL32 if it resides outside of the TZDRAM */
|
||||
tzdram_start = plat_bl31_params->tzdram_base;
|
||||
tzdram_end = plat_bl31_params->tzdram_base +
|
||||
plat_bl31_params->tzdram_size;
|
||||
bl32_start = bl32_img_info->image_base;
|
||||
bl32_end = bl32_img_info->image_base + bl32_img_info->image_size;
|
||||
|
||||
assert(tzdram_end > tzdram_start);
|
||||
assert(bl32_end > bl32_start);
|
||||
assert(bl32_ep_info->pc > tzdram_start);
|
||||
assert(bl32_ep_info->pc < tzdram_end);
|
||||
|
||||
/* relocate BL32 */
|
||||
if ((bl32_start >= tzdram_end) || (bl32_end <= tzdram_start)) {
|
||||
|
||||
INFO("Relocate BL32 to TZDRAM\n");
|
||||
|
||||
(void)memcpy16((void *)(uintptr_t)bl32_ep_info->pc,
|
||||
(void *)(uintptr_t)bl32_start,
|
||||
bl32_img_info->image_size);
|
||||
|
||||
/* clean up non-secure intermediate buffer */
|
||||
zeromem((void *)(uintptr_t)bl32_start,
|
||||
bl32_img_info->image_size);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Handler to indicate support for System Suspend
|
||||
******************************************************************************/
|
||||
bool plat_supports_system_suspend(void)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
#
|
||||
# Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
|
||||
# Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
|
@ -17,6 +18,8 @@ PROGRAMMABLE_RESET_ADDRESS := 1
|
|||
|
||||
COLD_BOOT_SINGLE_CPU := 1
|
||||
|
||||
RELOCATE_BL32_IMAGE := 1
|
||||
|
||||
# platform settings
|
||||
TZDRAM_BASE := 0x30000000
|
||||
$(eval $(call add_define,TZDRAM_BASE))
|
||||
|
|
@ -64,3 +67,6 @@ ERRATA_A57_826977 := 1
|
|||
ERRATA_A57_828024 := 1
|
||||
ERRATA_A57_829520 := 1
|
||||
ERRATA_A57_833471 := 1
|
||||
|
||||
# Enable higher performance Non-cacheable load forwarding
|
||||
A57_ENABLE_NONCACHEABLE_LOAD_FWD := 1
|
||||
|
|
|
|||
|
|
@ -145,13 +145,13 @@ const static uint32_t tegra194_streamid_override_regs[] = {
|
|||
* Array to hold the security configs for stream IDs
|
||||
******************************************************************************/
|
||||
const static mc_streamid_security_cfg_t tegra194_streamid_sec_cfgs[] = {
|
||||
mc_make_sec_cfg(HDAR, NON_SECURE, OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(HOST1XDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(NVENCSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(SATAR, NON_SECURE, OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(NVENCSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(HDAW, NON_SECURE, OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(SATAW, NON_SECURE, OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(HDAR, NON_SECURE, OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(HOST1XDMAR, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(NVENCSRD, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(SATAR, NON_SECURE, OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(NVENCSWR, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(HDAW, NON_SECURE, OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(SATAW, NON_SECURE, OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(ISPRA, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(ISPFALR, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(ISPWA, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
|
|
@ -160,115 +160,115 @@ const static mc_streamid_security_cfg_t tegra194_streamid_sec_cfgs[] = {
|
|||
mc_make_sec_cfg(XUSB_HOSTW, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(XUSB_DEVR, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(XUSB_DEVW, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(TSECSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(TSECSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(SDMMCRA, NON_SECURE, OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(SDMMCR, NON_SECURE, OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(SDMMCRAB, NON_SECURE, OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(SDMMCWA, NON_SECURE, OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(SDMMCW, NON_SECURE, OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(SDMMCWAB, NON_SECURE, OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(VICSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(VICSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(TSECSRD, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(TSECSWR, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(SDMMCRA, NON_SECURE, OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(SDMMCR, NON_SECURE, OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(SDMMCRAB, NON_SECURE, OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(SDMMCWA, NON_SECURE, OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(SDMMCW, NON_SECURE, OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(SDMMCWAB, NON_SECURE, OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(VICSRD, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(VICSWR, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(VIW, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(NVDECSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(NVDECSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(APER, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(APEW, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(NVJPGSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(NVJPGSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(SESRD, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(SESWR, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(AXIAPR, NON_SECURE, OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(AXIAPW, NON_SECURE, OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(ETRR, NON_SECURE, OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(ETRW, NON_SECURE, OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(TSECSRDB, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(TSECSWRB, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(NVDECSRD, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(NVDECSWR, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(APER, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(APEW, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(NVJPGSRD, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(NVJPGSWR, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(SESRD, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(SESWR, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(AXIAPR, NON_SECURE, OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(AXIAPW, NON_SECURE, OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(ETRR, NON_SECURE, OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(ETRW, NON_SECURE, OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(TSECSRDB, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(TSECSWRB, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(AXISR, SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(AXISW, SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(EQOSR, NON_SECURE, OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(EQOSW, NON_SECURE, OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(UFSHCR, NON_SECURE, OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(UFSHCW, NON_SECURE, OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(NVDISPLAYR, NON_SECURE, OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(BPMPR, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(BPMPW, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(BPMPDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(BPMPDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(AONR, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(AONW, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(AONDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(AONDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(SCER, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(SCEW, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(SCEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(SCEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(APEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(APEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(NVDISPLAYR1, NON_SECURE, OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(VICSRD1, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(NVDECSRD1, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(EQOSR, NON_SECURE, OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(EQOSW, NON_SECURE, OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(UFSHCR, NON_SECURE, OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(UFSHCW, NON_SECURE, OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(NVDISPLAYR, NON_SECURE, OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(BPMPR, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(BPMPW, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(BPMPDMAR, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(BPMPDMAW, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(AONR, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(AONW, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(AONDMAR, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(AONDMAW, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(SCER, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(SCEW, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(SCEDMAR, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(SCEDMAW, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(APEDMAR, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(APEDMAW, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(NVDISPLAYR1, NON_SECURE, OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(VICSRD1, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(NVDECSRD1, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(VIFALR, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(VIFALW, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(DLA0RDA, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(DLA0FALRDB, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(DLA0WRA, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(DLA0FALWRB, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(DLA1RDA, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(DLA1FALRDB, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(DLA1WRA, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(DLA1FALWRB, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(PVA0RDA, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(PVA0RDB, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(PVA0RDC, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(PVA0WRA, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(PVA0WRB, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(PVA0WRC, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(PVA1RDA, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(PVA1RDB, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(PVA1RDC, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(PVA1WRA, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(PVA1WRB, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(PVA1WRC, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(RCER, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(RCEW, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(RCEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(RCEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(NVENC1SRD, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(NVENC1SWR, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(PCIE0R, NON_SECURE, OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(PCIE0W, NON_SECURE, OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(PCIE1R, NON_SECURE, OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(PCIE1W, NON_SECURE, OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(PCIE2AR, NON_SECURE, OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(PCIE2AW, NON_SECURE, OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(PCIE3R, NON_SECURE, OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(PCIE3W, NON_SECURE, OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(PCIE4R, NON_SECURE, OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(PCIE4W, NON_SECURE, OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(PCIE5R, NON_SECURE, OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(PCIE5W, NON_SECURE, OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(DLA0RDA, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(DLA0FALRDB, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(DLA0WRA, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(DLA0FALWRB, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(DLA1RDA, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(DLA1FALRDB, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(DLA1WRA, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(DLA1FALWRB, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(PVA0RDA, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(PVA0RDB, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(PVA0RDC, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(PVA0WRA, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(PVA0WRB, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(PVA0WRC, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(PVA1RDA, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(PVA1RDB, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(PVA1RDC, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(PVA1WRA, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(PVA1WRB, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(PVA1WRC, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(RCER, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(RCEW, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(RCEDMAR, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(RCEDMAW, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(NVENC1SRD, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(NVENC1SWR, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(PCIE0R, NON_SECURE, OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(PCIE0W, NON_SECURE, OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(PCIE1R, NON_SECURE, OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(PCIE1W, NON_SECURE, OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(PCIE2AR, NON_SECURE, OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(PCIE2AW, NON_SECURE, OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(PCIE3R, NON_SECURE, OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(PCIE3W, NON_SECURE, OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(PCIE4R, NON_SECURE, OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(PCIE4W, NON_SECURE, OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(PCIE5R, NON_SECURE, OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(PCIE5W, NON_SECURE, OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(ISPFALW, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(DLA0RDA1, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(DLA1RDA1, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(PVA0RDA1, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(PVA0RDB1, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(PVA1RDA1, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(PVA1RDB1, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(PCIE5R1, NON_SECURE, OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(NVENCSRD1, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(NVENC1SRD1, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(DLA0RDA1, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(DLA1RDA1, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(PVA0RDA1, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(PVA0RDB1, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(PVA1RDA1, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(PVA1RDB1, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(PCIE5R1, NON_SECURE, OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(NVENCSRD1, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(NVENC1SRD1, NON_SECURE, NO_OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(ISPRA1, NON_SECURE, NO_OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(PCIE0R1, NON_SECURE, OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(MIU0R, NON_SECURE, OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(MIU0W, NON_SECURE, OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(MIU1R, NON_SECURE, OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(MIU1W, NON_SECURE, OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(MIU2R, NON_SECURE, OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(MIU2W, NON_SECURE, OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(MIU3R, NON_SECURE, OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(MIU3W, NON_SECURE, OVERRIDE, ENABLE),
|
||||
mc_make_sec_cfg(PCIE0R1, NON_SECURE, OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(MIU0R, NON_SECURE, OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(MIU0W, NON_SECURE, OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(MIU1R, NON_SECURE, OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(MIU1W, NON_SECURE, OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(MIU2R, NON_SECURE, OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(MIU2W, NON_SECURE, OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(MIU3R, NON_SECURE, OVERRIDE, DISABLE),
|
||||
mc_make_sec_cfg(MIU3W, NON_SECURE, OVERRIDE, DISABLE)
|
||||
};
|
||||
|
||||
/* To be called by common memctrl_v2.c */
|
||||
|
|
|
|||
|
|
@ -304,6 +304,9 @@ plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
|
|||
return (plat_params_from_bl2_t *)(uintptr_t)val;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Handler for late platform setup
|
||||
******************************************************************************/
|
||||
void plat_late_platform_setup(void)
|
||||
{
|
||||
#if ENABLE_STRICT_CHECKING_MODE
|
||||
|
|
@ -314,3 +317,11 @@ void plat_late_platform_setup(void)
|
|||
mce_enable_strict_checking();
|
||||
#endif
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Handler to indicate support for System Suspend
|
||||
******************************************************************************/
|
||||
bool plat_supports_system_suspend(void)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -394,6 +394,15 @@ int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state)
|
|||
*/
|
||||
tegra_reset_all_dma_masters();
|
||||
|
||||
/*
|
||||
* Mark PMC as accessible to the non-secure world
|
||||
* to allow the COP to execute System Suspend
|
||||
* sequence
|
||||
*/
|
||||
val = mmio_read_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE);
|
||||
val &= ~PMC_SECURITY_EN_BIT;
|
||||
mmio_write_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE, val);
|
||||
|
||||
/* clean up IRAM of any cruft */
|
||||
zeromem((void *)(uintptr_t)TEGRA_IRAM_BASE,
|
||||
TEGRA_IRAM_A_SIZE);
|
||||
|
|
@ -480,12 +489,14 @@ int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
|
|||
tegra_bpmp_resume();
|
||||
}
|
||||
|
||||
/* sc7entry-fw is part of TZDRAM area */
|
||||
if (plat_params->sc7entry_fw_base != 0U) {
|
||||
/* sc7entry-fw is part of TZDRAM area */
|
||||
offset = plat_params->tzdram_base - plat_params->sc7entry_fw_base;
|
||||
tegra_memctrl_tzdram_setup(plat_params->sc7entry_fw_base,
|
||||
plat_params->tzdram_size + offset);
|
||||
}
|
||||
|
||||
if (!tegra_chipid_is_t210_b01()) {
|
||||
/* restrict PMC access to secure world */
|
||||
val = mmio_read_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE);
|
||||
val |= PMC_SECURITY_EN_BIT;
|
||||
|
|
@ -533,10 +544,11 @@ int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
|
|||
tegra_fc_lock_active_cluster();
|
||||
|
||||
/*
|
||||
* Resume PMC hardware block for Tegra210 platforms supporting sc7entry-fw
|
||||
*/
|
||||
if (!tegra_chipid_is_t210_b01() && (plat_params->sc7entry_fw_base != 0U))
|
||||
* Resume PMC hardware block for Tegra210 platforms
|
||||
*/
|
||||
if (!tegra_chipid_is_t210_b01()) {
|
||||
tegra_pmc_resume();
|
||||
}
|
||||
|
||||
return PSCI_E_SUCCESS;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -236,6 +236,13 @@ void plat_late_platform_setup(void)
|
|||
val |= PMC_SECURITY_EN_BIT;
|
||||
mmio_write_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE, val);
|
||||
}
|
||||
|
||||
if (!tegra_chipid_is_t210_b01()) {
|
||||
/* restrict PMC access to secure world */
|
||||
val = mmio_read_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE);
|
||||
val |= PMC_SECURITY_EN_BIT;
|
||||
mmio_write_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE, val);
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
|
|
@ -255,3 +262,21 @@ void plat_gic_setup(void)
|
|||
*/
|
||||
tegra_fc_enable_fiq_to_ccplex_routing();
|
||||
}
|
||||
/*******************************************************************************
|
||||
* Handler to indicate support for System Suspend
|
||||
******************************************************************************/
|
||||
bool plat_supports_system_suspend(void)
|
||||
{
|
||||
const plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
|
||||
|
||||
/*
|
||||
* sc7entry-fw is only supported by Tegra210 SoCs.
|
||||
*/
|
||||
if (!tegra_chipid_is_t210_b01() && (plat_params->sc7entry_fw_base != 0U)) {
|
||||
return true;
|
||||
} else if (tegra_chipid_is_t210_b01()) {
|
||||
return true;
|
||||
} else {
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -57,3 +57,6 @@ ERRATA_A53_855873 := 1
|
|||
|
||||
# Skip L1 $ flush when powering down Cortex-A57 CPUs
|
||||
SKIP_A57_L1_FLUSH_PWR_DWN := 1
|
||||
|
||||
# Enable higher performance Non-cacheable load forwarding
|
||||
A57_ENABLE_NONCACHEABLE_LOAD_FWD := 1
|
||||
|
|
|
|||
Loading…
Reference in New Issue