AArch32: Add essential ARM platform and FVP support
This patch adds AArch32 support for FVP and implements common platform APIs like `plat_get_my_stack`, `plat_set_my_stack`, `plat_my_core_cos` for AArch32. Only Multi Processor(MP) implementations of these functions are considered in this patch. The ARM Standard platform layer helpers are implemented for AArch32 and the common makefiles are modified to cater for both AArch64 and AArch32 builds. Compatibility with the deprecated platform API is not supported for AArch32. Change-Id: Iad228400613eec91abf731b49e21a15bcf2833ea
This commit is contained in:
Soby Mathew
parent
c11ba852b9
commit
877cf3ff12
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@ -321,9 +321,12 @@
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# error "Unsupported ARM_TSP_RAM_LOCATION_ID value"
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#endif
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/* BL32 is mandatory in AArch32 */
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#ifndef AARCH32
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#ifdef SPD_none
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#undef BL32_BASE
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#endif /* SPD_none */
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#endif
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/*******************************************************************************
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* FWU Images: NS_BL1U, BL2U & NS_BL2U defines.
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@ -31,8 +31,10 @@
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PLAT_INCLUDES += -Iinclude/plat/arm/board/common/ \
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-Iinclude/plat/arm/board/common/drivers
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PLAT_BL_COMMON_SOURCES += drivers/arm/pl011/aarch64/pl011_console.S \
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plat/arm/board/common/aarch64/board_arm_helpers.S
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PLAT_BL_COMMON_SOURCES += drivers/arm/pl011/${ARCH}/pl011_console.S
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ifeq (${ARCH}, aarch64)
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PLAT_BL_COMMON_SOURCES += plat/arm/board/common/aarch64/board_arm_helpers.S
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endif
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BL1_SOURCES += plat/arm/board/common/drivers/norflash/norflash.c
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@ -0,0 +1,115 @@
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <platform_def.h>
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#include "../drivers/pwrc/fvp_pwrc.h"
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#include "../fvp_def.h"
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.globl plat_get_my_entrypoint
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.globl plat_is_my_cpu_primary
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/* ---------------------------------------------------------------------
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* unsigned long plat_get_my_entrypoint (void);
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*
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* Main job of this routine is to distinguish between a cold and warm
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* boot. On FVP, this information can be queried from the power
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* controller. The Power Control SYS Status Register (PSYSR) indicates
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* the wake-up reason for the CPU.
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*
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* For a cold boot, return 0.
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* For a warm boot, read the mailbox and return the address it contains.
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*
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* TODO: PSYSR is a common register and should be
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* accessed using locks. Since it is not possible
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* to use locks immediately after a cold reset
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* we are relying on the fact that after a cold
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* reset all cpus will read the same WK field
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* ---------------------------------------------------------------------
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*/
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func plat_get_my_entrypoint
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/* ---------------------------------------------------------------------
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* When bit PSYSR.WK indicates either "Wake by PPONR" or "Wake by GIC
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* WakeRequest signal" then it is a warm boot.
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* ---------------------------------------------------------------------
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*/
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ldcopr r2, MPIDR
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ldr r1, =PWRC_BASE
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str r2, [r1, #PSYSR_OFF]
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ldr r2, [r1, #PSYSR_OFF]
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ubfx r2, r2, #PSYSR_WK_SHIFT, #PSYSR_WK_WIDTH
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cmp r2, #WKUP_PPONR
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beq warm_reset
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cmp r2, #WKUP_GICREQ
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beq warm_reset
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/* Cold reset */
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mov r0, #0
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bx lr
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warm_reset:
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/* ---------------------------------------------------------------------
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* A mailbox is maintained in the trusted SRAM. It is flushed out of the
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* caches after every update using normal memory so it is safe to read
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* it here with SO attributes.
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* ---------------------------------------------------------------------
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*/
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ldr r0, =PLAT_ARM_TRUSTED_MAILBOX_BASE
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ldr r0, [r0]
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cmp r0, #0
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beq _panic
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bx lr
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/* ---------------------------------------------------------------------
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* The power controller indicates this is a warm reset but the mailbox
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* is empty. This should never happen!
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* ---------------------------------------------------------------------
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*/
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_panic:
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b _panic
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endfunc plat_get_my_entrypoint
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/* -----------------------------------------------------
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* unsigned int plat_is_my_cpu_primary (void);
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*
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* Find out whether the current cpu is the primary
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* cpu.
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* -----------------------------------------------------
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*/
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func plat_is_my_cpu_primary
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ldcopr r0, MPIDR
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ldr r1, =(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
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and r0, r1
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cmp r0, #FVP_PRIMARY_CPU
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moveq r0, #1
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movne r0, #0
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bx lr
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endfunc plat_is_my_cpu_primary
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@ -121,6 +121,9 @@ const mmap_region_t plat_arm_mmap[] = {
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#endif
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#if IMAGE_BL32
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const mmap_region_t plat_arm_mmap[] = {
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#ifdef AARCH32
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ARM_MAP_SHARED_RAM,
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#endif
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V2M_MAP_IOFPGA,
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MAP_DEVICE0,
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MAP_DEVICE1,
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@ -69,6 +69,9 @@ FVP_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
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plat/common/plat_gicv2.c \
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plat/arm/common/arm_gicv2.c
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else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3_LEGACY)
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ifeq (${ARCH}, aarch32)
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$(error "GICV3 Legacy driver not supported for AArch32 build")
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endif
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FVP_GIC_SOURCES := drivers/arm/gic/arm_gic.c \
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drivers/arm/gic/gic_v2.c \
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drivers/arm/gic/gic_v3.c \
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@ -98,12 +101,15 @@ PLAT_INCLUDES := -Iplat/arm/board/fvp/include
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PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c
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FVP_CPU_LIBS := lib/cpus/aarch64/aem_generic.S \
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lib/cpus/aarch64/cortex_a35.S \
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FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S
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ifeq (${ARCH}, aarch64)
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FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \
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lib/cpus/aarch64/cortex_a53.S \
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lib/cpus/aarch64/cortex_a57.S \
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lib/cpus/aarch64/cortex_a72.S \
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lib/cpus/aarch64/cortex_a73.S
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endif
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BL1_SOURCES += drivers/io/io_semihosting.c \
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lib/semihosting/semihosting.c \
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@ -0,0 +1,59 @@
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <asm_macros.S>
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#include <platform_def.h>
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.weak plat_arm_calc_core_pos
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.weak plat_my_core_pos
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/* -----------------------------------------------------
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* unsigned int plat_my_core_pos(void)
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* This function uses the plat_arm_calc_core_pos()
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* definition to get the index of the calling CPU.
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* -----------------------------------------------------
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*/
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func plat_my_core_pos
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ldcopr r0, MPIDR
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b plat_arm_calc_core_pos
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endfunc plat_my_core_pos
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/* -----------------------------------------------------
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* unsigned int plat_arm_calc_core_pos(uint64_t mpidr)
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* Helper function to calculate the core position.
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* With this function: CorePos = (ClusterId * 4) +
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* CoreId
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* -----------------------------------------------------
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*/
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func plat_arm_calc_core_pos
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and r1, r0, #MPIDR_CPU_MASK
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and r0, r0, #MPIDR_CLUSTER_MASK
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add r0, r1, r0, LSR #6
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bx lr
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endfunc plat_arm_calc_core_pos
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@ -134,6 +134,7 @@ uint32_t arm_get_spsr_for_bl32_entry(void)
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/*******************************************************************************
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* Gets SPSR for BL33 entry
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******************************************************************************/
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#ifndef AARCH32
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uint32_t arm_get_spsr_for_bl33_entry(void)
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{
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unsigned long el_status;
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@ -154,6 +155,28 @@ uint32_t arm_get_spsr_for_bl33_entry(void)
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spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
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return spsr;
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}
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#else
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/*******************************************************************************
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* Gets SPSR for BL33 entry
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******************************************************************************/
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uint32_t arm_get_spsr_for_bl33_entry(void)
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{
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unsigned int hyp_status, mode, spsr;
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hyp_status = GET_VIRT_EXT(read_id_pfr1());
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mode = (hyp_status) ? MODE32_hyp : MODE32_svc;
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/*
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* TODO: Consider the possibility of specifying the SPSR in
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* the FIP ToC and allowing the platform to have a say as
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* well.
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*/
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spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1,
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SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
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return spsr;
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}
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#endif /* AARCH32 */
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/*******************************************************************************
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* Configures access to the system counter timer module.
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@ -28,24 +28,31 @@
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# POSSIBILITY OF SUCH DAMAGE.
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#
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# On ARM standard platorms, the TSP can execute from Trusted SRAM, Trusted
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# DRAM (if available) or the TZC secured area of DRAM.
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# Trusted SRAM is the default.
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ifeq (${ARCH}, aarch64)
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# On ARM standard platorms, the TSP can execute from Trusted SRAM, Trusted
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# DRAM (if available) or the TZC secured area of DRAM.
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# Trusted SRAM is the default.
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ARM_TSP_RAM_LOCATION := tsram
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ifeq (${ARM_TSP_RAM_LOCATION}, tsram)
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ARM_TSP_RAM_LOCATION_ID = ARM_TRUSTED_SRAM_ID
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else ifeq (${ARM_TSP_RAM_LOCATION}, tdram)
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ARM_TSP_RAM_LOCATION_ID = ARM_TRUSTED_DRAM_ID
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else ifeq (${ARM_TSP_RAM_LOCATION}, dram)
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ARM_TSP_RAM_LOCATION_ID = ARM_DRAM_ID
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else
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$(error "Unsupported ARM_TSP_RAM_LOCATION value")
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ARM_TSP_RAM_LOCATION := tsram
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ifeq (${ARM_TSP_RAM_LOCATION}, tsram)
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ARM_TSP_RAM_LOCATION_ID = ARM_TRUSTED_SRAM_ID
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else ifeq (${ARM_TSP_RAM_LOCATION}, tdram)
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ARM_TSP_RAM_LOCATION_ID = ARM_TRUSTED_DRAM_ID
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else ifeq (${ARM_TSP_RAM_LOCATION}, dram)
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ARM_TSP_RAM_LOCATION_ID = ARM_DRAM_ID
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else
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$(error "Unsupported ARM_TSP_RAM_LOCATION value")
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endif
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# Process flags
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$(eval $(call add_define,ARM_TSP_RAM_LOCATION_ID))
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# Process ARM_BL31_IN_DRAM flag
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ARM_BL31_IN_DRAM := 0
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$(eval $(call assert_boolean,ARM_BL31_IN_DRAM))
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$(eval $(call add_define,ARM_BL31_IN_DRAM))
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endif
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# Process flags
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$(eval $(call add_define,ARM_TSP_RAM_LOCATION_ID))
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# For the original power-state parameter format, the State-ID can be encoded
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# according to the recommended encoding or zero. This flag determines which
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# State-ID encoding to be parsed.
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@ -83,7 +90,7 @@ $(eval $(call assert_boolean,ARM_BL31_IN_DRAM))
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$(eval $(call add_define,ARM_BL31_IN_DRAM))
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# Enable PSCI_STAT_COUNT/RESIDENCY APIs on ARM platforms
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ENABLE_PSCI_STAT = 1
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ENABLE_PSCI_STAT := 1
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# On ARM platforms, separate the code and read-only data sections to allow
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# mapping the former as executable and the latter as execute-never.
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@ -91,15 +98,17 @@ SEPARATE_CODE_AND_RODATA := 1
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PLAT_INCLUDES += -Iinclude/common/tbbr \
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-Iinclude/plat/arm/common \
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-Iinclude/plat/arm/common/aarch64
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-Iinclude/plat/arm/common
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ifeq (${ARCH}, aarch64)
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PLAT_INCLUDES += -Iinclude/plat/arm/common/aarch64
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endif
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PLAT_BL_COMMON_SOURCES += lib/xlat_tables/xlat_tables_common.c \
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lib/xlat_tables/aarch64/xlat_tables.c \
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plat/arm/common/aarch64/arm_helpers.S \
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lib/xlat_tables/${ARCH}/xlat_tables.c \
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plat/arm/common/${ARCH}/arm_helpers.S \
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plat/arm/common/arm_common.c \
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plat/common/aarch64/plat_common.c
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plat/common/${ARCH}/plat_common.c
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BL1_SOURCES += drivers/arm/sp805/sp805.c \
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drivers/io/io_fip.c \
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@ -77,7 +77,7 @@ void plat_arm_gic_driver_init(void)
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* can use GIC system registers to manage interrupts and does
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* not need GIC interface base addresses to be configured.
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*/
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#if IMAGE_BL31
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#if (AARCH32 && IMAGE_BL32) || (IMAGE_BL31 && !AARCH32)
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gicv3_driver_init(&arm_gic_data);
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#endif
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}
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@ -0,0 +1,44 @@
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
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* Neither the name of ARM nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific
|
||||
* prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
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* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
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#include <platform.h>
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#include <xlat_tables.h>
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/*
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* The following platform setup functions are weakly defined. They
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* provide typical implementations that may be re-used by multiple
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* platforms but may also be overridden by a platform if required.
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*/
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#pragma weak bl32_plat_enable_mmu
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void bl32_plat_enable_mmu(uint32_t flags)
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{
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enable_mmu_secure(flags);
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}
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@ -0,0 +1,78 @@
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* Neither the name of ARM nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific
|
||||
* prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <arch.h>
|
||||
#include <asm_macros.S>
|
||||
|
||||
.weak plat_my_core_pos
|
||||
.weak plat_reset_handler
|
||||
.weak platform_mem_init
|
||||
.weak plat_panic_handler
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* int plat_my_core_pos(void);
|
||||
* With this function: CorePos = (ClusterId * 4) +
|
||||
* CoreId
|
||||
* -----------------------------------------------------
|
||||
*/
|
||||
func plat_my_core_pos
|
||||
ldcopr r0, MPIDR
|
||||
and r1, r0, #MPIDR_CPU_MASK
|
||||
and r0, r0, #MPIDR_CLUSTER_MASK
|
||||
add r0, r1, r0, LSR #6
|
||||
bx lr
|
||||
endfunc plat_my_core_pos
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* Placeholder function which should be redefined by
|
||||
* each platform.
|
||||
* -----------------------------------------------------
|
||||
*/
|
||||
func plat_reset_handler
|
||||
bx lr
|
||||
endfunc plat_reset_handler
|
||||
|
||||
/* ---------------------------------------------------------------------
|
||||
* Placeholder function which should be redefined by
|
||||
* each platform.
|
||||
* ---------------------------------------------------------------------
|
||||
*/
|
||||
func platform_mem_init
|
||||
bx lr
|
||||
endfunc platform_mem_init
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* void plat_panic_handler(void) __dead2;
|
||||
* Endless loop by default.
|
||||
* -----------------------------------------------------
|
||||
*/
|
||||
func plat_panic_handler
|
||||
b plat_panic_handler
|
||||
endfunc plat_panic_handler
|
||||
|
|
@ -0,0 +1,71 @@
|
|||
/*
|
||||
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* Neither the name of ARM nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific
|
||||
* prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <arch.h>
|
||||
#include <asm_macros.S>
|
||||
#include <platform_def.h>
|
||||
|
||||
.globl plat_get_my_stack
|
||||
.globl plat_set_my_stack
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* uintptr_t plat_get_my_stack (u_register_t mpidr)
|
||||
*
|
||||
* For a given CPU, this function returns the stack
|
||||
* pointer for a stack allocated in device memory.
|
||||
* -----------------------------------------------------
|
||||
*/
|
||||
func plat_get_my_stack
|
||||
mov r3, lr
|
||||
get_my_mp_stack platform_normal_stacks, PLATFORM_STACK_SIZE
|
||||
bx r3
|
||||
endfunc plat_get_my_stack
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* void plat_set_my_stack ()
|
||||
*
|
||||
* For the current CPU, this function sets the stack
|
||||
* pointer to a stack allocated in normal memory.
|
||||
* -----------------------------------------------------
|
||||
*/
|
||||
func plat_set_my_stack
|
||||
mov r3, lr
|
||||
get_my_mp_stack platform_normal_stacks, PLATFORM_STACK_SIZE
|
||||
mov sp, r0
|
||||
bx r3
|
||||
endfunc plat_set_my_stack
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* Per-cpu stacks in normal memory. Each cpu gets a
|
||||
* stack of PLATFORM_STACK_SIZE bytes.
|
||||
* -----------------------------------------------------
|
||||
*/
|
||||
declare_stack platform_normal_stacks, tzfw_normal_stacks, \
|
||||
PLATFORM_STACK_SIZE, PLATFORM_CORE_COUNT
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
|
|
@ -186,6 +186,11 @@ uint32_t plat_interrupt_type_to_line(uint32_t type,
|
|||
#pragma weak plat_ic_acknowledge_interrupt
|
||||
#pragma weak plat_ic_end_of_interrupt
|
||||
|
||||
/* In AArch32, the secure group1 interrupts are targeted to Secure PL1 */
|
||||
#ifdef AARCH32
|
||||
#define IS_IN_EL1() IS_IN_SECURE()
|
||||
#endif
|
||||
|
||||
/*
|
||||
* This function returns the highest priority pending interrupt at
|
||||
* the Interrupt controller
|
||||
|
|
|
|||
|
|
@ -33,6 +33,9 @@ ifeq (${PSCI_EXTENDED_STATE_ID}, 1)
|
|||
PSCI_EXTENDED_STATE_ID is not set")
|
||||
endif
|
||||
|
||||
ifneq (${ARCH}, aarch64)
|
||||
$(error "PSCI Compatibility mode is only supported for AArch64 platforms")
|
||||
endif
|
||||
|
||||
PLAT_BL_COMMON_SOURCES += plat/compat/aarch64/plat_helpers_compat.S
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue