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gic: Fix definitions 

Change-Id: I945029ca26ea2e63f0d92c5f33019b882f23bd72
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
This commit is contained in:
Antonio Nino Diaz 2018-08-24 11:46:33 +01:00
parent b9f68dfbfe
commit 8782922c25
4 changed files with 182 additions and 182 deletions
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4
drivers/arm/gic/v3/gicv3_private.h
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@ -19,8 +19,8 @@
******************************************************************************/ ******************************************************************************/
/* Constants to indicate the status of the RWP bit */ /* Constants to indicate the status of the RWP bit */
#define RWP_TRUE 1 #define RWP_TRUE U(1)
#define RWP_FALSE 0 #define RWP_FALSE U(0)
/* /*
* Macro to convert an mpidr to a value suitable for programming into a * Macro to convert an mpidr to a value suitable for programming into a

60
include/drivers/arm/gic_common.h
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@ -13,23 +13,23 @@
* GIC Distributor interface general definitions * GIC Distributor interface general definitions
******************************************************************************/ ******************************************************************************/
/* Constants to categorise interrupts */ /* Constants to categorise interrupts */
#define MIN_SGI_ID 0 #define MIN_SGI_ID U(0)
#define MIN_SEC_SGI_ID 8 #define MIN_SEC_SGI_ID U(8)
#define MIN_PPI_ID 16 #define MIN_PPI_ID U(16)
#define MIN_SPI_ID 32 #define MIN_SPI_ID U(32)
#define MAX_SPI_ID 1019 #define MAX_SPI_ID U(1019)
#define TOTAL_SPI_INTR_NUM (MAX_SPI_ID - MIN_SPI_ID + 1) #define TOTAL_SPI_INTR_NUM (MAX_SPI_ID - MIN_SPI_ID + U(1))
#define TOTAL_PCPU_INTR_NUM (MIN_SPI_ID - MIN_SGI_ID) #define TOTAL_PCPU_INTR_NUM (MIN_SPI_ID - MIN_SGI_ID)
/* Mask for the priority field common to all GIC interfaces */ /* Mask for the priority field common to all GIC interfaces */
#define GIC_PRI_MASK 0xff #define GIC_PRI_MASK U(0xff)
/* Mask for the configuration field common to all GIC interfaces */ /* Mask for the configuration field common to all GIC interfaces */
#define GIC_CFG_MASK 0x3 #define GIC_CFG_MASK U(0x3)
/* Constant to indicate a spurious interrupt in all GIC versions */ /* Constant to indicate a spurious interrupt in all GIC versions */
#define GIC_SPURIOUS_INTERRUPT 1023 #define GIC_SPURIOUS_INTERRUPT U(1023)
/* Interrupt configurations: 2-bit fields with LSB reserved */ /* Interrupt configurations: 2-bit fields with LSB reserved */
#define GIC_INTR_CFG_LEVEL (0 << 1) #define GIC_INTR_CFG_LEVEL (0 << 1)
@ -44,38 +44,38 @@
/******************************************************************************* /*******************************************************************************
* GIC Distributor interface register offsets that are common to GICv3 & GICv2 * GIC Distributor interface register offsets that are common to GICv3 & GICv2
******************************************************************************/ ******************************************************************************/
#define GICD_CTLR 0x0 #define GICD_CTLR U(0x0)
#define GICD_TYPER 0x4 #define GICD_TYPER U(0x4)
#define GICD_IIDR 0x8 #define GICD_IIDR U(0x8)
#define GICD_IGROUPR 0x80 #define GICD_IGROUPR U(0x80)
#define GICD_ISENABLER 0x100 #define GICD_ISENABLER U(0x100)
#define GICD_ICENABLER 0x180 #define GICD_ICENABLER U(0x180)
#define GICD_ISPENDR 0x200 #define GICD_ISPENDR U(0x200)
#define GICD_ICPENDR 0x280 #define GICD_ICPENDR U(0x280)
#define GICD_ISACTIVER 0x300 #define GICD_ISACTIVER U(0x300)
#define GICD_ICACTIVER 0x380 #define GICD_ICACTIVER U(0x380)
#define GICD_IPRIORITYR 0x400 #define GICD_IPRIORITYR U(0x400)
#define GICD_ICFGR 0xc00 #define GICD_ICFGR U(0xc00)
#define GICD_NSACR 0xe00 #define GICD_NSACR U(0xe00)
/* GICD_CTLR bit definitions */ /* GICD_CTLR bit definitions */
#define CTLR_ENABLE_G0_SHIFT 0 #define CTLR_ENABLE_G0_SHIFT 0
#define CTLR_ENABLE_G0_MASK 0x1 #define CTLR_ENABLE_G0_MASK U(0x1)
#define CTLR_ENABLE_G0_BIT (1 << CTLR_ENABLE_G0_SHIFT) #define CTLR_ENABLE_G0_BIT BIT_32(CTLR_ENABLE_G0_SHIFT)
/******************************************************************************* /*******************************************************************************
* GIC Distributor interface register constants that are common to GICv3 & GICv2 * GIC Distributor interface register constants that are common to GICv3 & GICv2
******************************************************************************/ ******************************************************************************/
#define PIDR2_ARCH_REV_SHIFT 4 #define PIDR2_ARCH_REV_SHIFT 4
#define PIDR2_ARCH_REV_MASK 0xf #define PIDR2_ARCH_REV_MASK U(0xf)
/* GICv3 revision as reported by the PIDR2 register */ /* GICv3 revision as reported by the PIDR2 register */
#define ARCH_REV_GICV3 0x3 #define ARCH_REV_GICV3 U(0x3)
/* GICv2 revision as reported by the PIDR2 register */ /* GICv2 revision as reported by the PIDR2 register */
#define ARCH_REV_GICV2 0x2 #define ARCH_REV_GICV2 U(0x2)
/* GICv1 revision as reported by the PIDR2 register */ /* GICv1 revision as reported by the PIDR2 register */
#define ARCH_REV_GICV1 0x1 #define ARCH_REV_GICV1 U(0x1)
#define IGROUPR_SHIFT 5 #define IGROUPR_SHIFT 5
#define ISENABLER_SHIFT 5 #define ISENABLER_SHIFT 5
@ -90,8 +90,8 @@
#define NSACR_SHIFT 4 #define NSACR_SHIFT 4
/* GICD_TYPER shifts and masks */ /* GICD_TYPER shifts and masks */
#define TYPER_IT_LINES_NO_SHIFT 0 #define TYPER_IT_LINES_NO_SHIFT U(0)
#define TYPER_IT_LINES_NO_MASK 0x1f #define TYPER_IT_LINES_NO_MASK U(0x1f)
/* Value used to initialize Normal world interrupt priorities four at a time */ /* Value used to initialize Normal world interrupt priorities four at a time */
#define GICD_IPRIORITYR_DEF_VAL \ #define GICD_IPRIORITYR_DEF_VAL \

108
include/drivers/arm/gicv2.h
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@ -12,37 +12,37 @@
******************************************************************************/ ******************************************************************************/
/* Interrupt group definitions */ /* Interrupt group definitions */
#define GICV2_INTR_GROUP0 0 #define GICV2_INTR_GROUP0 U(0)
#define GICV2_INTR_GROUP1 1 #define GICV2_INTR_GROUP1 U(1)
/* Interrupt IDs reported by the HPPIR and IAR registers */ /* Interrupt IDs reported by the HPPIR and IAR registers */
#define PENDING_G1_INTID 1022 #define PENDING_G1_INTID U(1022)
/* GICv2 can only target up to 8 PEs */ /* GICv2 can only target up to 8 PEs */
#define GICV2_MAX_TARGET_PE 8 #define GICV2_MAX_TARGET_PE U(8)
/******************************************************************************* /*******************************************************************************
* GICv2 specific Distributor interface register offsets and constants. * GICv2 specific Distributor interface register offsets and constants.
******************************************************************************/ ******************************************************************************/
#define GICD_ITARGETSR 0x800 #define GICD_ITARGETSR U(0x800)
#define GICD_SGIR 0xF00 #define GICD_SGIR U(0xF00)
#define GICD_CPENDSGIR 0xF10 #define GICD_CPENDSGIR U(0xF10)
#define GICD_SPENDSGIR 0xF20 #define GICD_SPENDSGIR U(0xF20)
#define GICD_PIDR2_GICV2 0xFE8 #define GICD_PIDR2_GICV2 U(0xFE8)
#define ITARGETSR_SHIFT 2 #define ITARGETSR_SHIFT 2
#define GIC_TARGET_CPU_MASK 0xff #define GIC_TARGET_CPU_MASK U(0xff)
#define CPENDSGIR_SHIFT 2 #define CPENDSGIR_SHIFT 2
#define SPENDSGIR_SHIFT CPENDSGIR_SHIFT #define SPENDSGIR_SHIFT CPENDSGIR_SHIFT
#define SGIR_TGTLSTFLT_SHIFT 24 #define SGIR_TGTLSTFLT_SHIFT 24
#define SGIR_TGTLSTFLT_MASK 0x3 #define SGIR_TGTLSTFLT_MASK U(0x3)
#define SGIR_TGTLST_SHIFT 16 #define SGIR_TGTLST_SHIFT 16
#define SGIR_TGTLST_MASK 0xff #define SGIR_TGTLST_MASK U(0xff)
#define SGIR_INTID_MASK 0xf #define SGIR_INTID_MASK ULL(0xf)
#define SGIR_TGT_SPECIFIC 0 #define SGIR_TGT_SPECIFIC U(0)
#define GICV2_SGIR_VALUE(tgt_lst_flt, tgt, intid) \ #define GICV2_SGIR_VALUE(tgt_lst_flt, tgt, intid) \
((((tgt_lst_flt) & SGIR_TGTLSTFLT_MASK) << SGIR_TGTLSTFLT_SHIFT) | \ ((((tgt_lst_flt) & SGIR_TGTLSTFLT_MASK) << SGIR_TGTLSTFLT_SHIFT) | \
@ -53,29 +53,29 @@
* GICv2 specific CPU interface register offsets and constants. * GICv2 specific CPU interface register offsets and constants.
******************************************************************************/ ******************************************************************************/
/* Physical CPU Interface registers */ /* Physical CPU Interface registers */
#define GICC_CTLR 0x0 #define GICC_CTLR U(0x0)
#define GICC_PMR 0x4 #define GICC_PMR U(0x4)
#define GICC_BPR 0x8 #define GICC_BPR U(0x8)
#define GICC_IAR 0xC #define GICC_IAR U(0xC)
#define GICC_EOIR 0x10 #define GICC_EOIR U(0x10)
#define GICC_RPR 0x14 #define GICC_RPR U(0x14)
#define GICC_HPPIR 0x18 #define GICC_HPPIR U(0x18)
#define GICC_AHPPIR 0x28 #define GICC_AHPPIR U(0x28)
#define GICC_IIDR 0xFC #define GICC_IIDR U(0xFC)
#define GICC_DIR 0x1000 #define GICC_DIR U(0x1000)
#define GICC_PRIODROP GICC_EOIR #define GICC_PRIODROP GICC_EOIR
/* GICC_CTLR bit definitions */ /* GICC_CTLR bit definitions */
#define EOI_MODE_NS (1 << 10) #define EOI_MODE_NS BIT_32(10)
#define EOI_MODE_S (1 << 9) #define EOI_MODE_S BIT_32(9)
#define IRQ_BYP_DIS_GRP1 (1 << 8) #define IRQ_BYP_DIS_GRP1 BIT_32(8)
#define FIQ_BYP_DIS_GRP1 (1 << 7) #define FIQ_BYP_DIS_GRP1 BIT_32(7)
#define IRQ_BYP_DIS_GRP0 (1 << 6) #define IRQ_BYP_DIS_GRP0 BIT_32(6)
#define FIQ_BYP_DIS_GRP0 (1 << 5) #define FIQ_BYP_DIS_GRP0 BIT_32(5)
#define CBPR (1 << 4) #define CBPR BIT_32(4)
#define FIQ_EN_SHIFT 3 #define FIQ_EN_SHIFT 3
#define FIQ_EN_BIT (1 << FIQ_EN_SHIFT) #define FIQ_EN_BIT BIT_32(FIQ_EN_SHIFT)
#define ACK_CTL (1 << 2) #define ACK_CTL BIT_32(2)
/* GICC_IIDR bit masks and shifts */ /* GICC_IIDR bit masks and shifts */
#define GICC_IIDR_PID_SHIFT 20 #define GICC_IIDR_PID_SHIFT 20
@ -83,36 +83,36 @@
#define GICC_IIDR_REV_SHIFT 12 #define GICC_IIDR_REV_SHIFT 12
#define GICC_IIDR_IMP_SHIFT 0 #define GICC_IIDR_IMP_SHIFT 0
#define GICC_IIDR_PID_MASK 0xfff #define GICC_IIDR_PID_MASK U(0xfff)
#define GICC_IIDR_ARCH_MASK 0xf #define GICC_IIDR_ARCH_MASK U(0xf)
#define GICC_IIDR_REV_MASK 0xf #define GICC_IIDR_REV_MASK U(0xf)
#define GICC_IIDR_IMP_MASK 0xfff #define GICC_IIDR_IMP_MASK U(0xfff)
/* HYP view virtual CPU Interface registers */ /* HYP view virtual CPU Interface registers */
#define GICH_CTL 0x0 #define GICH_CTL U(0x0)
#define GICH_VTR 0x4 #define GICH_VTR U(0x4)
#define GICH_ELRSR0 0x30 #define GICH_ELRSR0 U(0x30)
#define GICH_ELRSR1 0x34 #define GICH_ELRSR1 U(0x34)
#define GICH_APR0 0xF0 #define GICH_APR0 U(0xF0)
#define GICH_LR_BASE 0x100 #define GICH_LR_BASE U(0x100)
/* Virtual CPU Interface registers */ /* Virtual CPU Interface registers */
#define GICV_CTL 0x0 #define GICV_CTL U(0x0)
#define GICV_PRIMASK 0x4 #define GICV_PRIMASK U(0x4)
#define GICV_BP 0x8 #define GICV_BP U(0x8)
#define GICV_INTACK 0xC #define GICV_INTACK U(0xC)
#define GICV_EOI 0x10 #define GICV_EOI U(0x10)
#define GICV_RUNNINGPRI 0x14 #define GICV_RUNNINGPRI U(0x14)
#define GICV_HIGHESTPEND 0x18 #define GICV_HIGHESTPEND U(0x18)
#define GICV_DEACTIVATE 0x1000 #define GICV_DEACTIVATE U(0x1000)
/* GICD_CTLR bit definitions */ /* GICD_CTLR bit definitions */
#define CTLR_ENABLE_G1_SHIFT 1 #define CTLR_ENABLE_G1_SHIFT 1
#define CTLR_ENABLE_G1_MASK 0x1 #define CTLR_ENABLE_G1_MASK U(0x1)
#define CTLR_ENABLE_G1_BIT (1 << CTLR_ENABLE_G1_SHIFT) #define CTLR_ENABLE_G1_BIT BIT_32(CTLR_ENABLE_G1_SHIFT)
/* Interrupt ID mask for HPPIR, AHPPIR, IAR and AIAR CPU Interface registers */ /* Interrupt ID mask for HPPIR, AHPPIR, IAR and AIAR CPU Interface registers */
#define INT_ID_MASK 0x3ff #define INT_ID_MASK U(0x3ff)
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__

192
include/drivers/arm/gicv3.h
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@ -11,35 +11,35 @@
* GICv3 miscellaneous definitions * GICv3 miscellaneous definitions
******************************************************************************/ ******************************************************************************/
/* Interrupt group definitions */ /* Interrupt group definitions */
#define INTR_GROUP1S 0 #define INTR_GROUP1S U(0)
#define INTR_GROUP0 1 #define INTR_GROUP0 U(1)
#define INTR_GROUP1NS 2 #define INTR_GROUP1NS U(2)
/* Interrupt IDs reported by the HPPIR and IAR registers */ /* Interrupt IDs reported by the HPPIR and IAR registers */
#define PENDING_G1S_INTID 1020 #define PENDING_G1S_INTID U(1020)
#define PENDING_G1NS_INTID 1021 #define PENDING_G1NS_INTID U(1021)
/* Constant to categorize LPI interrupt */ /* Constant to categorize LPI interrupt */
#define MIN_LPI_ID 8192 #define MIN_LPI_ID U(8192)
/* GICv3 can only target up to 16 PEs with SGI */ /* GICv3 can only target up to 16 PEs with SGI */
#define GICV3_MAX_SGI_TARGETS 16 #define GICV3_MAX_SGI_TARGETS U(16)
/******************************************************************************* /*******************************************************************************
* GICv3 specific Distributor interface register offsets and constants. * GICv3 specific Distributor interface register offsets and constants.
******************************************************************************/ ******************************************************************************/
#define GICD_STATUSR 0x10 #define GICD_STATUSR U(0x10)
#define GICD_SETSPI_NSR 0x40 #define GICD_SETSPI_NSR U(0x40)
#define GICD_CLRSPI_NSR 0x48 #define GICD_CLRSPI_NSR U(0x48)
#define GICD_SETSPI_SR 0x50 #define GICD_SETSPI_SR U(0x50)
#define GICD_CLRSPI_SR 0x50 #define GICD_CLRSPI_SR U(0x50)
#define GICD_IGRPMODR 0xd00 #define GICD_IGRPMODR U(0xd00)
/* /*
* GICD_IROUTER<n> register is at 0x6000 + 8n, where n is the interrupt id and * GICD_IROUTER<n> register is at 0x6000 + 8n, where n is the interrupt id and
* n >= 32, making the effective offset as 0x6100. * n >= 32, making the effective offset as 0x6100.
*/ */
#define GICD_IROUTER 0x6000 #define GICD_IROUTER U(0x6000)
#define GICD_PIDR2_GICV3 0xffe8 #define GICD_PIDR2_GICV3 U(0xffe8)
#define IGRPMODR_SHIFT 5 #define IGRPMODR_SHIFT 5
@ -52,29 +52,29 @@
#define CTLR_E1NWF_SHIFT 7 #define CTLR_E1NWF_SHIFT 7
#define GICD_CTLR_RWP_SHIFT 31 #define GICD_CTLR_RWP_SHIFT 31
#define CTLR_ENABLE_G1NS_MASK 0x1 #define CTLR_ENABLE_G1NS_MASK U(0x1)
#define CTLR_ENABLE_G1S_MASK 0x1 #define CTLR_ENABLE_G1S_MASK U(0x1)
#define CTLR_ARE_S_MASK 0x1 #define CTLR_ARE_S_MASK U(0x1)
#define CTLR_ARE_NS_MASK 0x1 #define CTLR_ARE_NS_MASK U(0x1)
#define CTLR_DS_MASK 0x1 #define CTLR_DS_MASK U(0x1)
#define CTLR_E1NWF_MASK 0x1 #define CTLR_E1NWF_MASK U(0x1)
#define GICD_CTLR_RWP_MASK 0x1 #define GICD_CTLR_RWP_MASK U(0x1)
#define CTLR_ENABLE_G1NS_BIT (1 << CTLR_ENABLE_G1NS_SHIFT) #define CTLR_ENABLE_G1NS_BIT BIT_32(CTLR_ENABLE_G1NS_SHIFT)
#define CTLR_ENABLE_G1S_BIT (1 << CTLR_ENABLE_G1S_SHIFT) #define CTLR_ENABLE_G1S_BIT BIT_32(CTLR_ENABLE_G1S_SHIFT)
#define CTLR_ARE_S_BIT (1 << CTLR_ARE_S_SHIFT) #define CTLR_ARE_S_BIT BIT_32(CTLR_ARE_S_SHIFT)
#define CTLR_ARE_NS_BIT (1 << CTLR_ARE_NS_SHIFT) #define CTLR_ARE_NS_BIT BIT_32(CTLR_ARE_NS_SHIFT)
#define CTLR_DS_BIT (1 << CTLR_DS_SHIFT) #define CTLR_DS_BIT BIT_32(CTLR_DS_SHIFT)
#define CTLR_E1NWF_BIT (1 << CTLR_E1NWF_SHIFT) #define CTLR_E1NWF_BIT BIT_32(CTLR_E1NWF_SHIFT)
#define GICD_CTLR_RWP_BIT (1 << GICD_CTLR_RWP_SHIFT) #define GICD_CTLR_RWP_BIT BIT_32(GICD_CTLR_RWP_SHIFT)
/* GICD_IROUTER shifts and masks */ /* GICD_IROUTER shifts and masks */
#define IROUTER_SHIFT 0 #define IROUTER_SHIFT 0
#define IROUTER_IRM_SHIFT 31 #define IROUTER_IRM_SHIFT 31
#define IROUTER_IRM_MASK 0x1 #define IROUTER_IRM_MASK U(0x1)
#define GICV3_IRM_PE 0 #define GICV3_IRM_PE U(0)
#define GICV3_IRM_ANY 1 #define GICV3_IRM_ANY U(1)
#define NUM_OF_DIST_REGS 30 #define NUM_OF_DIST_REGS 30
@ -82,54 +82,54 @@
* GICv3 Re-distributor interface registers & constants * GICv3 Re-distributor interface registers & constants
******************************************************************************/ ******************************************************************************/
#define GICR_PCPUBASE_SHIFT 0x11 #define GICR_PCPUBASE_SHIFT 0x11
#define GICR_SGIBASE_OFFSET (1 << 0x10) /* 64 KB */ #define GICR_SGIBASE_OFFSET U(65536) /* 64 KB */
#define GICR_CTLR 0x0 #define GICR_CTLR U(0x0)
#define GICR_TYPER 0x08 #define GICR_TYPER U(0x08)
#define GICR_WAKER 0x14 #define GICR_WAKER U(0x14)
#define GICR_PROPBASER 0x70 #define GICR_PROPBASER U(0x70)
#define GICR_PENDBASER 0x78 #define GICR_PENDBASER U(0x78)
#define GICR_IGROUPR0 (GICR_SGIBASE_OFFSET + 0x80) #define GICR_IGROUPR0 (GICR_SGIBASE_OFFSET + U(0x80))
#define GICR_ISENABLER0 (GICR_SGIBASE_OFFSET + 0x100) #define GICR_ISENABLER0 (GICR_SGIBASE_OFFSET + U(0x100))
#define GICR_ICENABLER0 (GICR_SGIBASE_OFFSET + 0x180) #define GICR_ICENABLER0 (GICR_SGIBASE_OFFSET + U(0x180))
#define GICR_ISPENDR0 (GICR_SGIBASE_OFFSET + 0x200) #define GICR_ISPENDR0 (GICR_SGIBASE_OFFSET + U(0x200))
#define GICR_ICPENDR0 (GICR_SGIBASE_OFFSET + 0x280) #define GICR_ICPENDR0 (GICR_SGIBASE_OFFSET + U(0x280))
#define GICR_ISACTIVER0 (GICR_SGIBASE_OFFSET + 0x300) #define GICR_ISACTIVER0 (GICR_SGIBASE_OFFSET + U(0x300))
#define GICR_ICACTIVER0 (GICR_SGIBASE_OFFSET + 0x380) #define GICR_ICACTIVER0 (GICR_SGIBASE_OFFSET + U(0x380))
#define GICR_IPRIORITYR (GICR_SGIBASE_OFFSET + 0x400) #define GICR_IPRIORITYR (GICR_SGIBASE_OFFSET + U(0x400))
#define GICR_ICFGR0 (GICR_SGIBASE_OFFSET + 0xc00) #define GICR_ICFGR0 (GICR_SGIBASE_OFFSET + U(0xc00))
#define GICR_ICFGR1 (GICR_SGIBASE_OFFSET + 0xc04) #define GICR_ICFGR1 (GICR_SGIBASE_OFFSET + U(0xc04))
#define GICR_IGRPMODR0 (GICR_SGIBASE_OFFSET + 0xd00) #define GICR_IGRPMODR0 (GICR_SGIBASE_OFFSET + U(0xd00))
#define GICR_NSACR (GICR_SGIBASE_OFFSET + 0xe00) #define GICR_NSACR (GICR_SGIBASE_OFFSET + U(0xe00))
/* GICR_CTLR bit definitions */ /* GICR_CTLR bit definitions */
#define GICR_CTLR_UWP_SHIFT 31 #define GICR_CTLR_UWP_SHIFT 31
#define GICR_CTLR_UWP_MASK 0x1 #define GICR_CTLR_UWP_MASK U(0x1)
#define GICR_CTLR_UWP_BIT (1U << GICR_CTLR_UWP_SHIFT) #define GICR_CTLR_UWP_BIT BIT_32(GICR_CTLR_UWP_SHIFT)
#define GICR_CTLR_RWP_SHIFT 3 #define GICR_CTLR_RWP_SHIFT 3
#define GICR_CTLR_RWP_MASK 0x1 #define GICR_CTLR_RWP_MASK U(0x1)
#define GICR_CTLR_RWP_BIT (1U << GICR_CTLR_RWP_SHIFT) #define GICR_CTLR_RWP_BIT BIT_32(GICR_CTLR_RWP_SHIFT)
#define GICR_CTLR_EN_LPIS_BIT (1U << 0) #define GICR_CTLR_EN_LPIS_BIT BIT_32(0)
/* GICR_WAKER bit definitions */ /* GICR_WAKER bit definitions */
#define WAKER_CA_SHIFT 2 #define WAKER_CA_SHIFT 2
#define WAKER_PS_SHIFT 1 #define WAKER_PS_SHIFT 1
#define WAKER_CA_MASK 0x1 #define WAKER_CA_MASK U(0x1)
#define WAKER_PS_MASK 0x1 #define WAKER_PS_MASK U(0x1)
#define WAKER_CA_BIT (1 << WAKER_CA_SHIFT) #define WAKER_CA_BIT BIT_32(WAKER_CA_SHIFT)
#define WAKER_PS_BIT (1 << WAKER_PS_SHIFT) #define WAKER_PS_BIT BIT_32(WAKER_PS_SHIFT)
/* GICR_TYPER bit definitions */ /* GICR_TYPER bit definitions */
#define TYPER_AFF_VAL_SHIFT 32 #define TYPER_AFF_VAL_SHIFT 32
#define TYPER_PROC_NUM_SHIFT 8 #define TYPER_PROC_NUM_SHIFT 8
#define TYPER_LAST_SHIFT 4 #define TYPER_LAST_SHIFT 4
#define TYPER_AFF_VAL_MASK 0xffffffff #define TYPER_AFF_VAL_MASK U(0xffffffff)
#define TYPER_PROC_NUM_MASK 0xffff #define TYPER_PROC_NUM_MASK U(0xffff)
#define TYPER_LAST_MASK 0x1 #define TYPER_LAST_MASK U(0x1)
#define TYPER_LAST_BIT (1 << TYPER_LAST_SHIFT) #define TYPER_LAST_BIT BIT_32(TYPER_LAST_SHIFT)
#define NUM_OF_REDIST_REGS 30 #define NUM_OF_REDIST_REGS 30
@ -137,75 +137,75 @@
* GICv3 CPU interface registers & constants * GICv3 CPU interface registers & constants
******************************************************************************/ ******************************************************************************/
/* ICC_SRE bit definitions*/ /* ICC_SRE bit definitions*/
#define ICC_SRE_EN_BIT (1 << 3) #define ICC_SRE_EN_BIT BIT_32(3)
#define ICC_SRE_DIB_BIT (1 << 2) #define ICC_SRE_DIB_BIT BIT_32(2)
#define ICC_SRE_DFB_BIT (1 << 1) #define ICC_SRE_DFB_BIT BIT_32(1)
#define ICC_SRE_SRE_BIT (1 << 0) #define ICC_SRE_SRE_BIT BIT_32(0)
/* ICC_IGRPEN1_EL3 bit definitions */ /* ICC_IGRPEN1_EL3 bit definitions */
#define IGRPEN1_EL3_ENABLE_G1NS_SHIFT 0 #define IGRPEN1_EL3_ENABLE_G1NS_SHIFT 0
#define IGRPEN1_EL3_ENABLE_G1S_SHIFT 1 #define IGRPEN1_EL3_ENABLE_G1S_SHIFT 1
#define IGRPEN1_EL3_ENABLE_G1NS_BIT (1 << IGRPEN1_EL3_ENABLE_G1NS_SHIFT) #define IGRPEN1_EL3_ENABLE_G1NS_BIT BIT_32(IGRPEN1_EL3_ENABLE_G1NS_SHIFT)
#define IGRPEN1_EL3_ENABLE_G1S_BIT (1 << IGRPEN1_EL3_ENABLE_G1S_SHIFT) #define IGRPEN1_EL3_ENABLE_G1S_BIT BIT_32(IGRPEN1_EL3_ENABLE_G1S_SHIFT)
/* ICC_IGRPEN0_EL1 bit definitions */ /* ICC_IGRPEN0_EL1 bit definitions */
#define IGRPEN1_EL1_ENABLE_G0_SHIFT 0 #define IGRPEN1_EL1_ENABLE_G0_SHIFT 0
#define IGRPEN1_EL1_ENABLE_G0_BIT (1 << IGRPEN1_EL1_ENABLE_G0_SHIFT) #define IGRPEN1_EL1_ENABLE_G0_BIT BIT_32(IGRPEN1_EL1_ENABLE_G0_SHIFT)
/* ICC_HPPIR0_EL1 bit definitions */ /* ICC_HPPIR0_EL1 bit definitions */
#define HPPIR0_EL1_INTID_SHIFT 0 #define HPPIR0_EL1_INTID_SHIFT 0
#define HPPIR0_EL1_INTID_MASK 0xffffff #define HPPIR0_EL1_INTID_MASK U(0xffffff)
/* ICC_HPPIR1_EL1 bit definitions */ /* ICC_HPPIR1_EL1 bit definitions */
#define HPPIR1_EL1_INTID_SHIFT 0 #define HPPIR1_EL1_INTID_SHIFT 0
#define HPPIR1_EL1_INTID_MASK 0xffffff #define HPPIR1_EL1_INTID_MASK U(0xffffff)
/* ICC_IAR0_EL1 bit definitions */ /* ICC_IAR0_EL1 bit definitions */
#define IAR0_EL1_INTID_SHIFT 0 #define IAR0_EL1_INTID_SHIFT 0
#define IAR0_EL1_INTID_MASK 0xffffff #define IAR0_EL1_INTID_MASK U(0xffffff)
/* ICC_IAR1_EL1 bit definitions */ /* ICC_IAR1_EL1 bit definitions */
#define IAR1_EL1_INTID_SHIFT 0 #define IAR1_EL1_INTID_SHIFT 0
#define IAR1_EL1_INTID_MASK 0xffffff #define IAR1_EL1_INTID_MASK U(0xffffff)
/* ICC SGI macros */ /* ICC SGI macros */
#define SGIR_TGT_MASK 0xffff #define SGIR_TGT_MASK ULL(0xffff)
#define SGIR_AFF1_SHIFT 16 #define SGIR_AFF1_SHIFT 16
#define SGIR_INTID_SHIFT 24 #define SGIR_INTID_SHIFT 24
#define SGIR_INTID_MASK 0xf #define SGIR_INTID_MASK ULL(0xf)
#define SGIR_AFF2_SHIFT 32 #define SGIR_AFF2_SHIFT 32
#define SGIR_IRM_SHIFT 40 #define SGIR_IRM_SHIFT 40
#define SGIR_IRM_MASK 0x1 #define SGIR_IRM_MASK ULL(0x1)
#define SGIR_AFF3_SHIFT 48 #define SGIR_AFF3_SHIFT 48
#define SGIR_AFF_MASK 0xf #define SGIR_AFF_MASK ULL(0xf)
#define SGIR_IRM_TO_AFF 0 #define SGIR_IRM_TO_AFF U(0)
#define GICV3_SGIR_VALUE(aff3, aff2, aff1, intid, irm, tgt) \ #define GICV3_SGIR_VALUE(_aff3, _aff2, _aff1, _intid, _irm, _tgt) \
((((uint64_t) (aff3) & SGIR_AFF_MASK) << SGIR_AFF3_SHIFT) | \ ((((uint64_t) (_aff3) & SGIR_AFF_MASK) << SGIR_AFF3_SHIFT) | \
(((uint64_t) (irm) & SGIR_IRM_MASK) << SGIR_IRM_SHIFT) | \ (((uint64_t) (_irm) & SGIR_IRM_MASK) << SGIR_IRM_SHIFT) | \
(((uint64_t) (aff2) & SGIR_AFF_MASK) << SGIR_AFF2_SHIFT) | \ (((uint64_t) (_aff2) & SGIR_AFF_MASK) << SGIR_AFF2_SHIFT) | \
(((intid) & SGIR_INTID_MASK) << SGIR_INTID_SHIFT) | \ (((_intid) & SGIR_INTID_MASK) << SGIR_INTID_SHIFT) | \
(((aff1) & SGIR_AFF_MASK) << SGIR_AFF1_SHIFT) | \ (((_aff1) & SGIR_AFF_MASK) << SGIR_AFF1_SHIFT) | \
((tgt) & SGIR_TGT_MASK)) ((_tgt) & SGIR_TGT_MASK))
/***************************************************************************** /*****************************************************************************
* GICv3 ITS registers and constants * GICv3 ITS registers and constants
*****************************************************************************/ *****************************************************************************/
#define GITS_CTLR 0x0 #define GITS_CTLR U(0x0)
#define GITS_IIDR 0x4 #define GITS_IIDR U(0x4)
#define GITS_TYPER 0x8 #define GITS_TYPER U(0x8)
#define GITS_CBASER 0x80 #define GITS_CBASER U(0x80)
#define GITS_CWRITER 0x88 #define GITS_CWRITER U(0x88)
#define GITS_CREADR 0x90 #define GITS_CREADR U(0x90)
#define GITS_BASER 0x100 #define GITS_BASER U(0x100)
/* GITS_CTLR bit definitions */ /* GITS_CTLR bit definitions */
#define GITS_CTLR_ENABLED_BIT 1 #define GITS_CTLR_ENABLED_BIT BIT_32(0)
#define GITS_CTLR_QUIESCENT_SHIFT 31 #define GITS_CTLR_QUIESCENT_SHIFT 31
#define GITS_CTLR_QUIESCENT_BIT (1U << GITS_CTLR_QUIESCENT_SHIFT) #define GITS_CTLR_QUIESCENT_BIT BIT_32(GITS_CTLR_QUIESCENT_SHIFT)
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
@ -263,7 +263,7 @@ static inline void gicv3_end_of_interrupt(unsigned int id)
DIV_ROUND_UP_2EVAL(TOTAL_PCPU_INTR_NUM, (1 << reg_name ## _SHIFT)) DIV_ROUND_UP_2EVAL(TOTAL_PCPU_INTR_NUM, (1 << reg_name ## _SHIFT))
/* Interrupt ID mask for HPPIR, AHPPIR, IAR and AIAR CPU Interface registers */ /* Interrupt ID mask for HPPIR, AHPPIR, IAR and AIAR CPU Interface registers */
#define INT_ID_MASK 0xffffff #define INT_ID_MASK U(0xffffff)
/******************************************************************************* /*******************************************************************************
* This structure describes some of the implementation defined attributes of the * This structure describes some of the implementation defined attributes of the