From 87a1df73619e9031c970ea5e0813a3040cc80992 Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Thu, 23 Mar 2017 17:32:20 -0700 Subject: [PATCH] Tegra186: mce: add the mce_update_cstate_info() helper function This patch adds a helper function to the MCE driver to allow its clients to issue UPDATE_CSTATE_INFO requests, without having to setup the CPU context struct. We introduced a struct to encapsulate the request parameters, that clients can pass on to the MCE driver. The MCE driver gets the parameters from the struct and programs the hardware accordingly. Change-Id: I02bce57506c4ccd90da82127805d6b564375cbf1 Signed-off-by: Varun Wadekar --- .../tegra/soc/t186/drivers/include/mce.h | 19 +++++++++++++++++++ plat/nvidia/tegra/soc/t186/drivers/mce/mce.c | 13 +++++++++++++ 2 files changed, 32 insertions(+) diff --git a/plat/nvidia/tegra/soc/t186/drivers/include/mce.h b/plat/nvidia/tegra/soc/t186/drivers/include/mce.h index 606569236..38ca32c37 100644 --- a/plat/nvidia/tegra/soc/t186/drivers/include/mce.h +++ b/plat/nvidia/tegra/soc/t186/drivers/include/mce.h @@ -101,6 +101,24 @@ typedef enum mce_cmd { #define MCE_CMD_MASK 0xFF +/******************************************************************************* + * Struct to prepare UPDATE_CSTATE_INFO request + ******************************************************************************/ +typedef struct mce_cstate_info { + /* cluster cstate value */ + uint32_t cluster; + /* ccplex cstate value */ + uint32_t ccplex; + /* system cstate value */ + uint32_t system; + /* force system state? */ + uint8_t system_state_force; + /* wake mask value */ + uint32_t wake_mask; + /* update the wake mask? */ + uint8_t update_wake_mask; +} mce_cstate_info_t; + /******************************************************************************* * Macros to prepare CSTATE info request ******************************************************************************/ @@ -322,6 +340,7 @@ int mce_update_gsc_videomem(void); int mce_update_gsc_tzdram(void); int mce_update_gsc_tzram(void); __dead2 void mce_enter_ccplex_state(uint32_t state_idx); +void mce_update_cstate_info(mce_cstate_info_t *cstate); void mce_verify_firmware_version(void); /* declarations for ARI/NVG handler functions */ diff --git a/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c b/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c index 9d0d71fd6..1a712dcca 100644 --- a/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c +++ b/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c @@ -448,6 +448,19 @@ __dead2 void mce_enter_ccplex_state(uint32_t state_idx) panic(); } +/******************************************************************************* + * Handler to issue the UPDATE_CSTATE_INFO request + ******************************************************************************/ +void mce_update_cstate_info(mce_cstate_info_t *cstate) +{ + arch_mce_ops_t *ops = mce_get_curr_cpu_ops(); + + /* issue the UPDATE_CSTATE_INFO request */ + ops->update_cstate_info(mce_get_curr_cpu_ari_base(), cstate->cluster, + cstate->ccplex, cstate->system, cstate->system_state_force, + cstate->wake_mask, cstate->update_wake_mask); +} + /******************************************************************************* * Handler to read the MCE firmware version and check if it is compatible * with interface header the BL3-1 was compiled against