diff --git a/docs/plat/nvidia-tegra.md b/docs/plat/nvidia-tegra.md index b29532c91..f82085b13 100644 --- a/docs/plat/nvidia-tegra.md +++ b/docs/plat/nvidia-tegra.md @@ -62,6 +62,22 @@ TARGET_SOC= SPD= bl31' Platforms wanting to use different TZDRAM_BASE, can add 'TZDRAM_BASE=' to the build command line. +The Tegra platform code expects a pointer to the following platform specific +structure via 'x1' register from the BL2 layer which is used by the +bl31_early_platform_setup() handler to extract the TZDRAM carveout base and +size for loading the Trusted OS and the UART port ID to be used. The Tegra +memory controller driver programs this base/size in order to restrict NS +accesses. + +typedef struct plat_params_from_bl2 { + /* TZ memory size */ + uint64_t tzdram_size; + /* TZ memory base */ + uint64_t tzdram_base; + /* UART port ID */ + int uart_id; +} plat_params_from_bl2_t; + Power Management ================ The PSCI implementation expects each platform to expose the 'power state' diff --git a/include/lib/cpus/aarch64/denver.h b/include/lib/cpus/aarch64/denver.h index c7bee808e..0de094a4c 100644 --- a/include/lib/cpus/aarch64/denver.h +++ b/include/lib/cpus/aarch64/denver.h @@ -31,8 +31,15 @@ #ifndef __DENVER_H__ #define __DENVER_H__ -/* MIDR for Denver v1.0 */ -#define DENVER_1_0_MIDR 0x4E0F0000 +/* MIDR values for Denver */ +#define DENVER_MIDR_PN0 0x4E0F0000 +#define DENVER_MIDR_PN1 0x4E0F0010 +#define DENVER_MIDR_PN2 0x4E0F0020 +#define DENVER_MIDR_PN3 0x4E0F0030 +#define DENVER_MIDR_PN4 0x4E0F0040 + +/* Implementer code in the MIDR register */ +#define DENVER_IMPL 0x4E /* CPU state ids - implementation defined */ #define DENVER_CPU_STATE_POWER_DOWN 0x3 diff --git a/lib/cpus/aarch64/denver.S b/lib/cpus/aarch64/denver.S index 0b61440dd..c38515562 100644 --- a/lib/cpus/aarch64/denver.S +++ b/lib/cpus/aarch64/denver.S @@ -163,7 +163,27 @@ func denver_cpu_reg_dump ret endfunc denver_cpu_reg_dump -declare_cpu_ops denver, DENVER_1_0_MIDR, \ +declare_cpu_ops denver, DENVER_MIDR_PN0, \ + denver_reset_func, \ + denver_core_pwr_dwn, \ + denver_cluster_pwr_dwn + +declare_cpu_ops denver, DENVER_MIDR_PN1, \ + denver_reset_func, \ + denver_core_pwr_dwn, \ + denver_cluster_pwr_dwn + +declare_cpu_ops denver, DENVER_MIDR_PN2, \ + denver_reset_func, \ + denver_core_pwr_dwn, \ + denver_cluster_pwr_dwn + +declare_cpu_ops denver, DENVER_MIDR_PN3, \ + denver_reset_func, \ + denver_core_pwr_dwn, \ + denver_cluster_pwr_dwn + +declare_cpu_ops denver, DENVER_MIDR_PN4, \ denver_reset_func, \ denver_core_pwr_dwn, \ denver_cluster_pwr_dwn diff --git a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S index 905c4c5fe..6851b1502 100644 --- a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S +++ b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S @@ -35,6 +35,22 @@ #include #include +#define MIDR_PN_CORTEX_A57 0xD07 + +/******************************************************************************* + * Implementation defined ACTLR_EL3 bit definitions + ******************************************************************************/ +#define ACTLR_EL3_L2ACTLR_BIT (1 << 6) +#define ACTLR_EL3_L2ECTLR_BIT (1 << 5) +#define ACTLR_EL3_L2CTLR_BIT (1 << 4) +#define ACTLR_EL3_CPUECTLR_BIT (1 << 1) +#define ACTLR_EL3_CPUACTLR_BIT (1 << 0) +#define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \ + ACTLR_EL3_L2ECTLR_BIT | \ + ACTLR_EL3_L2CTLR_BIT | \ + ACTLR_EL3_CPUECTLR_BIT | \ + ACTLR_EL3_CPUACTLR_BIT) + /* Global functions */ .globl plat_is_my_cpu_primary .globl plat_my_core_pos @@ -50,6 +66,7 @@ .globl tegra_sec_entry_point .globl ns_image_entrypoint .globl tegra_bl31_phys_base + .globl tegra_console_base /* --------------------- * Common CPU init code @@ -57,7 +74,18 @@ */ .macro cpu_init_common -#if ENABLE_L2_DYNAMIC_RETENTION + /* ------------------------------------------------ + * We enable procesor retention and L2/CPUECTLR NS + * access for A57 CPUs only. + * ------------------------------------------------ + */ + mrs x0, midr_el1 + mov x1, #(MIDR_PN_MASK << MIDR_PN_SHIFT) + and x0, x0, x1 + lsr x0, x0, #MIDR_PN_SHIFT + cmp x0, #MIDR_PN_CORTEX_A57 + b.ne 1f + /* --------------------------- * Enable processor retention * --------------------------- @@ -68,18 +96,14 @@ orr x0, x0, x1 msr L2ECTLR_EL1, x0 isb -#endif -#if ENABLE_CPU_DYNAMIC_RETENTION mrs x0, CPUECTLR_EL1 mov x1, #RETENTION_ENTRY_TICKS_512 << CPUECTLR_CPU_RET_CTRL_SHIFT bic x0, x0, #CPUECTLR_CPU_RET_CTRL_MASK orr x0, x0, x1 msr CPUECTLR_EL1, x0 isb -#endif -#if ENABLE_NS_L2_CPUECTRL_RW_ACCESS /* ------------------------------------------------------- * Enable L2 and CPU ECTLR RW access from non-secure world * ------------------------------------------------------- @@ -88,13 +112,12 @@ msr actlr_el3, x0 msr actlr_el2, x0 isb -#endif /* -------------------------------- * Enable the cycle count register * -------------------------------- */ - mrs x0, pmcr_el0 +1: mrs x0, pmcr_el0 ubfx x0, x0, #11, #5 // read PMCR.N field mov x1, #1 lsl x0, x1, x0 @@ -157,6 +180,20 @@ func plat_get_my_entrypoint ret endfunc plat_get_my_entrypoint + /* ----------------------------------------------------- + * int platform_get_core_pos(int mpidr); + * + * With this function: CorePos = (ClusterId * 4) + + * CoreId + * ----------------------------------------------------- + */ +func platform_get_core_pos + and x1, x0, #MPIDR_CPU_MASK + and x0, x0, #MPIDR_CLUSTER_MASK + add x0, x1, x0, LSR #6 + ret +endfunc platform_get_core_pos + /* ----------------------------------------------------- * void plat_secondary_cold_boot_setup (void); * @@ -190,7 +227,8 @@ endfunc platform_mem_init * --------------------------------------------- */ func plat_crash_console_init - mov_imm x0, TEGRA_BOOT_UART_BASE + adr x0, tegra_console_base + ldr x0, [x0] mov_imm x1, TEGRA_BOOT_UART_CLK_IN_HZ mov_imm x2, TEGRA_CONSOLE_BAUDRATE b console_core_init @@ -204,7 +242,8 @@ endfunc plat_crash_console_init * --------------------------------------------- */ func plat_crash_console_putc - mov_imm x1, TEGRA_BOOT_UART_BASE + adr x1, tegra_console_base + ldr x1, [x1] b console_core_putc endfunc plat_crash_console_putc @@ -366,3 +405,10 @@ ns_image_entrypoint: */ tegra_bl31_phys_base: .quad 0 + + /* -------------------------------------------------- + * UART controller base for console init + * -------------------------------------------------- + */ +tegra_console_base: + .quad 0 diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c similarity index 99% rename from plat/nvidia/tegra/common/drivers/memctrl/memctrl.c rename to plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c index 4f7c71e4a..ac7d1415a 100644 --- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl.c +++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c @@ -31,8 +31,9 @@ #include #include #include -#include #include +#include +#include #include #include #include @@ -54,7 +55,7 @@ void tegra_memctrl_setup(void) * Setup the Memory controller to allow only secure accesses to * the TZDRAM carveout */ - INFO("Configuring SMMU\n"); + INFO("Tegra Memory Controller (v1)\n"); /* allow translations for all MC engines */ tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_0_0, diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c index 0fd7c8216..3a9514bda 100644 --- a/plat/nvidia/tegra/common/tegra_bl31_setup.c +++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c @@ -37,6 +37,7 @@ #include #include #include +#include #include #include #include @@ -54,6 +55,7 @@ extern unsigned long __RO_END__; extern unsigned long __BL31_END__; extern uint64_t tegra_bl31_phys_base; +extern uint64_t tegra_console_base; /* * The next 3 constants identify the extents of the code, RO data region and the @@ -110,28 +112,47 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2, { plat_params_from_bl2_t *plat_params = (plat_params_from_bl2_t *)plat_params_from_bl2; - - /* - * Configure the UART port to be used as the console - */ - console_init(TEGRA_BOOT_UART_BASE, TEGRA_BOOT_UART_CLK_IN_HZ, - TEGRA_CONSOLE_BAUDRATE); - - /* Initialise crash console */ - plat_crash_console_init(); +#if DEBUG + int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; +#endif /* * Copy BL3-3, BL3-2 entry point information. * They are stored in Secure RAM, in BL2's address space. */ + assert(from_bl2->bl33_ep_info); bl33_image_ep_info = *from_bl2->bl33_ep_info; - bl32_image_ep_info = *from_bl2->bl32_ep_info; + + if (from_bl2->bl32_ep_info) + bl32_image_ep_info = *from_bl2->bl32_ep_info; /* - * Parse platform specific parameters - TZDRAM aperture size + * Parse platform specific parameters - TZDRAM aperture base and size */ - if (plat_params) - plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size; + assert(plat_params); + plat_bl31_params_from_bl2.tzdram_base = plat_params->tzdram_base; + plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size; + plat_bl31_params_from_bl2.uart_id = plat_params->uart_id; + + /* + * Get the base address of the UART controller to be used for the + * console + */ + assert(plat_params->uart_id); + tegra_console_base = plat_get_console_from_id(plat_params->uart_id); + + /* + * Configure the UART port to be used as the console + */ + assert(tegra_console_base); + console_init(tegra_console_base, TEGRA_BOOT_UART_CLK_IN_HZ, + TEGRA_CONSOLE_BAUDRATE); + + /* Initialise crash console */ + plat_crash_console_init(); + + INFO("BL3-1: Boot CPU: %s Processor [%lx]\n", (impl == DENVER_IMPL) ? + "Denver" : "ARM", read_mpidr()); } /******************************************************************************* @@ -159,7 +180,7 @@ void bl31_platform_setup(void) /* * Do initial security configuration to allow DRAM/device access. */ - tegra_memctrl_tzdram_setup(tegra_bl31_phys_base, + tegra_memctrl_tzdram_setup(plat_bl31_params_from_bl2.tzdram_base, plat_bl31_params_from_bl2.tzdram_size); /* Set the next EL to be AArch64 */ @@ -168,6 +189,8 @@ void bl31_platform_setup(void) /* Initialize the gic cpu and distributor interfaces */ tegra_gic_setup(); + + INFO("BL3-1: Tegra platform setup complete\n"); } /******************************************************************************* @@ -215,6 +238,8 @@ void bl31_plat_arch_setup(void) /* enable the MMU */ enable_mmu_el3(0); + + INFO("BL3-1: Tegra: MMU enabled\n"); } /******************************************************************************* diff --git a/plat/nvidia/tegra/common/tegra_common.mk b/plat/nvidia/tegra/common/tegra_common.mk index 3c07032d3..82da7fd04 100644 --- a/plat/nvidia/tegra/common/tegra_common.mk +++ b/plat/nvidia/tegra/common/tegra_common.mk @@ -54,12 +54,9 @@ BL31_SOURCES += drivers/arm/gic/gic_v2.c \ plat/common/aarch64/platform_mp_stack.S \ plat/common/plat_psci_common.c \ ${COMMON_DIR}/aarch64/tegra_helpers.S \ - ${COMMON_DIR}/drivers/memctrl/memctrl.c \ ${COMMON_DIR}/drivers/pmc/pmc.c \ - ${COMMON_DIR}/drivers/flowctrl/flowctrl.c \ ${COMMON_DIR}/tegra_bl31_setup.c \ ${COMMON_DIR}/tegra_delay_timer.c \ ${COMMON_DIR}/tegra_gic.c \ ${COMMON_DIR}/tegra_pm.c \ - ${COMMON_DIR}/tegra_sip_calls.c \ ${COMMON_DIR}/tegra_topology.c diff --git a/plat/nvidia/tegra/common/tegra_pm.c b/plat/nvidia/tegra/common/tegra_pm.c index 6fb3e9c61..8b7a05903 100644 --- a/plat/nvidia/tegra/common/tegra_pm.c +++ b/plat/nvidia/tegra/common/tegra_pm.c @@ -174,7 +174,7 @@ void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state) * Security configuration to allow DRAM/device access. */ plat_params = bl31_get_plat_params(); - tegra_memctrl_tzdram_setup(tegra_bl31_phys_base, + tegra_memctrl_tzdram_setup(plat_params->tzdram_base, plat_params->tzdram_size); } diff --git a/plat/nvidia/tegra/include/drivers/memctrl.h b/plat/nvidia/tegra/include/drivers/memctrl.h index 26c805768..b06b4de78 100644 --- a/plat/nvidia/tegra/include/drivers/memctrl.h +++ b/plat/nvidia/tegra/include/drivers/memctrl.h @@ -31,53 +31,6 @@ #ifndef __MEMCTRL_H__ #define __MEMCTRL_H__ -#include -#include - -/* SMMU registers */ -#define MC_SMMU_CONFIG_0 0x10 -#define MC_SMMU_CONFIG_0_SMMU_ENABLE_DISABLE 0 -#define MC_SMMU_CONFIG_0_SMMU_ENABLE_ENABLE 1 -#define MC_SMMU_TLB_CONFIG_0 0x14 -#define MC_SMMU_TLB_CONFIG_0_RESET_VAL 0x20000010 -#define MC_SMMU_PTC_CONFIG_0 0x18 -#define MC_SMMU_PTC_CONFIG_0_RESET_VAL 0x2000003f -#define MC_SMMU_TLB_FLUSH_0 0x30 -#define TLB_FLUSH_VA_MATCH_ALL 0 -#define TLB_FLUSH_ASID_MATCH_DISABLE 0 -#define TLB_FLUSH_ASID_MATCH_SHIFT 31 -#define MC_SMMU_TLB_FLUSH_ALL \ - (TLB_FLUSH_VA_MATCH_ALL | \ - (TLB_FLUSH_ASID_MATCH_DISABLE << TLB_FLUSH_ASID_MATCH_SHIFT)) -#define MC_SMMU_PTC_FLUSH_0 0x34 -#define MC_SMMU_PTC_FLUSH_ALL 0 -#define MC_SMMU_ASID_SECURITY_0 0x38 -#define MC_SMMU_ASID_SECURITY 0 -#define MC_SMMU_TRANSLATION_ENABLE_0_0 0x228 -#define MC_SMMU_TRANSLATION_ENABLE_1_0 0x22c -#define MC_SMMU_TRANSLATION_ENABLE_2_0 0x230 -#define MC_SMMU_TRANSLATION_ENABLE_3_0 0x234 -#define MC_SMMU_TRANSLATION_ENABLE_4_0 0xb98 -#define MC_SMMU_TRANSLATION_ENABLE (~0) - -/* TZDRAM carveout configuration registers */ -#define MC_SECURITY_CFG0_0 0x70 -#define MC_SECURITY_CFG1_0 0x74 - -/* Video Memory carveout configuration registers */ -#define MC_VIDEO_PROTECT_BASE 0x648 -#define MC_VIDEO_PROTECT_SIZE_MB 0x64c - -static inline uint32_t tegra_mc_read_32(uint32_t off) -{ - return mmio_read_32(TEGRA_MC_BASE + off); -} - -static inline void tegra_mc_write_32(uint32_t off, uint32_t val) -{ - mmio_write_32(TEGRA_MC_BASE + off, val); -} - void tegra_memctrl_setup(void); void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes); void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes); diff --git a/plat/nvidia/tegra/include/drivers/memctrl_v1.h b/plat/nvidia/tegra/include/drivers/memctrl_v1.h new file mode 100644 index 000000000..e2e05277b --- /dev/null +++ b/plat/nvidia/tegra/include/drivers/memctrl_v1.h @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __MEMCTRLV1_H__ +#define __MEMCTRLV1_H__ + +#include +#include + +/* SMMU registers */ +#define MC_SMMU_CONFIG_0 0x10 +#define MC_SMMU_CONFIG_0_SMMU_ENABLE_DISABLE 0 +#define MC_SMMU_CONFIG_0_SMMU_ENABLE_ENABLE 1 +#define MC_SMMU_TLB_CONFIG_0 0x14 +#define MC_SMMU_TLB_CONFIG_0_RESET_VAL 0x20000010 +#define MC_SMMU_PTC_CONFIG_0 0x18 +#define MC_SMMU_PTC_CONFIG_0_RESET_VAL 0x2000003f +#define MC_SMMU_TLB_FLUSH_0 0x30 +#define TLB_FLUSH_VA_MATCH_ALL 0 +#define TLB_FLUSH_ASID_MATCH_DISABLE 0 +#define TLB_FLUSH_ASID_MATCH_SHIFT 31 +#define MC_SMMU_TLB_FLUSH_ALL \ + (TLB_FLUSH_VA_MATCH_ALL | \ + (TLB_FLUSH_ASID_MATCH_DISABLE << TLB_FLUSH_ASID_MATCH_SHIFT)) +#define MC_SMMU_PTC_FLUSH_0 0x34 +#define MC_SMMU_PTC_FLUSH_ALL 0 +#define MC_SMMU_ASID_SECURITY_0 0x38 +#define MC_SMMU_ASID_SECURITY 0 +#define MC_SMMU_TRANSLATION_ENABLE_0_0 0x228 +#define MC_SMMU_TRANSLATION_ENABLE_1_0 0x22c +#define MC_SMMU_TRANSLATION_ENABLE_2_0 0x230 +#define MC_SMMU_TRANSLATION_ENABLE_3_0 0x234 +#define MC_SMMU_TRANSLATION_ENABLE_4_0 0xb98 +#define MC_SMMU_TRANSLATION_ENABLE (~0) + +/* TZDRAM carveout configuration registers */ +#define MC_SECURITY_CFG0_0 0x70 +#define MC_SECURITY_CFG1_0 0x74 + +/* Video Memory carveout configuration registers */ +#define MC_VIDEO_PROTECT_BASE 0x648 +#define MC_VIDEO_PROTECT_SIZE_MB 0x64c + +static inline uint32_t tegra_mc_read_32(uint32_t off) +{ + return mmio_read_32(TEGRA_MC_BASE + off); +} + +static inline void tegra_mc_write_32(uint32_t off, uint32_t val) +{ + mmio_write_32(TEGRA_MC_BASE + off, val); +} + +#endif /* __MEMCTRLV1_H__ */ diff --git a/plat/nvidia/tegra/include/platform_def.h b/plat/nvidia/tegra/include/platform_def.h index cd06d93f5..92c4c554b 100644 --- a/plat/nvidia/tegra/include/platform_def.h +++ b/plat/nvidia/tegra/include/platform_def.h @@ -84,8 +84,6 @@ * Platform specific page table and MMU setup constants ******************************************************************************/ #define ADDR_SPACE_SIZE (1ull << 32) -#define MAX_XLAT_TABLES 3 -#define MAX_MMAP_REGIONS 8 /******************************************************************************* * Some data must be aligned on the biggest cache line size in the platform. diff --git a/plat/nvidia/tegra/include/t132/tegra_def.h b/plat/nvidia/tegra/include/t132/tegra_def.h index 683c90381..09d9b7429 100644 --- a/plat/nvidia/tegra/include/t132/tegra_def.h +++ b/plat/nvidia/tegra/include/t132/tegra_def.h @@ -70,6 +70,15 @@ ******************************************************************************/ #define TEGRA_EVP_BASE 0x6000F000 +/******************************************************************************* + * Tegra UART controller base addresses + ******************************************************************************/ +#define TEGRA_UARTA_BASE 0x70006000 +#define TEGRA_UARTB_BASE 0x70006040 +#define TEGRA_UARTC_BASE 0x70006200 +#define TEGRA_UARTD_BASE 0x70006300 +#define TEGRA_UARTE_BASE 0x70006400 + /******************************************************************************* * Tegra Power Mgmt Controller constants ******************************************************************************/ diff --git a/plat/nvidia/tegra/include/t210/tegra_def.h b/plat/nvidia/tegra/include/t210/tegra_def.h index 750e6e3f2..8be39bb32 100644 --- a/plat/nvidia/tegra/include/t210/tegra_def.h +++ b/plat/nvidia/tegra/include/t210/tegra_def.h @@ -47,20 +47,6 @@ ******************************************************************************/ #define PLAT_SYS_SUSPEND_STATE_ID PSTATE_ID_SOC_POWERDN -/******************************************************************************* - * Implementation defined ACTLR_EL3 bit definitions - ******************************************************************************/ -#define ACTLR_EL3_L2ACTLR_BIT (1 << 6) -#define ACTLR_EL3_L2ECTLR_BIT (1 << 5) -#define ACTLR_EL3_L2CTLR_BIT (1 << 4) -#define ACTLR_EL3_CPUECTLR_BIT (1 << 1) -#define ACTLR_EL3_CPUACTLR_BIT (1 << 0) -#define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \ - ACTLR_EL3_L2ECTLR_BIT | \ - ACTLR_EL3_L2CTLR_BIT | \ - ACTLR_EL3_CPUECTLR_BIT | \ - ACTLR_EL3_CPUACTLR_BIT) - /******************************************************************************* * GIC memory map ******************************************************************************/ @@ -109,6 +95,15 @@ ******************************************************************************/ #define TEGRA_EVP_BASE 0x6000F000 +/******************************************************************************* + * Tegra UART controller base addresses + ******************************************************************************/ +#define TEGRA_UARTA_BASE 0x70006000 +#define TEGRA_UARTB_BASE 0x70006040 +#define TEGRA_UARTC_BASE 0x70006200 +#define TEGRA_UARTD_BASE 0x70006300 +#define TEGRA_UARTE_BASE 0x70006400 + /******************************************************************************* * Tegra Power Mgmt Controller constants ******************************************************************************/ diff --git a/plat/nvidia/tegra/include/tegra_private.h b/plat/nvidia/tegra/include/tegra_private.h index cf75d9f53..75416ec3c 100644 --- a/plat/nvidia/tegra/include/tegra_private.h +++ b/plat/nvidia/tegra/include/tegra_private.h @@ -43,7 +43,12 @@ #define TEGRA_DRAM_END 0x27FFFFFFF typedef struct plat_params_from_bl2 { + /* TZ memory size */ uint64_t tzdram_size; + /* TZ memory base */ + uint64_t tzdram_base; + /* UART port ID */ + int uart_id; } plat_params_from_bl2_t; /* Declarations for plat_psci_handlers.c */ @@ -52,6 +57,7 @@ int32_t tegra_soc_validate_power_state(unsigned int power_state, /* Declarations for plat_setup.c */ const mmap_region_t *plat_get_mmio_map(void); +uint32_t plat_get_console_from_id(int id); /* Declarations for plat_secondary.c */ void plat_secondary_setup(void); diff --git a/plat/nvidia/tegra/soc/t132/plat_setup.c b/plat/nvidia/tegra/soc/t132/plat_setup.c index 0d6641375..337a2c59f 100644 --- a/plat/nvidia/tegra/soc/t132/plat_setup.c +++ b/plat/nvidia/tegra/soc/t132/plat_setup.c @@ -78,3 +78,31 @@ unsigned int plat_get_syscnt_freq2(void) { return 12000000; } + +/******************************************************************************* + * Maximum supported UART controllers + ******************************************************************************/ +#define TEGRA132_MAX_UART_PORTS 5 + +/******************************************************************************* + * This variable holds the UART port base addresses + ******************************************************************************/ +static uint32_t tegra132_uart_addresses[TEGRA132_MAX_UART_PORTS + 1] = { + 0, /* undefined - treated as an error case */ + TEGRA_UARTA_BASE, + TEGRA_UARTB_BASE, + TEGRA_UARTC_BASE, + TEGRA_UARTD_BASE, + TEGRA_UARTE_BASE, +}; + +/******************************************************************************* + * Retrieve the UART controller base to be used as the console + ******************************************************************************/ +uint32_t plat_get_console_from_id(int id) +{ + if (id > TEGRA132_MAX_UART_PORTS) + return 0; + + return tegra132_uart_addresses[id]; +} diff --git a/plat/nvidia/tegra/common/tegra_sip_calls.c b/plat/nvidia/tegra/soc/t132/plat_sip_calls.c similarity index 97% rename from plat/nvidia/tegra/common/tegra_sip_calls.c rename to plat/nvidia/tegra/soc/t132/plat_sip_calls.c index de36a3c6b..450e1dd3b 100644 --- a/plat/nvidia/tegra/common/tegra_sip_calls.c +++ b/plat/nvidia/tegra/soc/t132/plat_sip_calls.c @@ -43,7 +43,7 @@ #define SCR_RW_BITPOS __builtin_ctz(SCR_RW_BIT) /******************************************************************************* - * Tegra SiP SMCs + * Tegra132 SiP SMCs ******************************************************************************/ #define TEGRA_SIP_NEW_VIDEOMEM_REGION 0x82000003 #define TEGRA_SIP_AARCH_SWITCH 0x82000004 @@ -58,7 +58,7 @@ /******************************************************************************* * This function is responsible for handling all SiP calls from the NS world ******************************************************************************/ -uint64_t tegra_sip_handler(uint32_t smc_fid, +uint64_t tegra132_sip_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, @@ -138,11 +138,11 @@ uint64_t tegra_sip_handler(uint32_t smc_fid, /* Define a runtime service descriptor for fast SMC calls */ DECLARE_RT_SVC( - tegra_sip_fast, + tegra132_sip_fast, OEN_SIP_START, OEN_SIP_END, SMC_TYPE_FAST, NULL, - tegra_sip_handler + tegra132_sip_handler ); diff --git a/plat/nvidia/tegra/soc/t132/platform_t132.mk b/plat/nvidia/tegra/soc/t132/platform_t132.mk index 69d62964f..6b9fce3b4 100644 --- a/plat/nvidia/tegra/soc/t132/platform_t132.mk +++ b/plat/nvidia/tegra/soc/t132/platform_t132.mk @@ -28,9 +28,6 @@ # POSSIBILITY OF SUCH DAMAGE. # -TEGRA_BOOT_UART_BASE := 0x70006300 -$(eval $(call add_define,TEGRA_BOOT_UART_BASE)) - TZDRAM_BASE := 0xF5C00000 $(eval $(call add_define,TZDRAM_BASE)) @@ -40,7 +37,16 @@ $(eval $(call add_define,PLATFORM_CLUSTER_COUNT)) PLATFORM_MAX_CPUS_PER_CLUSTER := 2 $(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER)) +MAX_XLAT_TABLES := 3 +$(eval $(call add_define,MAX_XLAT_TABLES)) + +MAX_MMAP_REGIONS := 8 +$(eval $(call add_define,MAX_MMAP_REGIONS)) + BL31_SOURCES += lib/cpus/aarch64/denver.S \ + ${COMMON_DIR}/drivers/flowctrl/flowctrl.c \ + ${COMMON_DIR}/drivers/memctrl/memctrl_v1.c \ ${SOC_DIR}/plat_psci_handlers.c \ + ${SOC_DIR}/plat_sip_calls.c \ ${SOC_DIR}/plat_setup.c \ ${SOC_DIR}/plat_secondary.c diff --git a/plat/nvidia/tegra/soc/t210/plat_setup.c b/plat/nvidia/tegra/soc/t210/plat_setup.c index 70a55c696..246faf874 100644 --- a/plat/nvidia/tegra/soc/t210/plat_setup.c +++ b/plat/nvidia/tegra/soc/t210/plat_setup.c @@ -84,3 +84,31 @@ unsigned int plat_get_syscnt_freq2(void) { return 19200000; } + +/******************************************************************************* + * Maximum supported UART controllers + ******************************************************************************/ +#define TEGRA210_MAX_UART_PORTS 5 + +/******************************************************************************* + * This variable holds the UART port base addresses + ******************************************************************************/ +static uint32_t tegra210_uart_addresses[TEGRA210_MAX_UART_PORTS + 1] = { + 0, /* undefined - treated as an error case */ + TEGRA_UARTA_BASE, + TEGRA_UARTB_BASE, + TEGRA_UARTC_BASE, + TEGRA_UARTD_BASE, + TEGRA_UARTE_BASE, +}; + +/******************************************************************************* + * Retrieve the UART controller base to be used as the console + ******************************************************************************/ +uint32_t plat_get_console_from_id(int id) +{ + if (id > TEGRA210_MAX_UART_PORTS) + return 0; + + return tegra210_uart_addresses[id]; +} diff --git a/plat/nvidia/tegra/soc/t210/plat_sip_calls.c b/plat/nvidia/tegra/soc/t210/plat_sip_calls.c new file mode 100644 index 000000000..7d9838a35 --- /dev/null +++ b/plat/nvidia/tegra/soc/t210/plat_sip_calls.c @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/******************************************************************************* + * Tegra210 SiP SMCs + ******************************************************************************/ +#define TEGRA_SIP_NEW_VIDEOMEM_REGION 0x82000003 + +/******************************************************************************* + * This function is responsible for handling all SiP calls from the NS world + ******************************************************************************/ +uint64_t tegra210_sip_handler(uint32_t smc_fid, + uint64_t x1, + uint64_t x2, + uint64_t x3, + uint64_t x4, + void *cookie, + void *handle, + uint64_t flags) +{ + uint32_t ns; + int err; + + /* Determine which security state this SMC originated from */ + ns = is_caller_non_secure(flags); + if (!ns) + SMC_RET1(handle, SMC_UNK); + + switch (smc_fid) { + + case TEGRA_SIP_NEW_VIDEOMEM_REGION: + + /* clean up the high bits */ + x1 = (uint32_t)x1; + x2 = (uint32_t)x2; + + /* + * Check if Video Memory overlaps TZDRAM (contains bl31/bl32) + * or falls outside of the valid DRAM range + */ + err = bl31_check_ns_address(x1, x2); + if (err) + SMC_RET1(handle, err); + + /* + * Check if Video Memory is aligned to 1MB. + */ + if ((x1 & 0xFFFFF) || (x2 & 0xFFFFF)) { + ERROR("Unaligned Video Memory base address!\n"); + SMC_RET1(handle, -ENOTSUP); + } + + /* new video memory carveout settings */ + tegra_memctrl_videomem_setup(x1, x2); + + SMC_RET1(handle, 0); + break; + + default: + ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); + break; + } + + SMC_RET1(handle, SMC_UNK); +} + +/* Define a runtime service descriptor for fast SMC calls */ +DECLARE_RT_SVC( + tegra210_sip_fast, + + OEN_SIP_START, + OEN_SIP_END, + SMC_TYPE_FAST, + NULL, + tegra210_sip_handler +); diff --git a/plat/nvidia/tegra/soc/t210/platform_t210.mk b/plat/nvidia/tegra/soc/t210/platform_t210.mk index 5001629d4..d83c54db0 100644 --- a/plat/nvidia/tegra/soc/t210/platform_t210.mk +++ b/plat/nvidia/tegra/soc/t210/platform_t210.mk @@ -28,33 +28,30 @@ # POSSIBILITY OF SUCH DAMAGE. # -TEGRA_BOOT_UART_BASE := 0x70006000 -$(eval $(call add_define,TEGRA_BOOT_UART_BASE)) - TZDRAM_BASE := 0xFDC00000 $(eval $(call add_define,TZDRAM_BASE)) ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT := 1 $(eval $(call add_define,ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT)) -ENABLE_NS_L2_CPUECTRL_RW_ACCESS := 1 -$(eval $(call add_define,ENABLE_NS_L2_CPUECTRL_RW_ACCESS)) - -ENABLE_L2_DYNAMIC_RETENTION := 1 -$(eval $(call add_define,ENABLE_L2_DYNAMIC_RETENTION)) - -ENABLE_CPU_DYNAMIC_RETENTION := 1 -$(eval $(call add_define,ENABLE_CPU_DYNAMIC_RETENTION)) - PLATFORM_CLUSTER_COUNT := 2 $(eval $(call add_define,PLATFORM_CLUSTER_COUNT)) PLATFORM_MAX_CPUS_PER_CLUSTER := 4 $(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER)) +MAX_XLAT_TABLES := 3 +$(eval $(call add_define,MAX_XLAT_TABLES)) + +MAX_MMAP_REGIONS := 8 +$(eval $(call add_define,MAX_MMAP_REGIONS)) + BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ lib/cpus/aarch64/cortex_a57.S \ + ${COMMON_DIR}/drivers/flowctrl/flowctrl.c \ + ${COMMON_DIR}/drivers/memctrl/memctrl_v1.c \ ${SOC_DIR}/plat_psci_handlers.c \ + ${SOC_DIR}/plat_sip_calls.c \ ${SOC_DIR}/plat_setup.c \ ${SOC_DIR}/plat_secondary.c