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rpi4: Cleanup memory regions, move pens to first page 

Now that we have the SMP pens in the first page of DRAM, we can get rid
of all the fancy RPi3 memory regions that our RPi4 port does not really
need. This avoids using up memory all over the place, restricting ATF
to just run in the first 512KB of DRAM.

Remove the now unused regions. This also moves the SMP pens into our
first memory page (holding the firmware magic), where the original
firmware put them, but where there is also enough space for them.

Since the pens will require code execution privileges, we amend the
memory attributes used for that page to include write and execution
rights.

Change-Id: I131633abeb4a4d7b9057e737b9b0d163b73e47c6
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This commit is contained in:
Andre Przywara 2019-07-15 09:04:27 +01:00
parent 2b19e2f361
commit 882c0ff6ba
2 changed files with 6 additions and 67 deletions
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68
plat/rpi/rpi4/include/platform_def.h
View File

@ -58,70 +58,12 @@
#define CACHE_WRITEBACK_SHIFT U(6)
#define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT)
/*
* Partition memory into secure ROM, non-secure DRAM, secure "SRAM", and
* secure DRAM. Note that this is all actually DRAM with different names,
* there is no Secure RAM in the Raspberry Pi 4.
*/
#if RPI3_USE_UEFI_MAP
#define SEC_ROM_BASE ULL(0x00000000)
#define SEC_ROM_SIZE ULL(0x00010000)
/* FIP placed after ROM to append it to BL1 with very little padding. */
#define PLAT_RPI3_FIP_BASE ULL(0x00020000)
#define PLAT_RPI3_FIP_MAX_SIZE ULL(0x00010000)
/* Reserve 2M of secure SRAM and DRAM, starting at 2M */
#define SEC_SRAM_BASE ULL(0x00200000)
#define SEC_SRAM_SIZE ULL(0x00100000)
#define SEC_DRAM0_BASE ULL(0x00300000)
#define SEC_DRAM0_SIZE ULL(0x00100000)
/* Windows on ARM requires some RAM at 4M */
#define NS_DRAM0_BASE ULL(0x00400000)
#define NS_DRAM0_SIZE ULL(0x00C00000)
#else
#define SEC_ROM_BASE ULL(0x00000000)
#define SEC_ROM_SIZE ULL(0x00020000)
/* FIP placed after ROM to append it to BL1 with very little padding. */
#define PLAT_RPI3_FIP_BASE ULL(0x00020000)
#define PLAT_RPI3_FIP_MAX_SIZE ULL(0x001E0000)
/* We have 16M of memory reserved starting at 256M */
#define SEC_SRAM_BASE ULL(0x10000000)
#define SEC_SRAM_SIZE ULL(0x00100000)
#define SEC_DRAM0_BASE ULL(0x10100000)
#define SEC_DRAM0_SIZE ULL(0x00F00000)
/* End of reserved memory */
#define NS_DRAM0_BASE ULL(0x11000000)
#define NS_DRAM0_SIZE ULL(0x01000000)
#endif /* RPI3_USE_UEFI_MAP */
/*
* BL33 entrypoint.
*/
#define PLAT_RPI3_NS_IMAGE_OFFSET NS_DRAM0_BASE
#define PLAT_RPI3_NS_IMAGE_MAX_SIZE NS_DRAM0_SIZE
/*
* I/O registers.
*/
#define DEVICE0_BASE RPI_IO_BASE
#define DEVICE0_SIZE RPI_IO_SIZE
/*
* TF-A lives in SRAM, partition it here
*/
#define SHARED_RAM_BASE SEC_SRAM_BASE
#define SHARED_RAM_SIZE ULL(0x00001000)
#define BL_RAM_BASE (SHARED_RAM_BASE + SHARED_RAM_SIZE)
#define BL_RAM_SIZE (SEC_SRAM_SIZE - SHARED_RAM_SIZE)
/*
* Mailbox to control the secondary cores. All secondary cores are held in a
* wait loop in cold boot. To release them perform the following steps (plus
@ -135,10 +77,8 @@
*
* sev();
*/
#define PLAT_RPI3_TRUSTED_MAILBOX_BASE SHARED_RAM_BASE
/* The secure entry point to be used on warm reset by all CPUs. */
#define PLAT_RPI3_TM_ENTRYPOINT PLAT_RPI3_TRUSTED_MAILBOX_BASE
#define PLAT_RPI3_TM_ENTRYPOINT 0x100
#define PLAT_RPI3_TM_ENTRYPOINT_SIZE ULL(8)
/* Hold entries for each CPU. */
@ -160,11 +100,11 @@
* Put BL31 at the top of the Trusted SRAM. BL31_BASE is calculated using the
* current BL31 debug size plus a little space for growth.
*/
#define PLAT_MAX_BL31_SIZE ULL(0x20000)
#define PLAT_MAX_BL31_SIZE ULL(0x80000)
#define BL31_BASE ULL(0x1000)
#define BL31_LIMIT ULL(0x100000)
#define BL31_PROGBITS_LIMIT ULL(0x100000)
#define BL31_LIMIT ULL(0x80000)
#define BL31_PROGBITS_LIMIT ULL(0x80000)
#define SEC_SRAM_ID 0
#define SEC_DRAM_ID 1

5
plat/rpi/rpi4/rpi4_bl31_setup.c
View File

@ -197,10 +197,9 @@ void bl31_plat_arch_setup(void)
/*
* Add the first page of memory, which holds the stub magic,
* the kernel and the DT address.
* This is read-only, as the GPU already populated the header,
* we just need to read it.
* This also holds the secondary CPU's entrypoints and mailboxes.
*/
mmap_add_region(0, 0, 4096, MT_MEMORY | MT_RO | MT_SECURE);
mmap_add_region(0, 0, 4096, MT_NON_CACHEABLE | MT_RW | MT_SECURE);
rpi3_setup_page_tables(BL31_BASE, BL31_END - BL31_BASE,
BL_CODE_BASE, BL_CODE_END,