Merge "A5DS: Correct system freq, Cache Writeback Granule" into integration
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commit
8849298cb3
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2019, Arm Limited. All rights reserved.
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* Copyright (c) 2019-2020, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -64,10 +64,17 @@
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arm,tag-latency = <1 1 1>;
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};
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refclk100mhz: refclk100mhz {
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refclk7500khz: refclk7500khz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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clock-frequency = <7500000>;
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clock-output-names = "apb_pclk";
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};
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refclk24mhz: refclk24mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "apb_pclk";
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};
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@ -82,7 +89,7 @@
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rtc@1a220000 {
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compatible = "arm,pl031", "arm,primecell";
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reg = <0x1a220000 0x1000>;
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clocks = <&refclk100mhz>;
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clocks = <&refclk24mhz>;
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interrupts = <0 6 0xf04>;
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clock-names = "apb_pclk";
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};
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@ -102,7 +109,7 @@
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reg = <0x1a200000 0x1000>;
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interrupt-parent = <&gic>;
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interrupts = <0 8 0xf04>;
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clocks = <&refclk100mhz>;
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clocks = <&refclk7500khz>;
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clock-names = "apb_pclk";
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};
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@ -111,7 +118,7 @@
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reg = <0x1a210000 0x1000>;
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interrupt-parent = <&gic>;
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interrupts = <0 9 0xf04>;
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clocks = <&refclk100mhz>;
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clocks = <&refclk7500khz>;
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clock-names = "apb_pclk";
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};
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2019, Arm Limited. All rights reserved.
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* Copyright (c) 2019-2020, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -47,7 +47,7 @@
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#define A5_PERIPHERALS_BASE 0x1c000000
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#define A5_PERIPHERALS_SIZE 0x10000
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#define ARM_CACHE_WRITEBACK_SHIFT 6
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#define ARM_CACHE_WRITEBACK_SHIFT 5
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#define ARM_IRQ_SEC_PHY_TIMER 29
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@ -162,7 +162,7 @@
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ARM_BL_REGIONS)
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/* Memory mapped Generic timer interfaces */
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#define A5DS_TIMER_BASE_FREQUENCY UL(24000000)
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#define A5DS_TIMER_BASE_FREQUENCY UL(7500000)
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#define ARM_CONSOLE_BAUDRATE 115200
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@ -310,15 +310,15 @@
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* PL011 related constants
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*/
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#define PLAT_ARM_BOOT_UART_BASE 0x1A200000
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#define PLAT_ARM_BOOT_UART_CLK_IN_HZ 24000000
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#define PLAT_ARM_BOOT_UART_CLK_IN_HZ UL(7500000)
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#define PLAT_ARM_RUN_UART_BASE 0x1A210000
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#define PLAT_ARM_RUN_UART_CLK_IN_HZ 24000000
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#define PLAT_ARM_RUN_UART_CLK_IN_HZ UL(7500000)
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#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE
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#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ
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#define A5DS_TIMER_BASE_FREQUENCY UL(24000000)
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#define A5DS_TIMER_BASE_FREQUENCY UL(7500000)
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/* System timer related constants */
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#define PLAT_ARM_NSTIMER_FRAME_ID 1
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