From 889c07c7b1a9739bcc907ad1f988fa484d22f84c Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Wed, 8 Nov 2017 14:45:08 -0800 Subject: [PATCH] Tegra186: helper functions for CPU rst handler and SMMU ctx offset This patch adds a helper function to get the SMMU context's offset and uses another helper function to get the CPU trampoline offset. These helper functions are used by the System Suspend entry sequence to save the SMMU context and CPU reset handler to TZDRAM. Change-Id: I95e2862fe37ccad00fa48ec165c6e4024df01147 Signed-off-by: Varun Wadekar --- plat/nvidia/tegra/include/t186/tegra186_private.h | 1 + plat/nvidia/tegra/soc/t186/plat_psci_handlers.c | 10 +++------- plat/nvidia/tegra/soc/t186/plat_trampoline.S | 11 +++++++++++ 3 files changed, 15 insertions(+), 7 deletions(-) diff --git a/plat/nvidia/tegra/include/t186/tegra186_private.h b/plat/nvidia/tegra/include/t186/tegra186_private.h index cb52f084e..30b1595e8 100644 --- a/plat/nvidia/tegra/include/t186/tegra186_private.h +++ b/plat/nvidia/tegra/include/t186/tegra186_private.h @@ -10,5 +10,6 @@ void tegra186_cpu_reset_handler(void); uint64_t tegra186_get_cpu_reset_handler_base(void); uint64_t tegra186_get_cpu_reset_handler_size(void); +uint64_t tegra186_get_smmu_ctx_offset(void); #endif /* TEGRA186_PRIVATE_H */ diff --git a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c index 5d3cdfaf5..162a2833a 100644 --- a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c @@ -22,12 +22,10 @@ #include #include #include +#include #include extern void memcpy16(void *dest, const void *src, unsigned int length); -extern void tegra186_cpu_reset_handler(void); -extern uint64_t __tegra186_cpu_reset_handler_end, - __tegra186_smmu_context; /* state id mask */ #define TEGRA186_STATE_ID_MASK 0xFU @@ -127,8 +125,7 @@ int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) /* save SMMU context to TZDRAM */ smmu_ctx_base = params_from_bl2->tzdram_base + - ((uintptr_t)&__tegra186_smmu_context - - (uintptr_t)&tegra186_cpu_reset_handler); + tegra186_get_smmu_ctx_offset(); tegra_smmu_save_context((uintptr_t)smmu_ctx_base); /* Prepare for system suspend */ @@ -279,8 +276,7 @@ int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_sta * BL3-1 over to TZDRAM. */ val = params_from_bl2->tzdram_base + - ((uintptr_t)&__tegra186_cpu_reset_handler_end - - (uintptr_t)&tegra186_cpu_reset_handler); + tegra186_get_cpu_reset_handler_size(); memcpy16((void *)(uintptr_t)val, (void *)(uintptr_t)BL31_BASE, (uintptr_t)&__BL31_END__ - (uintptr_t)BL31_BASE); } diff --git a/plat/nvidia/tegra/soc/t186/plat_trampoline.S b/plat/nvidia/tegra/soc/t186/plat_trampoline.S index 3ed2940ca..d609a144b 100644 --- a/plat/nvidia/tegra/soc/t186/plat_trampoline.S +++ b/plat/nvidia/tegra/soc/t186/plat_trampoline.S @@ -69,6 +69,8 @@ endfunc tegra186_cpu_reset_handler __tegra186_cpu_reset_handler_data: .quad tegra_secure_entrypoint .quad __BL31_END__ - BL31_BASE + + .align 4 .globl __tegra186_smmu_context __tegra186_smmu_context: .rept TEGRA186_SMMU_CTX_SIZE @@ -83,6 +85,7 @@ __tegra186_cpu_reset_handler_end: .globl tegra186_get_cpu_reset_handler_size .globl tegra186_get_cpu_reset_handler_base + .globl tegra186_get_smmu_ctx_offset /* return size of the CPU reset handler */ func tegra186_get_cpu_reset_handler_size @@ -97,3 +100,11 @@ func tegra186_get_cpu_reset_handler_base adr x0, tegra186_cpu_reset_handler ret endfunc tegra186_get_cpu_reset_handler_base + +/* return the size of the SMMU context */ +func tegra186_get_smmu_ctx_offset + adr x0, __tegra186_smmu_context + adr x1, tegra186_cpu_reset_handler + sub x0, x0, x1 + ret +endfunc tegra186_get_smmu_ctx_offset