feat(stm32mp1): allow configuration of DDR AXI ports number
A new flag STM32MP_DDR_DUAL_AXI_PORT is added, and enabled by default. It will allow choosing single or dual AXI ports for DDR. Change-Id: I48826a66a6f4d18df87e081c0960af89ddda1b9d Signed-off-by: Yann Gautier <yann.gautier@st.com>
This commit is contained in:
Yann Gautier
parent
ba7d2e2698
commit
88f4fb8fa7
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@ -54,9 +54,17 @@ struct reg_desc {
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#define DDRCTL_REG_REG_SIZE 25 /* st,ctl-reg */
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#define DDRCTL_REG_TIMING_SIZE 12 /* st,ctl-timing */
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#define DDRCTL_REG_MAP_SIZE 9 /* st,ctl-map */
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#if STM32MP_DDR_DUAL_AXI_PORT
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#define DDRCTL_REG_PERF_SIZE 17 /* st,ctl-perf */
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#else
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#define DDRCTL_REG_PERF_SIZE 11 /* st,ctl-perf */
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#endif
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#if STM32MP_DDR_32BIT_INTERFACE
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#define DDRPHY_REG_REG_SIZE 11 /* st,phy-reg */
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#else
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#define DDRPHY_REG_REG_SIZE 9 /* st,phy-reg */
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#endif
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#define DDRPHY_REG_TIMING_SIZE 10 /* st,phy-timing */
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#define DDRCTL_REG_REG(x) DDRCTL_REG(x, stm32mp1_ddrctrl_reg)
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@ -130,12 +138,14 @@ static const struct reg_desc ddr_perf[DDRCTL_REG_PERF_SIZE] = {
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DDRCTL_REG_PERF(pcfgqos1_0),
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DDRCTL_REG_PERF(pcfgwqos0_0),
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DDRCTL_REG_PERF(pcfgwqos1_0),
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#if STM32MP_DDR_DUAL_AXI_PORT
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DDRCTL_REG_PERF(pcfgr_1),
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DDRCTL_REG_PERF(pcfgw_1),
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DDRCTL_REG_PERF(pcfgqos0_1),
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DDRCTL_REG_PERF(pcfgqos1_1),
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DDRCTL_REG_PERF(pcfgwqos0_1),
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DDRCTL_REG_PERF(pcfgwqos1_1),
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#endif
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};
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#define DDRPHY_REG_REG(x) DDRPHY_REG(x, stm32mp1_ddrphy_reg)
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@ -149,8 +159,10 @@ static const struct reg_desc ddrphy_reg[DDRPHY_REG_REG_SIZE] = {
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DDRPHY_REG_REG(zq0cr1),
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DDRPHY_REG_REG(dx0gcr),
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DDRPHY_REG_REG(dx1gcr),
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#if STM32MP_DDR_32BIT_INTERFACE
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DDRPHY_REG_REG(dx2gcr),
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DDRPHY_REG_REG(dx3gcr),
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#endif
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};
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#define DDRPHY_REG_TIMING(x) DDRPHY_REG(x, stm32mp1_ddrphy_timing)
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@ -587,10 +599,12 @@ static void stm32mp1_ddr3_dll_off(struct ddr_info *priv)
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DDRPHYC_DXNDLLCR_DLLDIS);
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mmio_setbits_32((uintptr_t)&priv->phy->dx1dllcr,
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DDRPHYC_DXNDLLCR_DLLDIS);
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#if STM32MP_DDR_32BIT_INTERFACE
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mmio_setbits_32((uintptr_t)&priv->phy->dx2dllcr,
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DDRPHYC_DXNDLLCR_DLLDIS);
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mmio_setbits_32((uintptr_t)&priv->phy->dx3dllcr,
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DDRPHYC_DXNDLLCR_DLLDIS);
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#endif
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/* 12. Exit the self-refresh state by setting PWRCTL.selfref_sw = 0. */
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mmio_clrbits_32((uintptr_t)&priv->ctl->pwrctl,
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@ -861,10 +875,12 @@ void stm32mp1_ddr_init(struct ddr_info *priv,
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(uintptr_t)&priv->ctl->pctrl_0,
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mmio_read_32((uintptr_t)&priv->ctl->pctrl_0));
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#if STM32MP_DDR_DUAL_AXI_PORT
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/* Enable uMCTL2 AXI port 1 */
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mmio_setbits_32((uintptr_t)&priv->ctl->pctrl_1,
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DDRCTRL_PCTRL_N_PORT_EN);
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VERBOSE("[0x%lx] pctrl_1 = 0x%x\n",
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(uintptr_t)&priv->ctl->pctrl_1,
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mmio_read_32((uintptr_t)&priv->ctl->pctrl_1));
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#endif
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}
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@ -1,21 +1,23 @@
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/*
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* Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved
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* Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <platform_def.h>
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#include <drivers/st/stm32mp1_ddr_helpers.h>
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#include <lib/mmio.h>
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#include <platform_def.h>
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void ddr_enable_clock(void)
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{
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stm32mp1_clk_rcc_regs_lock();
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mmio_setbits_32(stm32mp_rcc_base() + RCC_DDRITFCR,
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RCC_DDRITFCR_DDRC1EN |
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#if STM32MP_DDR_DUAL_AXI_PORT
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RCC_DDRITFCR_DDRC2EN |
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#endif
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RCC_DDRITFCR_DDRPHYCEN |
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RCC_DDRITFCR_DDRPHYCAPBEN |
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RCC_DDRITFCR_DDRCAPBEN);
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@ -101,12 +101,14 @@ struct stm32mp1_ddrctrl_perf {
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uint32_t pcfgqos1_0;
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uint32_t pcfgwqos0_0;
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uint32_t pcfgwqos1_0;
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#if STM32MP_DDR_DUAL_AXI_PORT
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uint32_t pcfgr_1;
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uint32_t pcfgw_1;
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uint32_t pcfgqos0_1;
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uint32_t pcfgqos1_1;
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uint32_t pcfgwqos0_1;
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uint32_t pcfgwqos1_1;
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#endif
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};
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struct stm32mp1_ddrphy_reg {
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@ -119,8 +121,10 @@ struct stm32mp1_ddrphy_reg {
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uint32_t zq0cr1;
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uint32_t dx0gcr;
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uint32_t dx1gcr;
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#if STM32MP_DDR_32BIT_INTERFACE
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uint32_t dx2gcr;
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uint32_t dx3gcr;
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#endif
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};
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struct stm32mp1_ddrphy_timing {
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@ -128,6 +128,7 @@ struct stm32mp1_ddrctl {
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uint32_t pcfgwqos1_0; /* 0x4a0 Write QoS Configuration 1 */
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uint8_t reserved4a4[0x4b4 - 0x4a4];
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#if STM32MP_DDR_DUAL_AXI_PORT
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/* PORT 1 */
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uint32_t pcfgr_1; /* 0x4b4 Configuration Read */
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uint32_t pcfgw_1; /* 0x4b8 Configuration Write */
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@ -137,6 +138,7 @@ struct stm32mp1_ddrctl {
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uint32_t pcfgqos1_1; /* 0x548 Read QoS Configuration 1 */
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uint32_t pcfgwqos0_1; /* 0x54c Write QoS Configuration 0 */
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uint32_t pcfgwqos1_1; /* 0x550 Write QoS Configuration 1 */
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#endif
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} __packed;
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/* DDR Physical Interface Control (DDRPHYC) registers*/
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@ -214,6 +216,7 @@ struct stm32mp1_ddrphy {
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uint32_t dx1dqtr; /* 0x210 Byte lane 1 DQ Timing */
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uint32_t dx1dqstr; /* 0x214 Byte lane 1 QS Timing */
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uint8_t res6[0x240 - 0x218]; /* 0x218 */
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#if STM32MP_DDR_32BIT_INTERFACE
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uint32_t dx2gcr; /* 0x240 Byte lane 2 General Configuration */
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uint32_t dx2gsr0; /* 0x244 Byte lane 2 General Status 0 */
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uint32_t dx2gsr1; /* 0x248 Byte lane 2 General Status 1 */
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@ -227,6 +230,7 @@ struct stm32mp1_ddrphy {
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uint32_t dx3dllcr; /* 0x28c Byte lane 3 DLL Control */
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uint32_t dx3dqtr; /* 0x290 Byte lane 3 DQ Timing */
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uint32_t dx3dqstr; /* 0x294 Byte lane 3 QS Timing */
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#endif
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} __packed;
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/* DDR Controller registers offsets */
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@ -249,7 +253,9 @@ struct stm32mp1_ddrphy {
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#define DDRCTRL_SWSTAT 0x324
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#define DDRCTRL_PSTAT 0x3FC
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#define DDRCTRL_PCTRL_0 0x490
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#if STM32MP_DDR_DUAL_AXI_PORT
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#define DDRCTRL_PCTRL_1 0x540
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#endif
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/* DDR Controller Register fields */
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#define DDRCTRL_MSTR_DDR3 BIT(0)
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@ -339,10 +345,12 @@ struct stm32mp1_ddrphy {
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#define DDRPHYC_DX0DLLCR 0x1CC
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#define DDRPHYC_DX1GCR 0x200
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#define DDRPHYC_DX1DLLCR 0x20C
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#if STM32MP_DDR_32BIT_INTERFACE
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#define DDRPHYC_DX2GCR 0x240
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#define DDRPHYC_DX2DLLCR 0x24C
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#define DDRPHYC_DX3GCR 0x280
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#define DDRPHYC_DX3DLLCR 0x28C
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#endif
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/* DDR PHY Register fields */
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#define DDRPHYC_PIR_INIT BIT(0)
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@ -1,5 +1,5 @@
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#
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# Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
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# Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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@ -23,6 +23,10 @@ STM32_TF_VERSION ?= 0
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# Enable dynamic memory mapping
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PLAT_XLAT_TABLES_DYNAMIC := 1
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# DDR controller with dual AXI port and 32-bit interface
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STM32MP_DDR_DUAL_AXI_PORT:= 1
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STM32MP_DDR_32BIT_INTERFACE:= 1
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ifeq ($(AARCH32_SP),sp_min)
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# Disable Neon support: sp_min runtime may conflict with non-secure world
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TF_CFLAGS += -mfloat-abi=soft
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@ -127,6 +131,8 @@ endif
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$(eval $(call assert_booleans,\
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$(sort \
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PLAT_XLAT_TABLES_DYNAMIC \
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STM32MP_DDR_32BIT_INTERFACE \
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STM32MP_DDR_DUAL_AXI_PORT \
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STM32MP_EMMC \
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STM32MP_EMMC_BOOT \
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STM32MP_RAW_NAND \
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@ -151,6 +157,8 @@ $(eval $(call add_defines,\
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PLAT_XLAT_TABLES_DYNAMIC \
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STM32_TF_A_COPIES \
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STM32_TF_VERSION \
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STM32MP_DDR_32BIT_INTERFACE \
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STM32MP_DDR_DUAL_AXI_PORT \
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STM32MP_EMMC \
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STM32MP_EMMC_BOOT \
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STM32MP_RAW_NAND \
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