Merge changes from topic "st_fixes" into integration
* changes: fix(stm32_console): do not skip init for crash console fix(plat/st): add UART reset in crash console init refactor(stm32mp1_clk): update RCC registers file fix(stm32mp1_clk): keep RTCAPB clock always on fix(stm32mp1_clk): fix RTC clock rating fix(stm32mp1_clk): correctly manage RTC clock source fix(spi_nand): check correct manufacturer id fix(spi_nand): check that parameters have been set
This commit is contained in:
Madhukar Pappireddy
TrustedFirmware Code Review
commit
890ee3e87a
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2019, STMicroelectronics - All Rights Reserved
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* Copyright (c) 2019-2021, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -286,6 +286,10 @@ int spi_nand_init(unsigned long long *size, unsigned int *erase_size)
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return -EINVAL;
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}
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assert((spinand_dev.nand_dev->page_size != 0U) &&
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(spinand_dev.nand_dev->block_size != 0U) &&
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(spinand_dev.nand_dev->size != 0U));
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ret = spi_nand_reset();
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if (ret != 0) {
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return ret;
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@ -301,12 +305,12 @@ int spi_nand_init(unsigned long long *size, unsigned int *erase_size)
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return ret;
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}
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ret = spi_nand_quad_enable(id[0]);
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ret = spi_nand_quad_enable(id[1]);
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if (ret != 0) {
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return ret;
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}
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VERBOSE("SPI_NAND Detected ID 0x%x 0x%x\n", id[0], id[1]);
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VERBOSE("SPI_NAND Detected ID 0x%x\n", id[1]);
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VERBOSE("Page size %i, Block size %i, size %lli\n",
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spinand_dev.nand_dev->page_size,
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@ -56,6 +56,7 @@ enum stm32mp1_parent_id {
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_HSI_KER = NB_OSC,
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_HSE_KER,
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_HSE_KER_DIV2,
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_HSE_RTC,
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_CSI_KER,
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_PLL1_P,
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_PLL1_Q,
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@ -107,7 +108,7 @@ enum stm32mp1_parent_sel {
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_USBPHY_SEL,
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_USBO_SEL,
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_MPU_SEL,
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_PER_SEL,
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_CKPER_SEL,
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_RTC_SEL,
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_PARENT_SEL_NB,
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_UNKNOWN_SEL = 0xff,
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@ -125,6 +126,7 @@ static const uint8_t parent_id_clock_id[_PARENT_NB] = {
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[_HSI_KER] = CK_HSI,
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[_HSE_KER] = CK_HSE,
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[_HSE_KER_DIV2] = CK_HSE_DIV2,
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[_HSE_RTC] = _UNKNOWN_ID,
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[_CSI_KER] = CK_CSI,
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[_PLL1_P] = PLL1_P,
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[_PLL1_Q] = PLL1_Q,
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@ -490,7 +492,7 @@ static const uint8_t per_parents[] = {
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};
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static const uint8_t rtc_parents[] = {
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_UNKNOWN_ID, _LSE, _LSI, _HSE
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_UNKNOWN_ID, _LSE, _LSI, _HSE_RTC
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};
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static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
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@ -502,7 +504,7 @@ static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
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_CLK_PARENT_SEL(UART1, RCC_UART1CKSELR, usart1_parents),
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_CLK_PARENT_SEL(RNG1, RCC_RNG1CKSELR, rng1_parents),
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_CLK_PARENT_SEL(MPU, RCC_MPCKSELR, mpu_parents),
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_CLK_PARENT_SEL(PER, RCC_CPERCKSELR, per_parents),
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_CLK_PARENT_SEL(CKPER, RCC_CPERCKSELR, per_parents),
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_CLK_PARENT_SEL(RTC, RCC_BDCR, rtc_parents),
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_CLK_PARENT_SEL(UART6, RCC_UART6CKSELR, uart6_parents),
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_CLK_PARENT_SEL(UART24, RCC_UART24CKSELR, uart234578_parents),
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@ -587,6 +589,7 @@ static const char * const stm32mp1_clk_parent_name[_PARENT_NB] __unused = {
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[_HSI_KER] = "HSI_KER",
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[_HSE_KER] = "HSE_KER",
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[_HSE_KER_DIV2] = "HSE_KER_DIV2",
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[_HSE_RTC] = "HSE_RTC",
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[_CSI_KER] = "CSI_KER",
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[_PLL1_P] = "PLL1_P",
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[_PLL1_Q] = "PLL1_Q",
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@ -969,6 +972,10 @@ static unsigned long get_clock_rate(int p)
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case _HSE_KER_DIV2:
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clock = stm32mp1_clk_get_fixed(_HSE) >> 1;
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break;
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case _HSE_RTC:
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clock = stm32mp1_clk_get_fixed(_HSE);
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clock /= (mmio_read_32(rcc_base + RCC_RTCDIVR) & RCC_DIVR_DIV_MASK) + 1U;
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break;
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case _LSI:
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clock = stm32mp1_clk_get_fixed(_LSI);
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break;
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@ -1652,7 +1659,7 @@ static void stm32mp1_set_rtcsrc(unsigned int clksrc, bool lse_css)
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(clksrc != (uint32_t)CLK_RTC_DISABLED)) {
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mmio_clrsetbits_32(address,
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RCC_BDCR_RTCSRC_MASK,
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clksrc << RCC_BDCR_RTCSRC_SHIFT);
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(clksrc & RCC_SELR_SRC_MASK) << RCC_BDCR_RTCSRC_SHIFT);
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mmio_setbits_32(address, RCC_BDCR_RTCCKEN);
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}
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@ -2152,6 +2159,7 @@ static void secure_parent_clocks(unsigned long parent_id)
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case _HSE:
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case _HSE_KER:
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case _HSE_KER_DIV2:
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case _HSE_RTC:
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case _LSE:
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break;
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@ -2210,6 +2218,7 @@ static void sync_earlyboot_clocks_state(void)
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DDRC2, DDRC2LP,
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DDRCAPB, DDRPHYCAPB, DDRPHYCAPBLP,
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DDRPHYC, DDRPHYCLP,
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RTCAPB,
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TZC1, TZC2,
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TZPC,
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STGEN_K,
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@ -2218,10 +2227,6 @@ static void sync_earlyboot_clocks_state(void)
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for (idx = 0U; idx < ARRAY_SIZE(secure_enable); idx++) {
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stm32mp_clk_enable(secure_enable[idx]);
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}
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if (!stm32mp_is_single_core()) {
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stm32mp1_clk_enable_secure(RTCAPB);
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}
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}
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int stm32mp1_clk_probe(void)
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -45,7 +45,12 @@ func console_stm32_core_init
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/* Check the input base address */
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cmp r0, #0
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beq core_init_fail
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#if defined(IMAGE_BL2)
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#if !defined(IMAGE_BL2)
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/* Skip UART initialization if it is already enabled */
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ldr r3, [r0, #USART_CR1]
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ands r3, r3, #USART_CR1_UE
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bne 1f
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#endif /* IMAGE_BL2 */
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/* Check baud rate and uart clock for sanity */
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cmp r1, #0
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beq core_init_fail
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@ -78,7 +83,7 @@ teack_loop:
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ldr r3, [r0, #USART_ISR]
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tst r3, #USART_ISR_TEACK
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beq teack_loop
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#endif /* IMAGE_BL2 */
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1:
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mov r0, #1
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bx lr
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core_init_fail:
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File diff suppressed because it is too large
Load Diff
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@ -205,6 +205,8 @@ enum ddr_type {
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#define DEBUG_UART_TX_CLKSRC RCC_UART24CKSELR_HSI
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#define DEBUG_UART_TX_EN_REG RCC_MP_APB1ENSETR
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#define DEBUG_UART_TX_EN RCC_MP_APB1ENSETR_UART4EN
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#define DEBUG_UART_RST_REG RCC_APB1RSTSETR
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#define DEBUG_UART_RST_BIT RCC_APB1RSTSETR_UART4RST
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/*******************************************************************************
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* STM32MP1 ETZPC
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -148,6 +148,19 @@ endfunc plat_my_core_pos
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* ---------------------------------------------
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*/
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func plat_crash_console_init
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/* Reset UART peripheral */
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ldr r1, =(RCC_BASE + DEBUG_UART_RST_REG)
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ldr r2, =DEBUG_UART_RST_BIT
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str r2, [r1]
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1:
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ldr r0, [r1]
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ands r2, r0, r2
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beq 1b
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str r2, [r1, #4] /* RSTCLR register */
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2:
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ldr r0, [r1]
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ands r2, r0, r2
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bne 2b
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/* Enable GPIOs for UART TX */
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ldr r1, =(RCC_BASE + DEBUG_UART_TX_GPIO_BANK_CLK_REG)
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ldr r2, [r1]
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