From 89121c2764a2f550932826e38a16fd0480038f9e Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Thu, 15 Nov 2018 20:44:40 -0800 Subject: [PATCH] Tegra194: reset power state info for CPUs We set deepest power state when offlining a core but that may not be requested by non-secure sw which controls idle states. It will re-init this info from non-secure software when the core come online. This patch resets the power state in the non-secure world context to allow it to start with a clean slate. Change-Id: Iafd92cb2a49571aa6eeb9580beaaff4ba55a87dc Signed-off-by: Varun Wadekar --- plat/nvidia/tegra/soc/t194/plat_psci_handlers.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c index bd8200456..ce5815b46 100644 --- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c @@ -381,6 +381,10 @@ int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) * will re-init this info from non-secure software when the * core come online. */ + actlr_elx = read_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1)); + actlr_elx &= ~DENVER_CPU_PMSTATE_MASK; + actlr_elx |= DENVER_CPU_PMSTATE_C1; + write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); /* * Check if we are exiting from deep sleep and restore SE