xlat lib: Reorganize architectural defs
Move the header files that provide translation tables architectural definitions from the library v2 source files to the library include directory. This allows to share these definitions between both versions (v1 and v2) of the library. Create a new header file that includes the AArch32 or AArch64 definitions based on the AARCH32 build flag, so that the library user doesn't have to worry about handling it on their side. Also repurpose some of the definitions the header files provide to concentrate on the things that differ between AArch32 and AArch64. As a result they now contain the following information: - the first table level that allows block descriptors; - the architectural limits of the virtual address space; - the initial lookup level to cover the entire address space. Additionally, move the XLAT_TABLE_LEVEL_MIN macro from xlat_tables_defs.h to the AArch32/AArch64 architectural definitions. This new organisation eliminates duplicated information in the AArch32 and AArch64 versions. It also decouples these architectural files from any platform-specific information. Previously, they were dependent on the address space size, which is platform-specific. Finally, for the v2 of the library, move the compatibility code for ADDR_SPACE_SIZE into a C file as it is not needed outside of this file. For v1, this code hasn't been changed and stays in a header file because it's needed by several files. Change-Id: If746c684acd80eebf918abd3ab6e8481d004ac68 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
This commit is contained in:
Sandrine Bailleux
parent
284c3d6709
commit
8933c34bbc
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __XLAT_TABLES_AARCH32_H__
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#define __XLAT_TABLES_AARCH32_H__
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#include <arch.h>
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#include <utils_def.h>
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#include <xlat_tables_defs.h>
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#if !defined(PAGE_SIZE)
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#error "PAGE_SIZE is not defined."
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#endif
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/*
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* In AArch32 state, the MMU only supports 4KB page granularity, which means
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* that the first translation table level is either 1 or 2. Both of them are
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* allowed to have block and table descriptors. See section G4.5.6 of the
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* ARMv8-A Architecture Reference Manual (DDI 0487A.k) for more information.
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*
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* The define below specifies the first table level that allows block
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* descriptors.
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*/
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#if PAGE_SIZE != (4 * 1024)
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#error "Invalid granule size. AArch32 supports 4KB pages only."
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#endif
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#define MIN_LVL_BLOCK_DESC 1
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#define XLAT_TABLE_LEVEL_MIN U(1)
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/*
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* Define the architectural limits of the virtual address space in AArch32
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* state.
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*
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* TTBCR.TxSZ is calculated as 32 minus the width of said address space. The
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* value of TTBCR.TxSZ must be in the range 0 to 7 [1], which means that the
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* virtual address space width must be in the range 32 to 25 bits.
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*
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* [1] See the ARMv8-A Architecture Reference Manual (DDI 0487A.j) for more
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* information, Section G4.6.5
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*/
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#define MIN_VIRT_ADDR_SPACE_SIZE (1 << (32 - TTBCR_TxSZ_MAX))
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#define MAX_VIRT_ADDR_SPACE_SIZE (ULL(1) << (32 - TTBCR_TxSZ_MIN))
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/*
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* Here we calculate the initial lookup level from the value of the given
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* virtual address space size. For a 4 KB page size,
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* - level 1 supports virtual address spaces of widths 32 to 31 bits;
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* - level 2 from 30 to 25.
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*
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* Wider or narrower address spaces are not supported. As a result, level 3
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* cannot be used as the initial lookup level with 4 KB granularity.
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* See the ARMv8-A Architecture Reference Manual (DDI 0487A.j) for more
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* information, Section G4.6.5
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*
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* For example, for a 31-bit address space (i.e. virt_addr_space_size ==
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* 1 << 31), TTBCR.TxSZ will be programmed to (32 - 31) = 1. According to Table
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* G4-5 in the ARM ARM, the initial lookup level for an address space like that
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* is 1.
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*
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* Note that this macro assumes that the given virtual address space size is
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* valid. Therefore, the caller is expected to check it is the case using the
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* CHECK_VIRT_ADDR_SPACE_SIZE() macro first.
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*/
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#define GET_XLAT_TABLE_LEVEL_BASE(virt_addr_space_size) \
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(((virt_addr_space_size) > (1 << L1_XLAT_ADDRESS_SHIFT)) ? 1 : 2)
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#endif /* __XLAT_TABLES_AARCH32_H__ */
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __XLAT_TABLES_AARCH64_H__
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#define __XLAT_TABLES_AARCH64_H__
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#include <arch.h>
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#include <utils_def.h>
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#include <xlat_tables_defs.h>
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#if !defined(PAGE_SIZE)
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#error "PAGE_SIZE is not defined."
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#endif
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/*
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* In AArch64 state, the MMU may support 4 KB, 16 KB and 64 KB page
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* granularity. For 4KB granularity, a level 0 table descriptor doesn't support
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* block translation. For 16KB, the same thing happens to levels 0 and 1. For
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* 64KB, same for level 1. See section D4.3.1 of the ARMv8-A Architecture
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* Reference Manual (DDI 0487A.k) for more information.
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*
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* The define below specifies the first table level that allows block
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* descriptors.
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*/
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#if PAGE_SIZE == (4 * 1024)
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# define MIN_LVL_BLOCK_DESC 1
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#elif PAGE_SIZE == (16 * 1024) || PAGE_SIZE == (64 * 1024)
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# define MIN_LVL_BLOCK_DESC 2
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#endif
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#define XLAT_TABLE_LEVEL_MIN U(0)
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/*
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* Define the architectural limits of the virtual address space in AArch64
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* state.
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*
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* TCR.TxSZ is calculated as 64 minus the width of said address space.
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* The value of TCR.TxSZ must be in the range 16 to 39 [1], which means that
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* the virtual address space width must be in the range 48 to 25 bits.
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*
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* [1] See the ARMv8-A Architecture Reference Manual (DDI 0487A.j) for more
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* information:
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* Page 1730: 'Input address size', 'For all translation stages'.
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*/
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#define MIN_VIRT_ADDR_SPACE_SIZE (1 << (64 - TCR_TxSZ_MAX))
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#define MAX_VIRT_ADDR_SPACE_SIZE (ULL(1) << (64 - TCR_TxSZ_MIN))
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/*
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* Here we calculate the initial lookup level from the value of the given
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* virtual address space size. For a 4 KB page size,
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* - level 0 supports virtual address spaces of widths 48 to 40 bits;
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* - level 1 from 39 to 31;
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* - level 2 from 30 to 25.
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*
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* Wider or narrower address spaces are not supported. As a result, level 3
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* cannot be used as initial lookup level with 4 KB granularity. See section
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* D4.2.5 in the ARMv8-A Architecture Reference Manual (DDI 0487A.j) for more
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* information.
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*
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* For example, for a 35-bit address space (i.e. virt_addr_space_size ==
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* 1 << 35), TCR.TxSZ will be programmed to (64 - 35) = 29. According to Table
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* D4-11 in the ARM ARM, the initial lookup level for an address space like that
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* is 1.
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*
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* Note that this macro assumes that the given virtual address space size is
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* valid. Therefore, the caller is expected to check it is the case using the
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* CHECK_VIRT_ADDR_SPACE_SIZE() macro first.
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*/
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#define GET_XLAT_TABLE_LEVEL_BASE(virt_addr_space_size) \
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(((virt_addr_space_size) > (ULL(1) << L0_XLAT_ADDRESS_SHIFT)) \
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? 0 \
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: (((virt_addr_space_size) > (1 << L1_XLAT_ADDRESS_SHIFT)) ? 1 : 2))
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#endif /* __XLAT_TABLES_AARCH64_H__ */
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __XLAT_TABLES_ARCH_H__
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#define __XLAT_TABLES_ARCH_H__
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#ifdef AARCH32
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#include "aarch32/xlat_tables_aarch32.h"
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#else
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#include "aarch64/xlat_tables_aarch64.h"
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#endif
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/*
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* Evaluates to 1 if the given virtual address space size is valid, or 0 if it's
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* not.
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*
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* A valid size is one that is a power of 2 and is within the architectural
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* limits. Not that these limits are different for AArch32 and AArch64.
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*/
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#define CHECK_VIRT_ADDR_SPACE_SIZE(size) \
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(((size) >= MIN_VIRT_ADDR_SPACE_SIZE) && \
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((size) <= MAX_VIRT_ADDR_SPACE_SIZE) && \
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IS_POWER_OF_TWO(size))
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/*
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* Evaluates to 1 if the given physical address space size is a power of 2,
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* or 0 if it's not.
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*/
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#define CHECK_PHY_ADDR_SPACE_SIZE(size) \
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(IS_POWER_OF_TWO(size))
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/*
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* Compute the number of entries required at the initial lookup level to address
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* the whole virtual address space.
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*/
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#define GET_NUM_BASE_LEVEL_ENTRIES(addr_space_size) \
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((addr_space_size) >> \
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XLAT_ADDR_SHIFT(GET_XLAT_TABLE_LEVEL_BASE(addr_space_size)))
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#endif /* __XLAT_TABLES_ARCH_H__ */
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@ -59,12 +59,6 @@
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#define XLAT_TABLE_SIZE_SHIFT PAGE_SIZE_SHIFT /* Size of one complete table */
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#define XLAT_TABLE_SIZE (U(1) << XLAT_TABLE_SIZE_SHIFT)
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#ifdef AARCH32
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#define XLAT_TABLE_LEVEL_MIN U(1)
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#else
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#define XLAT_TABLE_LEVEL_MIN U(0)
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#endif /* AARCH32 */
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#define XLAT_TABLE_LEVEL_MAX U(3)
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/* Values for number of entries in each MMU translation table */
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@ -7,56 +7,17 @@
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#include <arch.h>
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#include <arch_helpers.h>
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#include <assert.h>
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#include <cassert.h>
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#include <platform_def.h>
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#include <utils.h>
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#include <xlat_tables_arch.h>
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#include <xlat_tables.h>
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#include "../xlat_tables_private.h"
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/*
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* Each platform can define the size of the virtual address space, which is
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* defined in PLAT_VIRT_ADDR_SPACE_SIZE. TTBCR.TxSZ is calculated as 32 minus
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* the width of said address space. The value of TTBCR.TxSZ must be in the
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* range 0 to 7 [1], which means that the virtual address space width must be
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* in the range 32 to 25 bits.
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*
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* Here we calculate the initial lookup level from the value of
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* PLAT_VIRT_ADDR_SPACE_SIZE. For a 4 KB page size, level 1 supports virtual
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* address spaces of widths 32 to 31 bits, and level 2 from 30 to 25. Wider or
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* narrower address spaces are not supported. As a result, level 3 cannot be
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* used as initial lookup level with 4 KB granularity [1].
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*
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* For example, for a 31-bit address space (i.e. PLAT_VIRT_ADDR_SPACE_SIZE ==
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* 1 << 31), TTBCR.TxSZ will be programmed to (32 - 31) = 1. According to Table
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* G4-5 in the ARM ARM, the initial lookup level for an address space like that
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* is 1.
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*
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* See the ARMv8-A Architecture Reference Manual (DDI 0487A.j) for more
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* information:
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* [1] Section G4.6.5
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*/
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#define XLAT_TABLE_LEVEL_BASE \
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GET_XLAT_TABLE_LEVEL_BASE(PLAT_VIRT_ADDR_SPACE_SIZE)
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#if PLAT_VIRT_ADDR_SPACE_SIZE > (1ULL << (32 - TTBCR_TxSZ_MIN))
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# error "PLAT_VIRT_ADDR_SPACE_SIZE is too big."
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#elif PLAT_VIRT_ADDR_SPACE_SIZE > (1 << L1_XLAT_ADDRESS_SHIFT)
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# define XLAT_TABLE_LEVEL_BASE 1
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# define NUM_BASE_LEVEL_ENTRIES \
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(PLAT_VIRT_ADDR_SPACE_SIZE >> L1_XLAT_ADDRESS_SHIFT)
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#elif PLAT_VIRT_ADDR_SPACE_SIZE >= (1 << (32 - TTBCR_TxSZ_MAX))
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# define XLAT_TABLE_LEVEL_BASE 2
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# define NUM_BASE_LEVEL_ENTRIES \
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(PLAT_VIRT_ADDR_SPACE_SIZE >> L2_XLAT_ADDRESS_SHIFT)
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#else
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# error "PLAT_VIRT_ADDR_SPACE_SIZE is too small."
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#endif
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#define NUM_BASE_LEVEL_ENTRIES \
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GET_NUM_BASE_LEVEL_ENTRIES(PLAT_VIRT_ADDR_SPACE_SIZE)
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static uint64_t base_xlation_table[NUM_BASE_LEVEL_ENTRIES]
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__aligned(NUM_BASE_LEVEL_ENTRIES * sizeof(uint64_t));
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@ -8,66 +8,19 @@
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#include <arch_helpers.h>
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#include <assert.h>
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#include <bl_common.h>
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#include <cassert.h>
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#include <common_def.h>
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#include <platform_def.h>
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#include <sys/types.h>
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#include <utils.h>
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#include <xlat_tables.h>
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#include <xlat_tables_arch.h>
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#include "../xlat_tables_private.h"
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/*
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* Each platform can define the size of the virtual address space, which is
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* defined in PLAT_VIRT_ADDR_SPACE_SIZE. TCR.TxSZ is calculated as 64 minus the
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* width of said address space. The value of TCR.TxSZ must be in the range 16
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* to 39 [1], which means that the virtual address space width must be in the
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* range 48 to 25 bits.
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*
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* Here we calculate the initial lookup level from the value of
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* PLAT_VIRT_ADDR_SPACE_SIZE. For a 4 KB page size, level 0 supports virtual
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* address spaces of widths 48 to 40 bits, level 1 from 39 to 31, and level 2
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* from 30 to 25. Wider or narrower address spaces are not supported. As a
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* result, level 3 cannot be used as initial lookup level with 4 KB
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* granularity. [2]
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*
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* For example, for a 35-bit address space (i.e. PLAT_VIRT_ADDR_SPACE_SIZE ==
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* 1 << 35), TCR.TxSZ will be programmed to (64 - 35) = 29. According to Table
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* D4-11 in the ARM ARM, the initial lookup level for an address space like
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* that is 1.
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*
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* See the ARMv8-A Architecture Reference Manual (DDI 0487A.j) for more
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* information:
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* [1] Page 1730: 'Input address size', 'For all translation stages'.
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* [2] Section D4.2.5
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*/
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#define XLAT_TABLE_LEVEL_BASE \
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GET_XLAT_TABLE_LEVEL_BASE(PLAT_VIRT_ADDR_SPACE_SIZE)
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#if PLAT_VIRT_ADDR_SPACE_SIZE > (1ULL << (64 - TCR_TxSZ_MIN))
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# error "PLAT_VIRT_ADDR_SPACE_SIZE is too big."
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#elif PLAT_VIRT_ADDR_SPACE_SIZE > (1ULL << L0_XLAT_ADDRESS_SHIFT)
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# define XLAT_TABLE_LEVEL_BASE 0
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# define NUM_BASE_LEVEL_ENTRIES \
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(PLAT_VIRT_ADDR_SPACE_SIZE >> L0_XLAT_ADDRESS_SHIFT)
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#elif PLAT_VIRT_ADDR_SPACE_SIZE > (1 << L1_XLAT_ADDRESS_SHIFT)
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# define XLAT_TABLE_LEVEL_BASE 1
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# define NUM_BASE_LEVEL_ENTRIES \
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(PLAT_VIRT_ADDR_SPACE_SIZE >> L1_XLAT_ADDRESS_SHIFT)
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#elif PLAT_VIRT_ADDR_SPACE_SIZE >= (1 << (64 - TCR_TxSZ_MAX))
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# define XLAT_TABLE_LEVEL_BASE 2
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# define NUM_BASE_LEVEL_ENTRIES \
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(PLAT_VIRT_ADDR_SPACE_SIZE >> L2_XLAT_ADDRESS_SHIFT)
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#else
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# error "PLAT_VIRT_ADDR_SPACE_SIZE is too small."
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#endif
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#define NUM_BASE_LEVEL_ENTRIES \
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GET_NUM_BASE_LEVEL_ENTRIES(PLAT_VIRT_ADDR_SPACE_SIZE)
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static uint64_t base_xlation_table[NUM_BASE_LEVEL_ENTRIES]
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__aligned(NUM_BASE_LEVEL_ENTRIES * sizeof(uint64_t));
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@ -9,7 +9,7 @@
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#include <cassert.h>
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#include <platform_def.h>
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#include <utils_def.h>
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#include <xlat_tables_arch.h>
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/*
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* If the platform hasn't defined a physical and a virtual address space size
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# endif
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#endif
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/* The virtual and physical address space sizes must be powers of two. */
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CASSERT(IS_POWER_OF_TWO(PLAT_VIRT_ADDR_SPACE_SIZE),
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CASSERT(CHECK_VIRT_ADDR_SPACE_SIZE(PLAT_VIRT_ADDR_SPACE_SIZE),
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assert_valid_virt_addr_space_size);
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CASSERT(IS_POWER_OF_TWO(PLAT_PHY_ADDR_SPACE_SIZE),
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CASSERT(CHECK_PHY_ADDR_SPACE_SIZE(PLAT_PHY_ADDR_SPACE_SIZE),
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assert_valid_phy_addr_space_size);
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/*
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* In AArch32 state, the MMU only supports 4KB page granularity, which means
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* that the first translation table level is either 1 or 2. Both of them are
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* allowed to have block and table descriptors. See section G4.5.6 of the
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* ARMv8-A Architecture Reference Manual (DDI 0487A.k) for more information.
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*
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* In AArch64 state, the MMU may support 4 KB, 16 KB and 64 KB page
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* granularity. For 4KB granularity, a level 0 table descriptor doesn't support
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* block translation. For 16KB, the same thing happens to levels 0 and 1. For
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* 64KB, same for level 1. See section D4.3.1 of the ARMv8-A Architecture
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* Reference Manual (DDI 0487A.k) for more information.
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*
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* The define below specifies the first table level that allows block
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* descriptors.
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*/
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#ifdef AARCH32
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# define XLAT_BLOCK_LEVEL_MIN 1
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#else /* if AArch64 */
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# if PAGE_SIZE == (4*1024) /* 4KB */
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# define XLAT_BLOCK_LEVEL_MIN 1
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# else /* 16KB or 64KB */
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# define XLAT_BLOCK_LEVEL_MIN 2
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# endif
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#endif /* AARCH32 */
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/* Alias to retain compatibility with the old #define name */
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#define XLAT_BLOCK_LEVEL_MIN MIN_LVL_BLOCK_DESC
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void print_mmap(void);
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|
@ -1,72 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __XLAT_TABLES_ARCH_H__
|
||||
#define __XLAT_TABLES_ARCH_H__
|
||||
|
||||
#include <arch.h>
|
||||
#include <platform_def.h>
|
||||
#include <xlat_tables_defs.h>
|
||||
#include "../xlat_tables_private.h"
|
||||
|
||||
/*
|
||||
* In AArch32 state, the MMU only supports 4KB page granularity, which means
|
||||
* that the first translation table level is either 1 or 2. Both of them are
|
||||
* allowed to have block and table descriptors. See section G4.5.6 of the
|
||||
* ARMv8-A Architecture Reference Manual (DDI 0487A.k) for more information.
|
||||
*
|
||||
* The define below specifies the first table level that allows block
|
||||
* descriptors.
|
||||
*/
|
||||
|
||||
#define MIN_LVL_BLOCK_DESC 1
|
||||
|
||||
/*
|
||||
* Each platform can define the size of the virtual address space, which is
|
||||
* defined in PLAT_VIRT_ADDR_SPACE_SIZE. TTBCR.TxSZ is calculated as 32 minus
|
||||
* the width of said address space. The value of TTBCR.TxSZ must be in the
|
||||
* range 0 to 7 [1], which means that the virtual address space width must be
|
||||
* in the range 32 to 25 bits.
|
||||
*
|
||||
* Here we calculate the initial lookup level from the value of
|
||||
* PLAT_VIRT_ADDR_SPACE_SIZE. For a 4 KB page size, level 1 supports virtual
|
||||
* address spaces of widths 32 to 31 bits, and level 2 from 30 to 25. Wider or
|
||||
* narrower address spaces are not supported. As a result, level 3 cannot be
|
||||
* used as initial lookup level with 4 KB granularity [1].
|
||||
*
|
||||
* For example, for a 31-bit address space (i.e. PLAT_VIRT_ADDR_SPACE_SIZE ==
|
||||
* 1 << 31), TTBCR.TxSZ will be programmed to (32 - 31) = 1. According to Table
|
||||
* G4-5 in the ARM ARM, the initial lookup level for an address space like that
|
||||
* is 1.
|
||||
*
|
||||
* See the ARMv8-A Architecture Reference Manual (DDI 0487A.j) for more
|
||||
* information:
|
||||
* [1] Section G4.6.5
|
||||
*/
|
||||
|
||||
#if PLAT_VIRT_ADDR_SPACE_SIZE > (1ULL << (32 - TTBCR_TxSZ_MIN))
|
||||
|
||||
# error "PLAT_VIRT_ADDR_SPACE_SIZE is too big."
|
||||
|
||||
#elif PLAT_VIRT_ADDR_SPACE_SIZE > (1 << L1_XLAT_ADDRESS_SHIFT)
|
||||
|
||||
# define XLAT_TABLE_LEVEL_BASE 1
|
||||
# define NUM_BASE_LEVEL_ENTRIES \
|
||||
(PLAT_VIRT_ADDR_SPACE_SIZE >> L1_XLAT_ADDRESS_SHIFT)
|
||||
|
||||
#elif PLAT_VIRT_ADDR_SPACE_SIZE >= (1 << (32 - TTBCR_TxSZ_MAX))
|
||||
|
||||
# define XLAT_TABLE_LEVEL_BASE 2
|
||||
# define NUM_BASE_LEVEL_ENTRIES \
|
||||
(PLAT_VIRT_ADDR_SPACE_SIZE >> L2_XLAT_ADDRESS_SHIFT)
|
||||
|
||||
#else
|
||||
|
||||
# error "PLAT_VIRT_ADDR_SPACE_SIZE is too small."
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* __XLAT_TABLES_ARCH_H__ */
|
||||
|
|
@ -1,85 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __XLAT_TABLES_ARCH_H__
|
||||
#define __XLAT_TABLES_ARCH_H__
|
||||
|
||||
#include <arch.h>
|
||||
#include <platform_def.h>
|
||||
#include <xlat_tables_defs.h>
|
||||
#include "../xlat_tables_private.h"
|
||||
|
||||
/*
|
||||
* In AArch64 state, the MMU may support 4 KB, 16 KB and 64 KB page
|
||||
* granularity. For 4KB granularity, a level 0 table descriptor doesn't support
|
||||
* block translation. For 16KB, the same thing happens to levels 0 and 1. For
|
||||
* 64KB, same for level 1. See section D4.3.1 of the ARMv8-A Architecture
|
||||
* Reference Manual (DDI 0487A.k) for more information.
|
||||
*
|
||||
* The define below specifies the first table level that allows block
|
||||
* descriptors.
|
||||
*/
|
||||
|
||||
#if PAGE_SIZE == (4*1024) /* 4KB */
|
||||
# define MIN_LVL_BLOCK_DESC 1
|
||||
#else /* 16KB or 64KB */
|
||||
# define MIN_LVL_BLOCK_DESC 2
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Each platform can define the size of the virtual address space, which is
|
||||
* defined in PLAT_VIRT_ADDR_SPACE_SIZE. TCR.TxSZ is calculated as 64 minus the
|
||||
* width of said address space. The value of TCR.TxSZ must be in the range 16
|
||||
* to 39 [1], which means that the virtual address space width must be in the
|
||||
* range 48 to 25 bits.
|
||||
*
|
||||
* Here we calculate the initial lookup level from the value of
|
||||
* PLAT_VIRT_ADDR_SPACE_SIZE. For a 4 KB page size, level 0 supports virtual
|
||||
* address spaces of widths 48 to 40 bits, level 1 from 39 to 31, and level 2
|
||||
* from 30 to 25. Wider or narrower address spaces are not supported. As a
|
||||
* result, level 3 cannot be used as initial lookup level with 4 KB
|
||||
* granularity. [2]
|
||||
*
|
||||
* For example, for a 35-bit address space (i.e. PLAT_VIRT_ADDR_SPACE_SIZE ==
|
||||
* 1 << 35), TCR.TxSZ will be programmed to (64 - 35) = 29. According to Table
|
||||
* D4-11 in the ARM ARM, the initial lookup level for an address space like
|
||||
* that is 1.
|
||||
*
|
||||
* See the ARMv8-A Architecture Reference Manual (DDI 0487A.j) for more
|
||||
* information:
|
||||
* [1] Page 1730: 'Input address size', 'For all translation stages'.
|
||||
* [2] Section D4.2.5
|
||||
*/
|
||||
|
||||
#if PLAT_VIRT_ADDR_SPACE_SIZE > (1ULL << (64 - TCR_TxSZ_MIN))
|
||||
|
||||
# error "PLAT_VIRT_ADDR_SPACE_SIZE is too big."
|
||||
|
||||
#elif PLAT_VIRT_ADDR_SPACE_SIZE > (1ULL << L0_XLAT_ADDRESS_SHIFT)
|
||||
|
||||
# define XLAT_TABLE_LEVEL_BASE 0
|
||||
# define NUM_BASE_LEVEL_ENTRIES \
|
||||
(PLAT_VIRT_ADDR_SPACE_SIZE >> L0_XLAT_ADDRESS_SHIFT)
|
||||
|
||||
#elif PLAT_VIRT_ADDR_SPACE_SIZE > (1 << L1_XLAT_ADDRESS_SHIFT)
|
||||
|
||||
# define XLAT_TABLE_LEVEL_BASE 1
|
||||
# define NUM_BASE_LEVEL_ENTRIES \
|
||||
(PLAT_VIRT_ADDR_SPACE_SIZE >> L1_XLAT_ADDRESS_SHIFT)
|
||||
|
||||
#elif PLAT_VIRT_ADDR_SPACE_SIZE >= (1 << (64 - TCR_TxSZ_MAX))
|
||||
|
||||
# define XLAT_TABLE_LEVEL_BASE 2
|
||||
# define NUM_BASE_LEVEL_ENTRIES \
|
||||
(PLAT_VIRT_ADDR_SPACE_SIZE >> L2_XLAT_ADDRESS_SHIFT)
|
||||
|
||||
#else
|
||||
|
||||
# error "PLAT_VIRT_ADDR_SPACE_SIZE is too small."
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* __XLAT_TABLES_ARCH_H__ */
|
||||
|
|
@ -15,14 +15,41 @@
|
|||
#include <string.h>
|
||||
#include <types.h>
|
||||
#include <utils.h>
|
||||
#include <xlat_tables_arch.h>
|
||||
#include <xlat_tables_v2.h>
|
||||
#ifdef AARCH32
|
||||
# include "aarch32/xlat_tables_arch.h"
|
||||
#else
|
||||
# include "aarch64/xlat_tables_arch.h"
|
||||
#endif
|
||||
|
||||
#include "xlat_tables_private.h"
|
||||
|
||||
/*
|
||||
* Each platform can define the size of its physical and virtual address spaces.
|
||||
* If the platform hasn't defined one or both of them, default to
|
||||
* ADDR_SPACE_SIZE. The latter is deprecated, though.
|
||||
*/
|
||||
#if ERROR_DEPRECATED
|
||||
# ifdef ADDR_SPACE_SIZE
|
||||
# error "ADDR_SPACE_SIZE is deprecated. Use PLAT_xxx_ADDR_SPACE_SIZE instead."
|
||||
# endif
|
||||
#elif defined(ADDR_SPACE_SIZE)
|
||||
# ifndef PLAT_PHY_ADDR_SPACE_SIZE
|
||||
# define PLAT_PHY_ADDR_SPACE_SIZE ADDR_SPACE_SIZE
|
||||
# endif
|
||||
# ifndef PLAT_VIRT_ADDR_SPACE_SIZE
|
||||
# define PLAT_VIRT_ADDR_SPACE_SIZE ADDR_SPACE_SIZE
|
||||
# endif
|
||||
#endif
|
||||
|
||||
CASSERT(CHECK_VIRT_ADDR_SPACE_SIZE(PLAT_VIRT_ADDR_SPACE_SIZE),
|
||||
assert_invalid_virtual_addr_space_size);
|
||||
|
||||
CASSERT(CHECK_PHY_ADDR_SPACE_SIZE(PLAT_PHY_ADDR_SPACE_SIZE),
|
||||
assert_invalid_physical_addr_space_size);
|
||||
|
||||
#define NUM_BASE_LEVEL_ENTRIES \
|
||||
GET_NUM_BASE_LEVEL_ENTRIES(PLAT_VIRT_ADDR_SPACE_SIZE)
|
||||
|
||||
#define XLAT_TABLE_LEVEL_BASE \
|
||||
GET_XLAT_TABLE_LEVEL_BASE(PLAT_VIRT_ADDR_SPACE_SIZE)
|
||||
|
||||
/*
|
||||
* Private variables used by the TF
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -15,12 +15,10 @@
|
|||
#include <string.h>
|
||||
#include <types.h>
|
||||
#include <utils.h>
|
||||
#include <xlat_tables_arch.h>
|
||||
#include <xlat_tables_defs.h>
|
||||
#include <xlat_tables_v2.h>
|
||||
#ifdef AARCH32
|
||||
# include "aarch32/xlat_tables_arch.h"
|
||||
#else
|
||||
# include "aarch64/xlat_tables_arch.h"
|
||||
#endif
|
||||
|
||||
#include "xlat_tables_private.h"
|
||||
|
||||
#if PLAT_XLAT_TABLES_DYNAMIC
|
||||
|
|
|
|||
|
|
@ -7,32 +7,8 @@
|
|||
#ifndef __XLAT_TABLES_PRIVATE_H__
|
||||
#define __XLAT_TABLES_PRIVATE_H__
|
||||
|
||||
#include <cassert.h>
|
||||
#include <platform_def.h>
|
||||
#include <utils_def.h>
|
||||
|
||||
/*
|
||||
* If the platform hasn't defined a physical and a virtual address space size
|
||||
* default to ADDR_SPACE_SIZE.
|
||||
*/
|
||||
#if ERROR_DEPRECATED
|
||||
# ifdef ADDR_SPACE_SIZE
|
||||
# error "ADDR_SPACE_SIZE is deprecated. Use PLAT_xxx_ADDR_SPACE_SIZE instead."
|
||||
# endif
|
||||
#elif defined(ADDR_SPACE_SIZE)
|
||||
# ifndef PLAT_PHY_ADDR_SPACE_SIZE
|
||||
# define PLAT_PHY_ADDR_SPACE_SIZE ADDR_SPACE_SIZE
|
||||
# endif
|
||||
# ifndef PLAT_VIRT_ADDR_SPACE_SIZE
|
||||
# define PLAT_VIRT_ADDR_SPACE_SIZE ADDR_SPACE_SIZE
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/* The virtual and physical address space sizes must be powers of two. */
|
||||
CASSERT(IS_POWER_OF_TWO(PLAT_VIRT_ADDR_SPACE_SIZE),
|
||||
assert_valid_virt_addr_space_size);
|
||||
CASSERT(IS_POWER_OF_TWO(PLAT_PHY_ADDR_SPACE_SIZE),
|
||||
assert_valid_phy_addr_space_size);
|
||||
#include <xlat_tables_defs.h>
|
||||
|
||||
/* Struct that holds all information about the translation tables. */
|
||||
typedef struct {
|
||||
|
|
|
|||
Loading…
Reference in New Issue