From 25844ff728e4a0e5430ba2032457aba7b780a701 Mon Sep 17 00:00:00 2001 From: Jorge Ramirez-Ortiz Date: Fri, 15 Apr 2022 11:46:47 +0200 Subject: [PATCH 1/2] feat(bl31): aarch64: RESET_TO_BL31_WITH_PARAMS It is not always the case that RESET_TO_BL31 enabled platforms don't execute a bootloader before BL31. For those use cases, being able to receive arguments from that first loader (i.e: a DTB with TPM logs) might be necessary feature. This code has been validated on iMX8mm. Signed-off-by: Jorge Ramirez-Ortiz Change-Id: Ibf00c3867cb1d1012b8b376e64ccaeca1c9d2bff --- Makefile | 2 ++ bl31/aarch64/bl31_entrypoint.S | 4 +++- make_helpers/defaults.mk | 3 +++ 3 files changed, 8 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index da3e4931e..ebeb5ed4c 100644 --- a/Makefile +++ b/Makefile @@ -996,6 +996,7 @@ $(eval $(call assert_booleans,\ PROGRAMMABLE_RESET_ADDRESS \ PSCI_EXTENDED_STATE_ID \ RESET_TO_BL31 \ + RESET_TO_BL31_WITH_PARAMS \ SAVE_KEYS \ SEPARATE_CODE_AND_RODATA \ SEPARATE_BL2_NOLOAD_REGION \ @@ -1127,6 +1128,7 @@ $(eval $(call add_defines,\ PSCI_EXTENDED_STATE_ID \ RAS_EXTENSION \ RESET_TO_BL31 \ + RESET_TO_BL31_WITH_PARAMS \ SEPARATE_CODE_AND_RODATA \ SEPARATE_BL2_NOLOAD_REGION \ SEPARATE_NOBITS_REGION \ diff --git a/bl31/aarch64/bl31_entrypoint.S b/bl31/aarch64/bl31_entrypoint.S index ed058648f..b0c46dc7b 100644 --- a/bl31/aarch64/bl31_entrypoint.S +++ b/bl31/aarch64/bl31_entrypoint.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -67,6 +67,7 @@ func bl31_entrypoint _exception_vectors=runtime_exceptions \ _pie_fixup_size=BL31_LIMIT - BL31_BASE +#if !RESET_TO_BL31_WITH_PARAMS /* --------------------------------------------------------------------- * For RESET_TO_BL31 systems, BL31 is the first bootloader to run so * there's no argument to relay from a previous bootloader. Zero the @@ -77,6 +78,7 @@ func bl31_entrypoint mov x21, 0 mov x22, 0 mov x23, 0 +#endif /* RESET_TO_BL31_WITH_PARAMS */ #endif /* RESET_TO_BL31 */ /* -------------------------------------------------------------------- diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk index 99f44a4ec..eb58b36a8 100644 --- a/make_helpers/defaults.mk +++ b/make_helpers/defaults.mk @@ -254,6 +254,9 @@ RAS_EXTENSION := 0 # By default, BL1 acts as the reset handler, not BL31 RESET_TO_BL31 := 0 +# By default, clear the input registers when RESET_TO_BL31 is enabled +RESET_TO_BL31_WITH_PARAMS := 0 + # For Chain of Trust SAVE_KEYS := 0 From ac4ac38c5443afdef38e38e9247c96359de3a2ea Mon Sep 17 00:00:00 2001 From: Jorge Ramirez-Ortiz Date: Fri, 15 Apr 2022 11:51:03 +0200 Subject: [PATCH 2/2] docs(bl31): aarch64: RESET_TO_BL31_WITH_PARAMS Document the RESET_TO_BL31 with parameters feature. Signed-off-by: Jorge Ramirez-Ortiz Change-Id: I47014d724f2eb822b69a112c3acee546fbfe82d5 --- docs/design/reset-design.rst | 17 ++++++++++++----- docs/getting_started/build-options.rst | 5 +++++ 2 files changed, 17 insertions(+), 5 deletions(-) diff --git a/docs/design/reset-design.rst b/docs/design/reset-design.rst index 7b10c956c..666ee4f0d 100644 --- a/docs/design/reset-design.rst +++ b/docs/design/reset-design.rst @@ -141,19 +141,26 @@ CPU executes a modified BL31 initialization, as described below. Platform initialization ~~~~~~~~~~~~~~~~~~~~~~~ -In this configuration, when the CPU resets to BL31 there are no parameters that -can be passed in registers by previous boot stages. Instead, the platform code -in BL31 needs to know, or be able to determine, the location of the BL32 (if -required) and BL33 images and provide this information in response to the +In this configuration, when the CPU resets to BL31 there should be no parameters +that can be passed in registers by previous boot stages. Instead, the platform +code in BL31 needs to know, or be able to determine, the location of the BL32 +(if required) and BL33 images and provide this information in response to the ``bl31_plat_get_next_image_ep_info()`` function. +.. note:: + Some platforms that configure ``RESET_TO_BL31`` might still be able to + receive parameters in registers depending on their actual boot sequence. On + those occasions, and in addition to ``RESET_TO_BL31``, these platforms should + set ``RESET_TO_BL31_WITH_PARAMS`` to avoid the input registers from being + zeroed before entering BL31. + Additionally, platform software is responsible for carrying out any security initialisation, for example programming a TrustZone address space controller. This might be done by the Trusted Boot Firmware or by platform code in BL31. -------------- -*Copyright (c) 2015-2019, Arm Limited and Contributors. All rights reserved.* +*Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved.* .. |Default reset code flow| image:: ../resources/diagrams/default_reset_code.png .. |Reset code flow with programmable reset address| image:: ../resources/diagrams/reset_code_no_boot_type_check.png diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst index 4dbf5cb9f..46d57406b 100644 --- a/docs/getting_started/build-options.rst +++ b/docs/getting_started/build-options.rst @@ -709,6 +709,11 @@ Common build options entrypoint) or 1 (CPU reset to BL31 entrypoint). The default value is 0. +- ``RESET_TO_BL31_WITH_PARAMS``: If ``RESET_TO_BL31`` has been enabled, setting + this additional option guarantees that the input registers are not cleared + therefore allowing parameters to be passed to the BL31 entrypoint. + The default value is 0. + - ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1