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Merge changes from topic "corstone700" into integration 

* changes:
  corstone700: set UART clocks to 32MHz
  corstone700: clean-up as per coding style guide
  Corstone700: add support for mhuv2 in arm TF-A
This commit is contained in:
Manish Pandey 2020-02-18 21:47:38 +00:00 committed by TrustedFirmware Code Review
parent 76ce1028b0 6aa138ded5
commit 8a10c6c274
7 changed files with 243 additions and 57 deletions
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17
fdts/corstone700.dts
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2019-2020, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -68,14 +68,21 @@
clock-output-names = "smclk";
};
uartclk: uartclk {
/* UART clock - 32MHz */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32000000>;
clock-output-names = "uartclk";
};
serial0: uart@1a510000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x1a510000 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 19 4>;
clocks = <&refclk100mhz>, <&smbclk>;
clock-names = "apb_pclk", "smclk";
clocks = <&uartclk>, <&refclk100mhz>;
clock-names = "uartclk", "apb_pclk";
};
serial1: uart@1a520000 {
@ -83,8 +90,8 @@
reg = <0x1a520000 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 20 4>;
clocks = <&refclk100mhz>, <&smbclk>;
clock-names = "apb_pclk", "smclk";
clocks = <&uartclk>, <&refclk100mhz>;
clock-names = "uartclk", "apb_pclk";
};
timer {

5
plat/arm/board/corstone700/corstone700_plat.c
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@ -1,10 +1,12 @@
/*
* Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2019-2020, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/bl_common.h>
#include <mhu.h>
#include <plat/arm/common/plat_arm.h>
#include <plat/common/platform.h>
#include <platform_def.h>
@ -26,6 +28,7 @@ const mmap_region_t plat_arm_mmap[] = {
*/
void __init plat_arm_pwrc_setup(void)
{
mhu_secure_init();
}
unsigned int plat_get_syscnt_freq2(void)

6
plat/arm/board/corstone700/corstone700_topology.c
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -8,8 +8,8 @@
#include <plat/common/platform.h>
/* The Corstone700 power domain tree descriptor */
static unsigned char corstone700_power_domain_tree_desc
[PLAT_ARM_CLUSTER_COUNT + 2];
static unsigned char corstone700_power_domain_tree_desc[PLAT_ARM_CLUSTER_COUNT
+ 2];
/*******************************************************************************
* This function dynamically constructs the topology according to
* CLUSTER_COUNT and returns it.

117
plat/arm/board/corstone700/drivers/mhu/mhu.c Normal file
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@ -0,0 +1,117 @@
/*
* Copyright (c) 2019-2020, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <arch_helpers.h>
#include <common/debug.h>
#include <drivers/delay_timer.h>
#include <lib/bakery_lock.h>
#include <lib/mmio.h>
#include "mhu.h"
#include <plat_arm.h>
#include <platform_def.h>
ARM_INSTANTIATE_LOCK;
#pragma weak plat_arm_pwrc_setup
/*
* Slot 31 is reserved because the MHU hardware uses this register bit to
* indicate a non-secure access attempt. The total number of available slots is
* therefore 31 [30:0].
*/
#define MHU_MAX_SLOT_ID 30
void mhu_secure_message_start(uintptr_t address, unsigned int slot_id)
{
unsigned int intr_stat_check;
uint64_t timeout_cnt;
volatile uint8_t expiration;
assert(slot_id <= MHU_MAX_SLOT_ID);
arm_lock_get();
/*
* Make sure any previous command has finished
* and polling timeout not expired
*/
timeout_cnt = timeout_init_us(MHU_POLL_INTR_STAT_TIMEOUT);
do {
intr_stat_check = (mmio_read_32(address + CPU_INTR_S_STAT) &
(1 << slot_id));
expiration = timeout_elapsed(timeout_cnt);
} while ((intr_stat_check != 0U) && (expiration == 0U));
/*
* Note: No risk of timer overflows while waiting
* for the timeout expiration.
* According to Armv8 TRM: System counter roll-over
* time of not less than 40 years
*/
}
void mhu_secure_message_send(uintptr_t address,
unsigned int slot_id,
unsigned int message)
{
unsigned char access_ready;
uint64_t timeout_cnt;
volatile uint8_t expiration;
assert(slot_id <= MHU_MAX_SLOT_ID);
assert((mmio_read_32(address + CPU_INTR_S_STAT) &
(1 << slot_id)) == 0U);
MHU_V2_ACCESS_REQUEST(address);
timeout_cnt = timeout_init_us(MHU_POLL_INTR_STAT_TIMEOUT);
do {
access_ready = MHU_V2_IS_ACCESS_READY(address);
expiration = timeout_elapsed(timeout_cnt);
} while ((access_ready == 0U) && (expiration == 0U));
/*
* Note: No risk of timer overflows while waiting
* for the timeout expiration.
* According to Armv8 TRM: System counter roll-over
* time of not less than 40 years
*/
mmio_write_32(address + CPU_INTR_S_SET, message);
}
void mhu_secure_message_end(uintptr_t address, unsigned int slot_id)
{
assert(slot_id <= MHU_MAX_SLOT_ID);
/*
* Clear any response we got by writing one in the relevant slot bit to
* the CLEAR register
*/
MHU_V2_CLEAR_REQUEST(address);
arm_lock_release();
}
void __init mhu_secure_init(void)
{
arm_lock_init();
/*
* The STAT register resets to zero. Ensure it is in the expected state,
* as a stale or garbage value would make us think it's a message we've
* already sent.
*/
assert(mmio_read_32(PLAT_SDK700_MHU0_SEND + CPU_INTR_S_STAT) == 0);
}

37
plat/arm/board/corstone700/drivers/mhu/mhu.h Normal file
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@ -0,0 +1,37 @@
/*
* Copyright (c) 2019-2020, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MHU_H
#define MHU_H
#define MHU_POLL_INTR_STAT_TIMEOUT 50000 /*timeout value in us*/
/* CPU MHU secure channel registers */
#define CPU_INTR_S_STAT 0x00
#define CPU_INTR_S_SET 0x0C
/* MHUv2 Control Registers Offsets */
#define MHU_V2_MSG_CFG_OFFSET 0xF80
#define MHU_V2_ACCESS_REQ_OFFSET 0xF88
#define MHU_V2_ACCESS_READY_OFFSET 0xF8C
#define MHU_V2_ACCESS_REQUEST(addr) \
mmio_write_32((addr) + MHU_V2_ACCESS_REQ_OFFSET, 0x1)
#define MHU_V2_CLEAR_REQUEST(addr) \
mmio_write_32((addr) + MHU_V2_ACCESS_REQ_OFFSET, 0x0)
#define MHU_V2_IS_ACCESS_READY(addr) \
(mmio_read_32((addr) + MHU_V2_ACCESS_READY_OFFSET) & 0x1)
void mhu_secure_message_start(uintptr_t address, unsigned int slot_id);
void mhu_secure_message_send(uintptr_t address,
unsigned int slot_id,
unsigned int message);
void mhu_secure_message_end(uintptr_t address, unsigned int slot_id);
void mhu_secure_init(void);
#endif /* MHU_H */

101
plat/arm/board/corstone700/include/platform_def.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2019-2020, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -9,20 +9,35 @@
#include <lib/utils_def.h>
#include <lib/xlat_tables/xlat_tables_defs.h>
#include <plat/arm/board/common/v2m_def.h>
#include <plat/arm/common/arm_spm_def.h>
#include <plat/common/common_def.h>
/* PL011 UART related constants */
#ifdef V2M_IOFPGA_UART0_CLK_IN_HZ
#undef V2M_IOFPGA_UART0_CLK_IN_HZ
#endif
#ifdef V2M_IOFPGA_UART1_CLK_IN_HZ
#undef V2M_IOFPGA_UART1_CLK_IN_HZ
#endif
#define V2M_IOFPGA_UART0_CLK_IN_HZ 32000000
#define V2M_IOFPGA_UART1_CLK_IN_HZ 32000000
/* Core/Cluster/Thread counts for Corstone700 */
#define CORSTONE700_CLUSTER_COUNT U(1)
#define CORSTONE700_MAX_CPUS_PER_CLUSTER U(4)
#define CORSTONE700_MAX_PE_PER_CPU U(1)
#define CORSTONE700_CORE_COUNT (CORSTONE700_CLUSTER_COUNT * \
CORSTONE700_MAX_CPUS_PER_CLUSTER * \
CORSTONE700_MAX_PE_PER_CPU)
#define PLATFORM_CORE_COUNT CORSTONE700_CORE_COUNT
#define PLAT_ARM_CLUSTER_COUNT CORSTONE700_CLUSTER_COUNT
#define PLATFORM_CORE_COUNT (PLAT_ARM_CLUSTER_COUNT * \
CORSTONE700_MAX_CPUS_PER_CLUSTER * \
CORSTONE700_MAX_PE_PER_CPU)
/* UART related constants */
#define PLAT_ARM_BOOT_UART_BASE 0x1a510000
#define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ
@ -85,8 +100,12 @@
ARM_BL_REGIONS)
/* GIC related constants */
#define PLAT_ARM_GICD_BASE 0x1C010000
#define PLAT_ARM_GICC_BASE 0x1C02F000
#define PLAT_ARM_GICD_BASE 0x1C010000
#define PLAT_ARM_GICC_BASE 0x1C02F000
/* MHUv2 Secure Channel receiver and sender */
#define PLAT_SDK700_MHU0_SEND 0x1B800000
#define PLAT_SDK700_MHU0_RECV 0x1B810000
/* Timer/watchdog related constants */
#define ARM_SYS_CNTCTL_BASE UL(0x1a200000)
@ -101,46 +120,46 @@
* Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The
* power levels have a 1:1 mapping with the MPIDR affinity levels.
*/
#define ARM_PWR_LVL0 MPIDR_AFFLVL0
#define ARM_PWR_LVL1 MPIDR_AFFLVL1
#define ARM_PWR_LVL2 MPIDR_AFFLVL2
#define ARM_PWR_LVL0 MPIDR_AFFLVL0
#define ARM_PWR_LVL1 MPIDR_AFFLVL1
#define ARM_PWR_LVL2 MPIDR_AFFLVL2
/*
* Macros for local power states in ARM platforms encoded by State-ID field
* within the power-state parameter.
*/
/* Local power state for power domains in Run state. */
#define ARM_LOCAL_STATE_RUN U(0)
#define ARM_LOCAL_STATE_RUN U(0)
/* Local power state for retention. Valid only for CPU power domains */
#define ARM_LOCAL_STATE_RET U(1)
#define ARM_LOCAL_STATE_RET U(1)
/* Local power state for OFF/power-down. Valid for CPU and cluster
* power domains
*/
#define ARM_LOCAL_STATE_OFF U(2)
#define ARM_LOCAL_STATE_OFF U(2)
#define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE
#define PLAT_ARM_NSTIMER_FRAME_ID U(1)
#define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE
#define PLAT_ARM_NSTIMER_FRAME_ID U(1)
#define PLAT_ARM_NS_IMAGE_OFFSET (ARM_DRAM1_BASE + UL(0x8000000))
#define PLAT_ARM_NS_IMAGE_OFFSET (ARM_DRAM1_BASE + UL(0x8000000))
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
/*
* This macro defines the deepest retention state possible. A higher state
* ID will represent an invalid or a power down state.
*/
#define PLAT_MAX_RET_STATE 1
#define PLAT_MAX_RET_STATE 1
/*
* This macro defines the deepest power down states possible. Any state ID
* higher than this is invalid.
*/
#define PLAT_MAX_OFF_STATE 2
#define PLAT_MAX_OFF_STATE 2
#define PLATFORM_STACK_SIZE UL(0x440)
#define PLATFORM_STACK_SIZE UL(0x440)
#define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \
#define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \
ARM_SHARED_RAM_BASE, \
ARM_SHARED_RAM_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
@ -170,21 +189,21 @@
#define CORSTONE700_DEVICE_BASE (0x1A000000)
#define CORSTONE700_DEVICE_SIZE (0x26000000)
#define CORSTONE700_MAP_DEVICE MAP_REGION_FLAT( \
CORSTONE700_DEVICE_BASE, \
CORSTONE700_DEVICE_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
#define CORSTONE700_MAP_DEVICE MAP_REGION_FLAT( \
CORSTONE700_DEVICE_BASE,\
CORSTONE700_DEVICE_SIZE,\
MT_DEVICE | MT_RW | MT_SECURE)
#define ARM_IRQ_SEC_PHY_TIMER 29
#define ARM_IRQ_SEC_PHY_TIMER 29
#define ARM_IRQ_SEC_SGI_0 8
#define ARM_IRQ_SEC_SGI_1 9
#define ARM_IRQ_SEC_SGI_2 10
#define ARM_IRQ_SEC_SGI_3 11
#define ARM_IRQ_SEC_SGI_4 12
#define ARM_IRQ_SEC_SGI_5 13
#define ARM_IRQ_SEC_SGI_6 14
#define ARM_IRQ_SEC_SGI_7 15
#define ARM_IRQ_SEC_SGI_0 8
#define ARM_IRQ_SEC_SGI_1 9
#define ARM_IRQ_SEC_SGI_2 10
#define ARM_IRQ_SEC_SGI_3 11
#define ARM_IRQ_SEC_SGI_4 12
#define ARM_IRQ_SEC_SGI_5 13
#define ARM_IRQ_SEC_SGI_6 14
#define ARM_IRQ_SEC_SGI_7 15
/*
* Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3
@ -192,7 +211,7 @@
* as Group 0 interrupts.
*/
#define ARM_G1S_IRQ_PROPS(grp) \
INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \
INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \
(grp), GIC_INTR_CFG_LEVEL), \
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \
(grp), GIC_INTR_CFG_EDGE), \
@ -217,11 +236,11 @@
* as Group 0 interrupts.
*/
#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
ARM_G1S_IRQ_PROPS(grp), \
INTR_PROP_DESC(CORSTONE700_IRQ_TZ_WDOG, \
GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_LEVEL), \
INTR_PROP_DESC(CORSTONE700_IRQ_SEC_SYS_TIMER, \
GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_LEVEL) \
ARM_G1S_IRQ_PROPS(grp), \
INTR_PROP_DESC(CORSTONE700_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, \
(grp), GIC_INTR_CFG_LEVEL), \
INTR_PROP_DESC(CORSTONE700_IRQ_SEC_SYS_TIMER, \
GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_LEVEL)
#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp)

17
plat/arm/board/corstone700/platform.mk
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@ -1,5 +1,5 @@
#
# Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
# Copyright (c) 2019-2020, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@ -11,16 +11,19 @@ BL32_SOURCES += plat/arm/common/aarch32/arm_helpers.S \
plat/arm/common/arm_common.c \
lib/xlat_tables/aarch32/xlat_tables.c \
lib/xlat_tables/xlat_tables_common.c \
${CORSTONE700_CPU_LIBS}
${CORSTONE700_CPU_LIBS} \
plat/arm/board/corstone700/drivers/mhu/mhu.c
PLAT_INCLUDES := -Iplat/arm/board/corstone700/include
PLAT_INCLUDES := -Iplat/arm/board/corstone700/include \
-Iinclude/plat/arm/common \
-Iplat/arm/board/corstone700/drivers/mhu
NEED_BL32 := yes
CORSTONE700_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
drivers/arm/gic/v2/gicv2_main.c \
drivers/arm/gic/v2/gicv2_helpers.c \
plat/common/plat_gicv2.c \
CORSTONE700_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
drivers/arm/gic/v2/gicv2_main.c \
drivers/arm/gic/v2/gicv2_helpers.c \
plat/common/plat_gicv2.c \
plat/arm/common/arm_gicv2.c
# BL1/BL2 Image not a part of the capsule Image for Corstone700