Merge changes I1784d643,Icb6e3699,I7805756e into integration
* changes: fix(errata): workaround for Cortex-A510 erratum 2172148 fix(errata): workaround for Cortex-A510 erratum 2218950 fix(errata): workaround for Cortex-A510 erratum 2250311
This commit is contained in:
Bipin Ravi
TrustedFirmware Code Review
commit
8a34299289
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@ -493,6 +493,19 @@ For Cortex-A510, the following errata build flags are defined :
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in r0p3. The issue is also present in r0p0 and r0p1 but there is no
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workaround for those revisions.
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- ``ERRATA_A510_2250311``: This applies errata 2250311 workaround to
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Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2,
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r0p3 and r1p0, it is fixed in r1p1. This workaround disables MPMM even if
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ENABLE_MPMM=1.
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- ``ERRATA_A510_2218950``: This applies errata 2218950 workaround to
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Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2,
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r0p3 and r1p0, it is fixed in r1p1.
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- ``ERRATA_A510_2172148``: This applies errata 2172148 workaround to
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Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2,
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r0p3 and r1p0, it is fixed in r1p1.
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DSU Errata Workarounds
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----------------------
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@ -15,6 +15,8 @@
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#define CORTEX_A510_CPUECTLR_EL1 S3_0_C15_C1_4
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#define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT U(19)
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#define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE U(1)
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#define CORTEX_A510_CPUECTLR_EL1_RSCTL_SHIFT U(23)
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#define CORTEX_A510_CPUECTLR_EL1_NTCTL_SHIFT U(46)
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/*******************************************************************************
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* CPU Power Control register specific definitions
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@ -153,6 +153,117 @@ func check_errata_2041909
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b cpu_rev_var_range
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endfunc check_errata_2041909
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/* --------------------------------------------------
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* Errata Workaround for Cortex-A510 Errata #2250311.
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* This applies only to revisions r0p0, r0p1, r0p2,
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* r0p3 and r1p0, and is fixed in r1p1.
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* This workaround is not a typical errata fix. MPMM
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* is disabled here, but this conflicts with the BL31
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* MPMM support. So in addition to simply disabling
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* the feature, a flag is set in the MPMM library
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* indicating that it should not be enabled even if
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* ENABLE_MPMM=1.
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0, x1, x17
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* --------------------------------------------------
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*/
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func errata_cortex_a510_2250311_wa
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/* Check workaround compatibility. */
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mov x17, x30
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bl check_errata_2250311
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cbz x0, 1f
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/* Disable MPMM */
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mrs x0, CPUMPMMCR_EL3
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bfm x0, xzr, #0, #0 /* bfc instruction does not work in GCC */
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msr CPUMPMMCR_EL3, x0
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#if ENABLE_MPMM && IMAGE_BL31
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/* If ENABLE_MPMM is set, tell the runtime lib to skip enabling it. */
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bl mpmm_errata_disable
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#endif
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1:
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ret x17
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endfunc errata_cortex_a510_2250311_wa
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func check_errata_2250311
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/* Applies to r1p0 and lower */
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mov x1, #0x10
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b cpu_rev_var_ls
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endfunc check_errata_2250311
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/* --------------------------------------------------
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* Errata Workaround for Cortex-A510 Errata #2218950.
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* This applies only to revisions r0p0, r0p1, r0p2,
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* r0p3 and r1p0, and is fixed in r1p1.
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0, x1, x17
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* --------------------------------------------------
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*/
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func errata_cortex_a510_2218950_wa
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/* Check workaround compatibility. */
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mov x17, x30
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bl check_errata_2218950
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cbz x0, 1f
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/* Source register for BFI */
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mov x1, #1
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/* Set bit 18 in CPUACTLR_EL1 */
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mrs x0, CORTEX_A510_CPUACTLR_EL1
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bfi x0, x1, #18, #1
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msr CORTEX_A510_CPUACTLR_EL1, x0
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/* Set bit 25 in CMPXACTLR_EL1 */
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mrs x0, CORTEX_A510_CMPXACTLR_EL1
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bfi x0, x1, #25, #1
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msr CORTEX_A510_CMPXACTLR_EL1, x0
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1:
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ret x17
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endfunc errata_cortex_a510_2218950_wa
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func check_errata_2218950
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/* Applies to r1p0 and lower */
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mov x1, #0x10
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b cpu_rev_var_ls
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endfunc check_errata_2218950
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/* --------------------------------------------------
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* Errata Workaround for Cortex-A510 Errata #2172148.
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* This applies only to revisions r0p0, r0p1, r0p2,
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* r0p3 and r1p0, and is fixed in r1p1.
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0, x1, x17
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* --------------------------------------------------
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*/
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func errata_cortex_a510_2172148_wa
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/* Check workaround compatibility. */
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mov x17, x30
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bl check_errata_2172148
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cbz x0, 1f
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/*
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* Force L2 allocation of transient lines by setting
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* CPUECTLR_EL1.RSCTL=0b01 and CPUECTLR_EL1.NTCTL=0b01.
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*/
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mrs x0, CORTEX_A510_CPUECTLR_EL1
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mov x1, #1
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bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_RSCTL_SHIFT, #2
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bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_NTCTL_SHIFT, #2
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msr CORTEX_A510_CPUECTLR_EL1, x0
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1:
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ret x17
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endfunc errata_cortex_a510_2172148_wa
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func check_errata_2172148
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/* Applies to r1p0 and lower */
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mov x1, #0x10
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b cpu_rev_var_ls
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endfunc check_errata_2172148
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/* ----------------------------------------------------
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* HW will do the cache maintenance while powering down
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* ----------------------------------------------------
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@ -187,6 +298,9 @@ func cortex_a510_errata_report
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report_errata ERRATA_A510_2288014, cortex_a510, 2288014
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report_errata ERRATA_A510_2042739, cortex_a510, 2042739
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report_errata ERRATA_A510_2041909, cortex_a510, 2041909
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report_errata ERRATA_A510_2250311, cortex_a510, 2250311
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report_errata ERRATA_A510_2218950, cortex_a510, 2218950
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report_errata ERRATA_A510_2172148, cortex_a510, 2172148
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ldp x8, x30, [sp], #16
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ret
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@ -224,6 +338,21 @@ func cortex_a510_reset_func
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bl errata_cortex_a510_2041909_wa
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#endif
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#if ERRATA_A510_2250311
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mov x0, x18
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bl errata_cortex_a510_2250311_wa
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#endif
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#if ERRATA_A510_2218950
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mov x0, x18
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bl errata_cortex_a510_2218950_wa
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#endif
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#if ERRATA_A510_2172148
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mov x0, x18
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bl errata_cortex_a510_2172148_wa
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#endif
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ret x19
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endfunc cortex_a510_reset_func
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@ -548,6 +548,18 @@ ERRATA_A510_2042739 ?=0
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# present in r0p0 and r0p1 but there is no workaround for those revisions.
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ERRATA_A510_2041909 ?=0
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# Flag to apply erratum 2250311 workaround during reset. This erratum applies
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# to revisions r0p0, r0p1, r0p2, r0p3 and r1p0, and is fixed in r1p1.
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ERRATA_A510_2250311 ?=0
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# Flag to apply erratum 2218950 workaround during reset. This erratum applies
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# to revisions r0p0, r0p1, r0p2, r0p3 and r1p0, and is fixed in r1p1.
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ERRATA_A510_2218950 ?=0
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# Flag to apply erratum 2172148 workaround during reset. This erratum applies
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# to revisions r0p0, r0p1, r0p2, r0p3 and r1p0, and is fixed in r1p1.
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ERRATA_A510_2172148 ?=0
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# Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0.
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# Applying the workaround results in higher DSU power consumption on idle.
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ERRATA_DSU_798953 ?=0
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@ -1021,6 +1033,18 @@ $(eval $(call add_define,ERRATA_A510_2042739))
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$(eval $(call assert_boolean,ERRATA_A510_2041909))
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$(eval $(call add_define,ERRATA_A510_2041909))
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# Process ERRATA_A510_2250311 flag
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$(eval $(call assert_boolean,ERRATA_A510_2250311))
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$(eval $(call add_define,ERRATA_A510_2250311))
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# Process ERRATA_A510_2218950 flag
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$(eval $(call assert_boolean,ERRATA_A510_2218950))
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$(eval $(call add_define,ERRATA_A510_2218950))
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# Process ERRATA_A510_2172148 flag
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$(eval $(call assert_boolean,ERRATA_A510_2172148))
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$(eval $(call add_define,ERRATA_A510_2172148))
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# Process ERRATA_DSU_798953 flag
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$(eval $(call assert_boolean,ERRATA_DSU_798953))
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$(eval $(call add_define,ERRATA_DSU_798953))
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2021, Arm Limited. All rights reserved.
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* Copyright (c) 2021-2022, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -62,11 +62,25 @@ static bool mpmm_supported(void)
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return supported;
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}
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/* Defaults to false */
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static bool mpmm_disable_for_errata;
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void mpmm_enable(void)
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{
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bool supported = mpmm_supported();
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if (supported) {
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if (mpmm_supported()) {
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if (mpmm_disable_for_errata) {
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WARN("MPMM: disabled by errata workaround\n");
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return;
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}
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write_cpumpmmcr_el3_mpmm_en(1U);
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}
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}
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/*
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* This function is called from assembly code very early in BL31 so it must be
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* small and simple.
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*/
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void mpmm_errata_disable(void)
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{
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mpmm_disable_for_errata = true;
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}
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