fix(errata): workaround for Cortex-A710 erratum 2136059

Cortex-A710 erratum 2136059 is a Cat B erratum that applies to
revisions r0p0, r1p0 and r2p0 of the CPU. It is fixed in r2p1.
The workaround is to set CPUACTLR5_EL1[44] to 1 which will cause
the CPP instruction to invalidate the hardware prefetcher state
trained from any EL.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I43a86a365418fb663cc1b6ab1d365b4beddae0bc
This commit is contained in:
Bipin Ravi 2022-02-06 03:11:44 -06:00
parent cfe1a8f712
commit 8a855bd243
4 changed files with 49 additions and 0 deletions

View File

@ -413,6 +413,10 @@ For Cortex-A710, the following errata build flags are defined :
Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
of the CPU and is fixed in r2p1.
- ``ERRATA_A710_2136059``: This applies errata 2136059 workaround to
Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
of the CPU and is fixed in r2p1.
For Neoverse N2, the following errata build flags are defined :
- ``ERRATA_N2_2002655``: This applies errata 2002655 workaround to Neoverse-N2

View File

@ -33,6 +33,7 @@
******************************************************************************/
#define CORTEX_A710_CPUACTLR5_EL1 S3_0_C15_C8_0
#define CORTEX_A710_CPUACTLR5_EL1_BIT_13 (ULL(1) << 13)
#define CORTEX_A710_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44)
/*******************************************************************************
* CPU Auxiliary Control register specific definitions.

View File

@ -245,6 +245,36 @@ func check_errata_2267065
b cpu_rev_var_ls
endfunc check_errata_2267065
/* ---------------------------------------------------------------
* Errata Workaround for Cortex-A710 Erratum 2136059.
* This applies to revision r0p0, r1p0 and r2p0.
* It is fixed in r2p1.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* ---------------------------------------------------------------
*/
func errata_a710_2136059_wa
/* Compare x0 against revision r2p0 */
mov x17, x30
bl check_errata_2136059
cbz x0, 1f
/* Apply the workaround */
mrs x1, CORTEX_A710_CPUACTLR5_EL1
orr x1, x1, CORTEX_A710_CPUACTLR5_EL1_BIT_44
msr CORTEX_A710_CPUACTLR5_EL1, x1
1:
ret x17
endfunc errata_a710_2136059_wa
func check_errata_2136059
/* Applies to r0p0, r1p0 and r2p0 */
mov x1, #0x20
b cpu_rev_var_ls
endfunc check_errata_2136059
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down
* ----------------------------------------------------
@ -282,6 +312,7 @@ func cortex_a710_errata_report
report_errata ERRATA_A710_2083908, cortex_a710, 2083908
report_errata ERRATA_A710_2058056, cortex_a710, 2058056
report_errata ERRATA_A710_2267065, cortex_a710, 2267065
report_errata ERRATA_A710_2136059, cortex_a710, 2136059
ldp x8, x30, [sp], #16
ret
@ -332,6 +363,11 @@ func cortex_a710_reset_func
bl errata_a710_2267065_wa
#endif
#if ERRATA_A710_2136059
mov x0, x18
bl errata_a710_2136059_wa
#endif
isb
ret x19
endfunc cortex_a710_reset_func

View File

@ -499,6 +499,10 @@ ERRATA_A710_2017096 ?=0
# to revision r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is fixed in r2p1.
ERRATA_A710_2267065 ?=0
# Flag to apply erratum 2136059 workaround during reset. This erratum applies
# to revision r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is fixed in r2p1.
ERRATA_A710_2136059 ?=0
# Flag to apply erratum 2002765 workaround during reset. This erratum applies
# to revisions r0p0, r1p0, and r2p0 of the Cortex-X2 cpu and is still open.
ERRATA_X2_2002765 ?=0
@ -955,6 +959,10 @@ $(eval $(call add_define,ERRATA_A710_2017096))
$(eval $(call assert_boolean,ERRATA_A710_2267065))
$(eval $(call add_define,ERRATA_A710_2267065))
# Process ERRATA_A710_2136059 flag
$(eval $(call assert_boolean,ERRATA_A710_2136059))
$(eval $(call add_define,ERRATA_A710_2136059))
# Process ERRATA_X2_2002765 flag
$(eval $(call assert_boolean,ERRATA_X2_2002765))
$(eval $(call add_define,ERRATA_X2_2002765))