intel: Add ncore ccu driver
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I0544315986ee28b23157fdfec3fe5aebae6b860f
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/*
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* Copyright (c) 2019, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <common/debug.h>
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#include <errno.h>
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#include <lib/mmio.h>
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#include "ncore_ccu.h"
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#include <platform_def.h>
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uint32_t poll_active_bit(uint32_t dir);
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static coh_ss_id_t subsystem_id;
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void get_subsystem_id(void)
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{
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uint32_t snoop_filter, directory, coh_agent;
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snoop_filter = CSIDR_NUM_SF(mmio_read_32(NCORE_CCU_CSR(NCORE_CSIDR)));
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directory = CSUIDR_NUM_DIR(mmio_read_32(NCORE_CCU_CSR(NCORE_CSUIDR)));
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coh_agent = CSUIDR_NUM_CAI(mmio_read_32(NCORE_CCU_CSR(NCORE_CSUIDR)));
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subsystem_id.num_snoop_filter = snoop_filter + 1;
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subsystem_id.num_directory = directory;
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subsystem_id.num_coh_agent = coh_agent;
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}
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uint32_t directory_init(void)
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{
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uint32_t dir_sf_mtn, dir_sf_en;
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uint32_t dir, sf, ret;
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for (dir = 0; dir < subsystem_id.num_directory; dir++) {
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dir_sf_mtn = DIRECTORY_UNIT(dir, NCORE_DIRUSFMCR);
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dir_sf_en = DIRECTORY_UNIT(dir, NCORE_DIRUSFER);
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for (sf = 0; sf < subsystem_id.num_snoop_filter; sf++) {
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/* Initialize All Entries */
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mmio_write_32(dir_sf_mtn, SNOOP_FILTER_ID(sf));
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/* Poll Active Bit */
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ret = poll_active_bit(dir);
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if (ret != 0) {
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ERROR("Timeout during active bit polling");
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return -ETIMEDOUT;
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}
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/* Snoope Filter Enable */
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mmio_write_32(dir_sf_en, BIT(sf));
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}
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}
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return 0;
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}
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uint32_t coherent_agent_intfc_init(void)
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{
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uint32_t dir, ca, ca_id, ca_type, ca_snoop_en;
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for (dir = 0; dir < subsystem_id.num_directory; dir++) {
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ca_snoop_en = DIRECTORY_UNIT(dir, NCORE_DIRUCASER0);
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for (ca = 0; ca < subsystem_id.num_coh_agent; ca++) {
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ca_id = mmio_read_32(COH_AGENT_UNIT(ca, NCORE_CAIUIDR));
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/* Coh Agent Snoop Enable */
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if (CACHING_AGENT_BIT(ca_id))
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mmio_write_32(ca_snoop_en, BIT(ca));
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/* Coh Agent Snoop DVM Enable */
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ca_type = CACHING_AGENT_TYPE(ca_id);
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if (ca_type == ACE_W_DVM || ca_type == ACE_L_W_DVM)
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mmio_write_32(NCORE_CCU_CSR(NCORE_CSADSER0),
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BIT(ca));
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}
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}
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return 0;
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}
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uint32_t poll_active_bit(uint32_t dir)
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{
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uint32_t timeout = 80000;
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uint32_t poll_dir = DIRECTORY_UNIT(dir, NCORE_DIRUSFMAR);
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while (timeout > 0) {
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if (mmio_read_32(poll_dir) == 0)
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return 0;
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timeout--;
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}
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return -1;
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}
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void bypass_ocram_firewall(void)
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{
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mmio_clrbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF1),
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OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);
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mmio_clrbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF2),
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OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);
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mmio_clrbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF3),
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OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);
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mmio_clrbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF4),
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OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);
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}
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uint32_t init_ncore_ccu(void)
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{
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uint32_t status;
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get_subsystem_id();
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status = directory_init();
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status = coherent_agent_intfc_init();
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bypass_ocram_firewall();
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return status;
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}
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@ -0,0 +1,108 @@
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/*
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* Copyright (c) 2019, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef NCORE_CCU_H
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#define NCORE_CCU_H
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#define NCORE_CCU_OFFSET 0xf7000000
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/* Coherent Sub-System Address Map */
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#define NCORE_CAIU_OFFSET 0x00000
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#define NCORE_CAIU_SIZE 0x01000
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#define NCORE_NCBU_OFFSET 0x60000
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#define NCORE_NCBU_SIZE 0x01000
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#define NCORE_DIRU_OFFSET 0x80000
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#define NCORE_DIRU_SIZE 0x01000
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#define NCORE_CMIU_OFFSET 0xc0000
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#define NCORE_CMIU_SIZE 0x01000
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#define NCORE_CSR_OFFSET 0xff000
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#define NCORE_CSADSERO 0x00040
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#define NCORE_CSUIDR 0x00ff8
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#define NCORE_CSIDR 0x00ffc
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/* Directory Unit Register Map */
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#define NCORE_DIRUSFER 0x00010
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#define NCORE_DIRUMRHER 0x00070
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#define NCORE_DIRUSFMCR 0x00080
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#define NCORE_DIRUSFMAR 0x00084
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/* Coherent Agent Interface Unit Register Map */
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#define NCORE_CAIUIDR 0x00ffc
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/* Snoop Enable Register */
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#define NCORE_DIRUCASER0 0x00040
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#define NCORE_DIRUCASER1 0x00044
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#define NCORE_DIRUCASER2 0x00048
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#define NCORE_DIRUCASER3 0x0004c
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#define NCORE_CSADSER0 0x00040
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#define NCORE_CSADSER1 0x00044
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#define NCORE_CSADSER2 0x00048
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#define NCORE_CSADSER3 0x0004c
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/* Protocols Definition */
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#define ACE_W_DVM 0
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#define ACE_L_W_DVM 1
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#define ACE_WO_DVM 2
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#define ACE_L_WO_DVM 3
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/* Bypass OC Ram Firewall */
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#define NCORE_FW_OCRAM_BLK_BASE 0x100200
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#define NCORE_FW_OCRAM_BLK_CGF1 0x04
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#define NCORE_FW_OCRAM_BLK_CGF2 0x08
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#define NCORE_FW_OCRAM_BLK_CGF3 0x0c
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#define NCORE_FW_OCRAM_BLK_CGF4 0x10
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#define OCRAM_PRIVILEGED_MASK BIT(29)
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#define OCRAM_SECURE_MASK BIT(30)
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/* Macros */
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#define NCORE_CCU_REG(base) (NCORE_CCU_OFFSET + (base))
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#define NCORE_CCU_CSR(reg) (NCORE_CCU_REG(NCORE_CSR_OFFSET)\
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+ (reg))
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#define NCORE_CCU_DIR(reg) (NCORE_CCU_REG(NCORE_DIRU_OFFSET)\
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+ (reg))
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#define NCORE_CCU_CAI(reg) (NCORE_CCU_REG(NCORE_CAIU_OFFSET)\
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+ (reg))
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#define DIRECTORY_UNIT(x, reg) (NCORE_CCU_DIR(reg)\
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+ NCORE_DIRU_SIZE * (x))
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#define COH_AGENT_UNIT(x, reg) (NCORE_CCU_CAI(reg)\
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+ NCORE_CAIU_SIZE * (x))
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#define COH_CPU0_BYPASS_REG(reg) (NCORE_CCU_REG(NCORE_FW_OCRAM_BLK_BASE)\
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+ (reg))
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#define CSUIDR_NUM_CMI(x) (((x) & 0x3f000000) >> 24)
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#define CSUIDR_NUM_DIR(x) (((x) & 0x003f0000) >> 16)
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#define CSUIDR_NUM_NCB(x) (((x) & 0x00003f00) >> 8)
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#define CSUIDR_NUM_CAI(x) (((x) & 0x0000007f) >> 0)
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#define CSIDR_NUM_SF(x) (((x) & 0x007c0000) >> 18)
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#define SNOOP_FILTER_ID(x) (((x) << 16))
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#define CACHING_AGENT_BIT(x) (((x) & 0x08000) >> 15)
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#define CACHING_AGENT_TYPE(x) (((x) & 0xf0000) >> 16)
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typedef struct coh_ss_id {
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uint8_t num_coh_mem;
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uint8_t num_directory;
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uint8_t num_non_coh_bridge;
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uint8_t num_coh_agent;
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uint8_t num_snoop_filter;
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} coh_ss_id_t;
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uint32_t init_ncore_ccu(void);
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#endif
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