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Various improvements/cleanups on the linker scripts 

- Check at link-time that bootloader images will fit in memory
    at run time and that they won't overlap each other.
  - Remove text and rodata orphan sections.
  - Define new linker symbols to remove the need for platform setup
    code to know the order of sections.
  - Reduce the size of the raw binary images by cutting some sections
    out of the disk image and allocating them at load time, whenever
    possible.
  - Rework alignment constraints on sections.
  - Remove unused linker symbols.
  - Homogenize linker symbols names across all BLs.
  - Add some comments in the linker scripts.

Change-Id: I47a328af0ccc7c8ab47fcc0dc6e7dd26160610b9
This commit is contained in:
Sandrine Bailleux 2013-11-27 09:38:52 +00:00 committed by Dan Handley
parent 3e850a84c9
commit 8d69a03f6a
17 changed files with 263 additions and 207 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/aarch64/cpu/cpu_helpers.S
View File

@ -33,7 +33,7 @@
.weak cpu_reset_handler
.section aarch64_code, "ax"; .align 3
.section .text, "ax"; .align 3
cpu_reset_handler:; .type cpu_reset_handler, %function
mov x19, x30 // lr

2
arch/system/gic/aarch64/gic_v3_sysregs.S
View File

@ -48,7 +48,7 @@
#define ICC_CTLR_EL3 S3_6_C12_C12_4
#define ICC_PMR_EL1 S3_0_C4_C6_0
.section platform_code, "ax"; .align 3
.section .text, "ax"; .align 3
read_icc_sre_el1:; .type read_icc_sre_el1, %function
mrs x0, ICC_SRE_EL1

2
bl1/aarch64/bl1_entrypoint.S
View File

@ -33,7 +33,7 @@
.globl reset_handler
.section reset_code, "ax"; .align 3
.section .text, "ax"; .align 3
/* -----------------------------------------------------
* reset_handler() is the entry point into the trusted

90
bl1/bl1.ld.S
View File

@ -34,57 +34,77 @@ OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
MEMORY {
/* ROM is read-only and executable */
ROM (rx): ORIGIN = TZROM_BASE, LENGTH = TZROM_SIZE
/* RAM is read/write and Initialised */
RAM (rwx): ORIGIN = TZRAM_BASE, LENGTH = TZRAM_SIZE
}
SECTIONS
{
FIRMWARE_ROM : {
*(reset_code)
ro : {
__RO_START__ = .;
*bl1_entrypoint.o(.text)
*(.text)
*(.rodata)
*(.rodata*)
__RO_END__ = .;
} >ROM
.bss : {
__BSS_RAM_START__ = .;
*(.bss)
*(COMMON)
__BSS_RAM_STOP__ = .;
} >RAM AT>ROM
.data : {
/*
* The .data section gets copied from ROM to RAM at runtime.
* Its LMA and VMA must be 16-byte aligned.
*/
. = NEXT(16); /* Align LMA */
.data : ALIGN(16) { /* Align VMA */
__DATA_RAM_START__ = .;
*(.data)
__DATA_RAM_STOP__ = .;
} >RAM AT>ROM
FIRMWARE_RAM_STACKS ALIGN (PLATFORM_CACHE_LINE_SIZE) : {
. += 0x1000;
*(tzfw_normal_stacks)
. = ALIGN(4096);
__DATA_RAM_END__ = .;
} >RAM AT>ROM
FIRMWARE_RAM_COHERENT ALIGN (4096): {
*(tzfw_coherent_mem)
/* . += 0x1000;*/
/* Do we need to make sure this is at least 4k? */
. = ALIGN(4096);
stacks (NOLOAD) : {
__STACKS_START__ = .;
*(tzfw_normal_stacks)
__STACKS_END__ = .;
} >RAM
__FIRMWARE_ROM_START__ = LOADADDR(FIRMWARE_ROM);
__FIRMWARE_ROM_SIZE__ = SIZEOF(FIRMWARE_ROM);
/*
* The .bss section gets initialised to 0 at runtime.
* Its base address must be 16-byte aligned.
*/
.bss : ALIGN(16) {
__BSS_START__ = .;
*(.bss)
*(COMMON)
__BSS_END__ = .;
} >RAM
__FIRMWARE_DATA_START__ = LOADADDR(.data);
__FIRMWARE_DATA_SIZE__ = SIZEOF(.data);
/*
* The base address of the coherent memory section must be page-aligned (4K)
* to guarantee that the coherent data are stored on their own pages and
* are not mixed with normal data. This is required to set up the correct
* memory attributes for the coherent data page tables.
*/
coherent_ram (NOLOAD) : ALIGN(4096) {
__COHERENT_RAM_START__ = .;
*(tzfw_coherent_mem)
__COHERENT_RAM_END_UNALIGNED__ = .;
/*
* Memory page(s) mapped to this section will be marked
* as device memory. No other unexpected data must creep in.
* Ensure the rest of the current memory page is unused.
*/
. = NEXT(4096);
__COHERENT_RAM_END__ = .;
} >RAM
__FIRMWARE_BSS_START__ = LOADADDR(.bss);
__FIRMWARE_BSS_SIZE__ = SIZEOF(.bss);
__BL1_RAM_START__ = ADDR(.data);
__BL1_RAM_END__ = .;
__FIRMWARE_RAM_STACKS_START__ = LOADADDR(FIRMWARE_RAM_STACKS);
__FIRMWARE_RAM_STACKS_SIZE__ = SIZEOF(FIRMWARE_RAM_STACKS);
__FIRMWARE_RAM_COHERENT_START__ = LOADADDR(FIRMWARE_RAM_COHERENT);
__FIRMWARE_RAM_COHERENT_SIZE__ = SIZEOF(FIRMWARE_RAM_COHERENT);
__DATA_ROM_START__ = LOADADDR(.data);
__DATA_SIZE__ = SIZEOF(.data);
__BSS_SIZE__ = SIZEOF(.bss);
__COHERENT_RAM_UNALIGNED_SIZE__ =
__COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
ASSERT(. <= BL31_BASE, "BL31 image overlaps BL1 image.")
}

2
bl2/aarch64/bl2_entrypoint.S
View File

@ -35,7 +35,7 @@
.globl bl2_entrypoint
.section entry_code, "ax"; .align 3
.section .text, "ax"; .align 3
bl2_entrypoint:; .type bl2_entrypoint, %function

80
bl2/bl2.ld.S
View File

@ -34,7 +34,6 @@ OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
MEMORY {
/* RAM is read/write and Initialised */
RAM (rwx): ORIGIN = TZRAM_BASE, LENGTH = TZRAM_SIZE
}
@ -42,44 +41,69 @@ MEMORY {
SECTIONS
{
. = BL2_BASE;
ASSERT(. == ALIGN(4096),
"BL2_BASE address is not aligned on a page boundary.")
BL2_RO NEXT (4096): {
*(entry_code)
*(.text .rodata)
ro . : {
__RO_START__ = .;
*bl2_entrypoint.o(.text)
*(.text)
*(.rodata*)
__RO_END_UNALIGNED__ = .;
/*
* Memory page(s) mapped to this section will be marked as
* read-only, executable. No RW data from the next section must
* creep in. Ensure the rest of the current memory page is unused.
*/
. = NEXT(4096);
__RO_END__ = .;
} >RAM
BL2_STACKS NEXT (4096): {
.data . : {
__DATA_START__ = .;
*(.data)
__DATA_END__ = .;
} >RAM
stacks (NOLOAD) : {
__STACKS_START__ = .;
*(tzfw_normal_stacks)
__STACKS_END__ = .;
} >RAM
BL2_COHERENT_RAM NEXT (4096): {
*(tzfw_coherent_mem)
/* . += 0x1000;*/
/* Do we need to ensure at least 4k here? */
. = NEXT(4096);
} >RAM
__BL2_DATA_START__ = .;
.bss NEXT (4096): {
/*
* The .bss section gets initialised to 0 at runtime.
* Its base address must be 16-byte aligned.
*/
.bss : ALIGN(16) {
__BSS_START__ = .;
*(SORT_BY_ALIGNMENT(.bss))
*(COMMON)
__BSS_END__ = .;
} >RAM
.data : {
*(.data)
/*
* The base address of the coherent memory section must be page-aligned (4K)
* to guarantee that the coherent data are stored on their own pages and
* are not mixed with normal data. This is required to set up the correct
* memory attributes for the coherent data page tables.
*/
coherent_ram (NOLOAD) : ALIGN(4096) {
__COHERENT_RAM_START__ = .;
*(tzfw_coherent_mem)
__COHERENT_RAM_END_UNALIGNED__ = .;
/*
* Memory page(s) mapped to this section will be marked
* as device memory. No other unexpected data must creep in.
* Ensure the rest of the current memory page is unused.
*/
. = NEXT(4096);
__COHERENT_RAM_END__ = .;
} >RAM
__BL2_DATA_STOP__ = .;
__BL2_END__ = .;
__BL2_RO_BASE__ = LOADADDR(BL2_RO);
__BL2_RO_SIZE__ = SIZEOF(BL2_RO);
__BL2_STACKS_BASE__ = LOADADDR(BL2_STACKS);
__BL2_STACKS_SIZE__ = SIZEOF(BL2_STACKS);
__BL2_COHERENT_RAM_BASE__ = LOADADDR(BL2_COHERENT_RAM);
__BL2_COHERENT_RAM_SIZE__ = SIZEOF(BL2_COHERENT_RAM);
__BL2_RW_BASE__ = __BL2_DATA_START__;
__BL2_RW_SIZE__ = __BL2_DATA_STOP__ - __BL2_DATA_START__;
__BSS_SIZE__ = SIZEOF(.bss);
__COHERENT_RAM_UNALIGNED_SIZE__ =
__COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
}

2
bl31/aarch64/bl31_entrypoint.S
View File

@ -37,7 +37,7 @@
.globl bl31_entrypoint
.section entry_code, "ax"; .align 3
.section .text, "ax"; .align 3
/* -----------------------------------------------------
* bl31_entrypoint() is the cold boot entrypoint,

2
bl31/aarch64/runtime_exceptions.S
View File

@ -37,7 +37,7 @@
#include <asm_macros.S>
.section aarch64_code, "ax"; .align 11
.section .text, "ax"; .align 11
.align 7
runtime_exceptions:

82
bl31/bl31.ld.S
View File

@ -35,54 +35,78 @@ OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
MEMORY {
/* RAM is read/write and Initialised */
RAM (rwx): ORIGIN = TZRAM_BASE, LENGTH = TZRAM_SIZE
}
SECTIONS
{
. = BL31_BASE;
. = BL31_BASE;
ASSERT(. == ALIGN(4096),
"BL31_BASE address is not aligned on a page boundary.")
BL31_RO ALIGN (4096): {
*(entry_code)
ro . : {
__RO_START__ = .;
*bl31_entrypoint.o(.text)
*(.text)
*(.rodata)
*(.rodata*)
__RO_END_UNALIGNED__ = .;
/*
* Memory page(s) mapped to this section will be marked as read-only,
* executable. No RW data from the next section must creep in.
* Ensure the rest of the current memory page is unused.
*/
. = NEXT(4096);
__RO_END__ = .;
} >RAM
BL31_STACKS ALIGN (4096): {
. += 0x1000;
.data . : {
__DATA_START__ = .;
*(.data)
__DATA_END__ = .;
} >RAM
stacks (NOLOAD) : {
__STACKS_START__ = .;
*(tzfw_normal_stacks)
__STACKS_END__ = .;
} >RAM
BL31_COHERENT_RAM ALIGN (4096): {
*(tzfw_coherent_mem)
/* . += 0x1000;*/
/* Do we need to ensure at least 4k here? */
. = ALIGN(4096);
} >RAM
__BL31_DATA_START__ = .;
.bss ALIGN (4096): {
/*
* The .bss section gets initialised to 0 at runtime.
* Its base address must be 16-byte aligned.
*/
.bss : ALIGN(16) {
__BSS_START__ = .;
*(.bss)
*(COMMON)
__BSS_END__ = .;
} >RAM
.data : {
*(.data)
/*
* The base address of the coherent memory section must be page-aligned (4K)
* to guarantee that the coherent data are stored on their own pages and
* are not mixed with normal data. This is required to set up the correct
* memory attributes for the coherent data page tables.
*/
coherent_ram (NOLOAD) : ALIGN(4096) {
__COHERENT_RAM_START__ = .;
*(tzfw_coherent_mem)
__COHERENT_RAM_END_UNALIGNED__ = .;
/*
* Memory page(s) mapped to this section will be marked
* as device memory. No other unexpected data must creep in.
* Ensure the rest of the current memory page is unused.
*/
. = NEXT(4096);
__COHERENT_RAM_END__ = .;
} >RAM
__BL31_DATA_STOP__ = .;
__BL31_END__ = .;
__BL31_RO_BASE__ = LOADADDR(BL31_RO);
__BL31_RO_SIZE__ = SIZEOF(BL31_RO);
__BSS_SIZE__ = SIZEOF(.bss);
__COHERENT_RAM_UNALIGNED_SIZE__ =
__COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
__BL31_STACKS_BASE__ = LOADADDR(BL31_STACKS);
__BL31_STACKS_SIZE__ = SIZEOF(BL31_STACKS);
__BL31_COHERENT_RAM_BASE__ = LOADADDR(BL31_COHERENT_RAM);
__BL31_COHERENT_RAM_SIZE__ = SIZEOF(BL31_COHERENT_RAM);
__BL31_RW_BASE__ = __BL31_DATA_START__;
__BL31_RW_SIZE__ = __BL31_DATA_STOP__ - __BL31_DATA_START__;
ASSERT(. <= BL2_BASE, "BL31 image overlaps BL2 image.")
}

2
common/psci/psci_entry.S
View File

@ -39,7 +39,7 @@
.globl __psci_cpu_off
.globl __psci_cpu_suspend
.section platform_code, "ax"; .align 3
.section .text, "ax"; .align 3
/* -----------------------------------------------------
* This cpu has been physically powered up. Depending

2
include/aarch64/arch.h
View File

@ -248,6 +248,8 @@
#define OSH (0x2 << 6)
#define ISH (0x3 << 6)
#define IS_PAGE_ALIGNED(addr) (((addr) & 0xFFF) == 0)
/*
* AP[1] bit is ignored by hardware and is
* treated as if it is One in EL2/EL3

2
plat/fvp/aarch64/bl1_plat_helpers.S
View File

@ -38,7 +38,7 @@
.globl plat_secondary_cold_boot_setup
.section platform_code, "ax"; .align 3
.section .text, "ax"; .align 3
.macro platform_choose_gicmmap param1, param2, x_tmp, w_tmp, res

19
plat/fvp/aarch64/fvp_common.c
View File

@ -367,8 +367,6 @@ static unsigned long fill_xlation_tables(meminfo *tzram_layout,
/*****************************************************************
* LEVEL3 PAGETABLE SETUP
* The following setup assumes knowledge of the scatter file. This
* should be reasonable as this is platform specific code.
*****************************************************************/
/* Fill up the level3 pagetable for the trusted SRAM. */
@ -378,21 +376,13 @@ static unsigned long fill_xlation_tables(meminfo *tzram_layout,
if (tzram_end_index == tzram_start_index)
tzram_end_index++;
/*
* Reusing trom* to mark RO memory. BLX_STACKS follows BLX_RO in the
* scatter file. Using BLX_RO$$Limit does not work as it might not
* cross the page boundary thus leading to truncation of valid RO
* memory
*/
/* Reusing trom* to mark RO memory. */
trom_start_index = FOUR_KB_INDEX(ro_start);
trom_end_index = FOUR_KB_INDEX(ro_limit);
if (trom_end_index == trom_start_index)
trom_end_index++;
/*
* Reusing dev* to mark coherent device memory. $$Limit works here
* 'cause the coherent memory section is known to be 4k in size
*/
/* Reusing dev* to mark coherent device memory. */
dev0_start_index = FOUR_KB_INDEX(coh_start);
dev0_end_index = FOUR_KB_INDEX(coh_limit);
if (dev0_end_index == dev0_start_index)
@ -506,6 +496,11 @@ void configure_mmu(meminfo *mem_layout,
unsigned long coh_start,
unsigned long coh_limit)
{
assert(IS_PAGE_ALIGNED(ro_start));
assert(IS_PAGE_ALIGNED(ro_limit));
assert(IS_PAGE_ALIGNED(coh_start));
assert(IS_PAGE_ALIGNED(coh_limit));
fill_xlation_tables(mem_layout,
ro_start,
ro_limit,

2
plat/fvp/aarch64/fvp_helpers.S
View File

@ -33,7 +33,7 @@
.globl plat_report_exception
.section platform_code, "ax"
.section .text, "ax"
/* ---------------------------------------------
* void plat_report_exception(unsigned int type)

95
plat/fvp/bl1_plat_setup.c
View File

@ -40,46 +40,27 @@
* Declarations of linker defined symbols which will help us find the layout
* of trusted SRAM
******************************************************************************/
#if defined (__GNUC__)
extern unsigned long __FIRMWARE_ROM_START__;
extern unsigned long __FIRMWARE_ROM_SIZE__;
extern unsigned long __FIRMWARE_DATA_START__;
extern unsigned long __FIRMWARE_DATA_SIZE__;
extern unsigned long __FIRMWARE_BSS_START__;
extern unsigned long __FIRMWARE_BSS_SIZE__;
extern unsigned long __DATA_RAM_START__;
extern unsigned long __DATA_RAM_SIZE__;
extern unsigned long __BSS_RAM_START__;
extern unsigned long __BSS_RAM_SIZE__;
extern unsigned long __FIRMWARE_RAM_STACKS_START__;
extern unsigned long __FIRMWARE_RAM_STACKS_SIZE__;
extern unsigned long __FIRMWARE_RAM_PAGETABLES_START__;
extern unsigned long __FIRMWARE_RAM_PAGETABLES_SIZE__;
extern unsigned long __FIRMWARE_RAM_COHERENT_START__;
extern unsigned long __FIRMWARE_RAM_COHERENT_SIZE__;
extern unsigned long __COHERENT_RAM_START__;
extern unsigned long __COHERENT_RAM_END__;
extern unsigned long __COHERENT_RAM_UNALIGNED_SIZE__;
#define BL1_COHERENT_MEM_BASE (&__FIRMWARE_RAM_COHERENT_START__)
#define BL1_COHERENT_MEM_LIMIT \
((unsigned long long)&__FIRMWARE_RAM_COHERENT_START__ + \
(unsigned long long)&__FIRMWARE_RAM_COHERENT_SIZE__)
extern unsigned long __BL1_RAM_START__;
extern unsigned long __BL1_RAM_END__;
#define BL1_FIRMWARE_RAM_GLOBALS_ZI_BASE \
(unsigned long)(&__BSS_RAM_START__)
#define BL1_FIRMWARE_RAM_GLOBALS_ZI_LENGTH \
(unsigned long)(&__FIRMWARE_BSS_SIZE__)
/*
* The next 2 constants identify the extents of the coherent memory region.
* These addresses are used by the MMU setup code and therefore they must be
* page-aligned. It is the responsibility of the linker script to ensure that
* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
* page-aligned addresses.
*/
#define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
#define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
#define BL1_COHERENT_RAM_LENGTH \
(unsigned long)(&__COHERENT_RAM_UNALIGNED_SIZE__)
#define BL1_FIRMWARE_RAM_COHERENT_ZI_BASE \
(unsigned long)(&__FIRMWARE_RAM_COHERENT_START__)
#define BL1_FIRMWARE_RAM_COHERENT_ZI_LENGTH\
(unsigned long)(&__FIRMWARE_RAM_COHERENT_SIZE__)
#define BL1_NORMAL_RAM_BASE (unsigned long)(&__BSS_RAM_START__)
#define BL1_NORMAL_RAM_LIMIT \
((unsigned long)&__FIRMWARE_RAM_COHERENT_START__ + \
(unsigned long)&__FIRMWARE_RAM_COHERENT_SIZE__)
#else
#error "Unknown compiler."
#endif
#define BL1_RAM_BASE (unsigned long)(&__BL1_RAM_START__)
#define BL1_RAM_LIMIT (unsigned long)(&__BL1_RAM_END__)
/* Data structure which holds the extents of the trusted SRAM for BL1*/
@ -95,16 +76,9 @@ meminfo bl1_get_sec_mem_layout(void)
******************************************************************************/
void bl1_early_platform_setup(void)
{
unsigned long bl1_normal_ram_base;
unsigned long bl1_coherent_ram_limit;
unsigned long tzram_limit = TZRAM_BASE + TZRAM_SIZE;
/*
* Initialize extents of the bl1 sections as per the platform
* defined values.
*/
bl1_normal_ram_base = BL1_NORMAL_RAM_BASE;
bl1_coherent_ram_limit = BL1_NORMAL_RAM_LIMIT;
const unsigned long bl1_ram_base = BL1_RAM_BASE;
const unsigned long bl1_ram_limit = BL1_RAM_LIMIT;
const unsigned long tzram_limit = TZRAM_BASE + TZRAM_SIZE;
/*
* Calculate how much ram is BL1 using & how much remains free.
@ -113,19 +87,19 @@ void bl1_early_platform_setup(void)
* TODO: add support for discontigous chunks of free ram if
* needed. Might need dynamic memory allocation support
* et al.
* Also assuming that the section for coherent memory is
* the last and for globals the first in the scatter file.
*/
bl1_tzram_layout.total_base = TZRAM_BASE;
bl1_tzram_layout.total_size = TZRAM_SIZE;
if (bl1_coherent_ram_limit == tzram_limit) {
if (bl1_ram_limit == tzram_limit) {
/* BL1 has been loaded at the top of memory. */
bl1_tzram_layout.free_base = TZRAM_BASE;
bl1_tzram_layout.free_size = bl1_normal_ram_base - TZRAM_BASE;
bl1_tzram_layout.free_size = bl1_ram_base - TZRAM_BASE;
} else {
bl1_tzram_layout.free_base = bl1_coherent_ram_limit;
/* BL1 has been loaded at the bottom of memory. */
bl1_tzram_layout.free_base = bl1_ram_limit;
bl1_tzram_layout.free_size =
tzram_limit - bl1_coherent_ram_limit;
tzram_limit - bl1_ram_limit;
}
/* Initialize the platform config for future decision making */
@ -143,8 +117,8 @@ void bl1_platform_setup(void)
* This should zero out our coherent stacks as well but we don't care
* as they are not being used right now.
*/
memset((void *) BL1_FIRMWARE_RAM_COHERENT_ZI_BASE, 0,
(size_t) BL1_FIRMWARE_RAM_COHERENT_ZI_LENGTH);
memset((void *) BL1_COHERENT_RAM_BASE, 0,
(size_t) BL1_COHERENT_RAM_LENGTH);
/* Enable and initialize the System level generic timer */
mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF, CNTCR_EN);
@ -175,11 +149,8 @@ void bl1_plat_arch_setup(void)
}
configure_mmu(&bl1_tzram_layout,
TZROM_BASE, /* Read_only region start */
TZROM_BASE + TZROM_SIZE, /* Read_only region size */
/* Coherent region start */
BL1_FIRMWARE_RAM_COHERENT_ZI_BASE,
/* Coherent region size */
BL1_FIRMWARE_RAM_COHERENT_ZI_BASE +
BL1_FIRMWARE_RAM_COHERENT_ZI_LENGTH);
TZROM_BASE,
TZROM_BASE + TZROM_SIZE,
BL1_COHERENT_RAM_BASE,
BL1_COHERENT_RAM_LIMIT);
}

42
plat/fvp/bl2_plat_setup.c
View File

@ -39,20 +39,30 @@
* Declarations of linker defined symbols which will help us find the layout
* of trusted SRAM
******************************************************************************/
#if defined (__GNUC__)
extern unsigned long __BL2_RO_BASE__;
extern unsigned long __BL2_STACKS_BASE__;
extern unsigned long __BL2_COHERENT_RAM_BASE__;
extern unsigned long __BL2_RW_BASE__;
extern unsigned long __RO_START__;
extern unsigned long __RO_END__;
#define BL2_RO_BASE __BL2_RO_BASE__
#define BL2_STACKS_BASE __BL2_STACKS_BASE__
#define BL2_COHERENT_RAM_BASE __BL2_COHERENT_RAM_BASE__
#define BL2_RW_BASE __BL2_RW_BASE__
extern unsigned long __COHERENT_RAM_START__;
extern unsigned long __COHERENT_RAM_END__;
#else
#error "Unknown compiler."
#endif
/*
* The next 2 constants identify the extents of the code & RO data region.
* These addresses are used by the MMU setup code and therefore they must be
* page-aligned. It is the responsibility of the linker script to ensure that
* __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
*/
#define BL2_RO_BASE (unsigned long)(&__RO_START__)
#define BL2_RO_LIMIT (unsigned long)(&__RO_END__)
/*
* The next 2 constants identify the extents of the coherent memory region.
* These addresses are used by the MMU setup code and therefore they must be
* page-aligned. It is the responsibility of the linker script to ensure that
* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
* page-aligned addresses.
*/
#define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
#define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
/* Pointer to memory visible to both BL2 and BL31 for passing data */
extern unsigned char **bl2_el_change_mem_ptr;
@ -106,8 +116,8 @@ void bl2_platform_setup()
void bl2_plat_arch_setup()
{
configure_mmu(&bl2_tzram_layout,
(unsigned long) &BL2_RO_BASE,
(unsigned long) &BL2_STACKS_BASE,
(unsigned long) &BL2_COHERENT_RAM_BASE,
(unsigned long) &BL2_RW_BASE);
BL2_RO_BASE,
BL2_RO_LIMIT,
BL2_COHERENT_RAM_BASE,
BL2_COHERENT_RAM_LIMIT);
}

42
plat/fvp/bl31_plat_setup.c
View File

@ -44,20 +44,30 @@
* Declarations of linker defined symbols which will help us find the layout
* of trusted SRAM
******************************************************************************/
#if defined (__GNUC__)
extern unsigned long __BL31_RO_BASE__;
extern unsigned long __BL31_STACKS_BASE__;
extern unsigned long __BL31_COHERENT_RAM_BASE__;
extern unsigned long __BL31_RW_BASE__;
extern unsigned long __RO_START__;
extern unsigned long __RO_END__;
#define BL31_RO_BASE __BL31_RO_BASE__
#define BL31_STACKS_BASE __BL31_STACKS_BASE__
#define BL31_COHERENT_RAM_BASE __BL31_COHERENT_RAM_BASE__
#define BL31_RW_BASE __BL31_RW_BASE__
extern unsigned long __COHERENT_RAM_START__;
extern unsigned long __COHERENT_RAM_END__;
#else
#error "Unknown compiler."
#endif
/*
* The next 2 constants identify the extents of the code & RO data region.
* These addresses are used by the MMU setup code and therefore they must be
* page-aligned. It is the responsibility of the linker script to ensure that
* __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
*/
#define BL31_RO_BASE (unsigned long)(&__RO_START__)
#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
/*
* The next 2 constants identify the extents of the coherent memory region.
* These addresses are used by the MMU setup code and therefore they must be
* page-aligned. It is the responsibility of the linker script to ensure that
* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
* refer to page-aligned addresses.
*/
#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
/*******************************************************************************
* This data structures holds information copied by BL31 from BL2 to pass
@ -167,10 +177,10 @@ void bl31_platform_setup()
void bl31_plat_arch_setup()
{
configure_mmu(&bl31_tzram_layout,
(unsigned long) &BL31_RO_BASE,
(unsigned long) &BL31_STACKS_BASE,
(unsigned long) &BL31_COHERENT_RAM_BASE,
(unsigned long) &BL31_RW_BASE);
BL31_RO_BASE,
BL31_RO_LIMIT,
BL31_COHERENT_RAM_BASE,
BL31_COHERENT_RAM_LIMIT);
}
/*******************************************************************************