From 8e140272fbd4ea00d1a9d86dced18ce6eb3a9981 Mon Sep 17 00:00:00 2001 From: nayanpatel-arm Date: Tue, 28 Sep 2021 13:41:03 -0700 Subject: [PATCH] errata: workaround for Neoverse-V1 erratum 2108267 Neoverse-V1 erratum 2108267 is a Cat B erratum that applies to revisions r0p0, r1p0, and r1p1 of CPU. It is still open. The workaround is to write the value 2'b11 to the PF_MODE bits in the CPUECTLR_EL1 register which will place the data prefetcher in the most conservative mode instead of disabling it. SDEN can be found here: https://developer.arm.com/documentation/SDEN1401781/latest Signed-off-by: nayanpatel-arm Change-Id: Iedcb84a7ad34af7083116818f49d7296f7d9bf94 --- docs/design/cpu-specific-build-macros.rst | 4 +++ include/lib/cpus/aarch64/neoverse_v1.h | 3 ++ lib/cpus/aarch64/neoverse_v1.S | 35 +++++++++++++++++++++++ lib/cpus/cpu-ops.mk | 12 ++++++-- 4 files changed, 52 insertions(+), 2 deletions(-) diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 9676ae787..944228ce1 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -371,6 +371,10 @@ For Neoverse V1, the following errata build flags are defined : CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU. It is still open. +- ``ERRATA_V1_2108267``: This applies errata 2108267 workaround to Neoverse-V1 + CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU. + It is still open. + For Cortex-A710, the following errata build flags are defined : - ``ERRATA_A710_1987031``: This applies errata 1987031 workaround to diff --git a/include/lib/cpus/aarch64/neoverse_v1.h b/include/lib/cpus/aarch64/neoverse_v1.h index cfb26ab61..e43c90798 100644 --- a/include/lib/cpus/aarch64/neoverse_v1.h +++ b/include/lib/cpus/aarch64/neoverse_v1.h @@ -15,6 +15,9 @@ #define NEOVERSE_V1_CPUECTLR_EL1 S3_0_C15_C1_4 #define NEOVERSE_V1_CPUECTLR_EL1_BIT_8 (ULL(1) << 8) #define NEOVERSE_V1_CPUECTLR_EL1_BIT_53 (ULL(1) << 53) +#define NEOVERSE_V1_CPUECTLR_EL1_PF_MODE_CNSRV ULL(3) +#define CPUECTLR_EL1_PF_MODE_LSB U(6) +#define CPUECTLR_EL1_PF_MODE_WIDTH U(2) /******************************************************************************* * CPU Power Control register specific definitions diff --git a/lib/cpus/aarch64/neoverse_v1.S b/lib/cpus/aarch64/neoverse_v1.S index 0bcf52a78..200f67de3 100644 --- a/lib/cpus/aarch64/neoverse_v1.S +++ b/lib/cpus/aarch64/neoverse_v1.S @@ -259,6 +259,35 @@ func check_errata_2139242 b cpu_rev_var_ls endfunc check_errata_2139242 + /* -------------------------------------------------- + * Errata Workaround for Neoverse V1 Errata #2108267. + * This applies to revisions r0p0, r1p0, and r1p1, it + * is still open. + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x1, x17 + * -------------------------------------------------- + */ +func errata_neoverse_v1_2108267_wa + /* Check workaround compatibility. */ + mov x17, x30 + bl check_errata_2108267 + cbz x0, 1f + + /* Apply the workaround. */ + mrs x1, NEOVERSE_V1_CPUECTLR_EL1 + mov x0, #NEOVERSE_V1_CPUECTLR_EL1_PF_MODE_CNSRV + bfi x1, x0, #CPUECTLR_EL1_PF_MODE_LSB, #CPUECTLR_EL1_PF_MODE_WIDTH + msr NEOVERSE_V1_CPUECTLR_EL1, x1 +1: + ret x17 +endfunc errata_neoverse_v1_2108267_wa + +func check_errata_2108267 + /* Applies to r0p0, r1p0, r1p1 */ + mov x1, #0x11 + b cpu_rev_var_ls +endfunc check_errata_2108267 + /* --------------------------------------------- * HW will do the cache maintenance while powering down * --------------------------------------------- @@ -296,6 +325,7 @@ func neoverse_v1_errata_report report_errata ERRATA_V1_1940577, neoverse_v1, 1940577 report_errata ERRATA_V1_1966096, neoverse_v1, 1966096 report_errata ERRATA_V1_2139242, neoverse_v1, 2139242 + report_errata ERRATA_V1_2108267, neoverse_v1, 2108267 ldp x8, x30, [sp], #16 ret @@ -344,6 +374,11 @@ func neoverse_v1_reset_func bl errata_neoverse_v1_2139242_wa #endif +#if ERRATA_V1_2108267 + mov x0, x18 + bl errata_neoverse_v1_2108267_wa +#endif + ret x19 endfunc neoverse_v1_reset_func diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 1d470e20b..9b2d5464d 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -411,11 +411,15 @@ ERRATA_V1_1940577 ?=0 # Flag to apply erratum 1966096 workaround during reset. This erratum applies # to revisions r1p0 and r1p1 of the Neoverse V1 CPU and is open. This issue # exists in r0p0 as well but there is no workaround for that revision. -ERRATA_V1_1966096 ?=0 +ERRATA_V1_1966096 ?=0 # Flag to apply erratum 2139242 workaround during reset. This erratum applies # to revisions r0p0, r1p0, and r1p1 of the Neoverse V1 cpu and is still open. -ERRATA_V1_2139242 ?=0 +ERRATA_V1_2139242 ?=0 + +# Flag to apply erratum 2108267 workaround during reset. This erratum applies +# to revisions r0p0, r1p0, and r1p1 of the Neoverse V1 cpu and is still open. +ERRATA_V1_2108267 ?=0 # Flag to apply erratum 1987031 workaround during reset. This erratum applies # to revisions r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is still open. @@ -802,6 +806,10 @@ $(eval $(call add_define,ERRATA_V1_1966096)) $(eval $(call assert_boolean,ERRATA_V1_2139242)) $(eval $(call add_define,ERRATA_V1_2139242)) +# Process ERRATA_V1_2108267 flag +$(eval $(call assert_boolean,ERRATA_V1_2108267)) +$(eval $(call add_define,ERRATA_V1_2108267)) + # Process ERRATA_A710_1987031 flag $(eval $(call assert_boolean,ERRATA_A710_1987031)) $(eval $(call add_define,ERRATA_A710_1987031))