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drivers: arm: gicv3: auto-detect presence of GIC600-AE 

This patch adds the IIDR value for GIC600-AE to the gicv3_is_gic600()
helper function. This helps platforms supporting this version of the
GIC600 interrupt controller to function with the generic GIC driver.

Verified with tftf-validation test suite

******************************* Summary *******************************
> Test suite 'Framework Validation'
                                                                Passed
> Test suite 'Timer framework Validation'
                                                                Passed
=================================
Tests Skipped : 0
Tests Passed  : 6
Tests Failed  : 0
Tests Crashed : 0
Total tests   : 6
=================================
NOTICE:  Exiting tests.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I518ae7b56f7f372e374e453287d76ca370fc3574
This commit is contained in:
Varun Wadekar 2020-07-05 13:12:28 -07:00
parent 2634ef6d79
commit 8e570b71d8
1 changed files with 16 additions and 13 deletions
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29
drivers/arm/gic/v3/gic-x00.c
View File

@ -1,5 +1,6 @@
/*
* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -20,26 +21,27 @@
#include "gicv3_private.h"
/* GIC-600 specific register offsets */
#define GICR_PWRR 0x24
#define IIDR_MODEL_ARM_GIC_600 0x0200043b
#define GICR_PWRR 0x24
#define IIDR_MODEL_ARM_GIC_600 (0x0200043b)
#define IIDR_MODEL_ARM_GIC_600AE (0x0300043b)
/* GICR_PWRR fields */
#define PWRR_RDPD_SHIFT 0
#define PWRR_RDAG_SHIFT 1
#define PWRR_RDGPD_SHIFT 2
#define PWRR_RDGPO_SHIFT 3
#define PWRR_RDPD_SHIFT 0
#define PWRR_RDAG_SHIFT 1
#define PWRR_RDGPD_SHIFT 2
#define PWRR_RDGPO_SHIFT 3
#define PWRR_RDPD (1 << PWRR_RDPD_SHIFT)
#define PWRR_RDAG (1 << PWRR_RDAG_SHIFT)
#define PWRR_RDGPD (1 << PWRR_RDGPD_SHIFT)
#define PWRR_RDGPO (1 << PWRR_RDGPO_SHIFT)
#define PWRR_RDPD (1 << PWRR_RDPD_SHIFT)
#define PWRR_RDAG (1 << PWRR_RDAG_SHIFT)
#define PWRR_RDGPD (1 << PWRR_RDGPD_SHIFT)
#define PWRR_RDGPO (1 << PWRR_RDGPO_SHIFT)
/*
* Values to write to GICR_PWRR register to power redistributor
* for operating through the core (GICR_PWRR.RDAG = 0)
*/
#define PWRR_ON (0 << PWRR_RDPD_SHIFT)
#define PWRR_OFF (1 << PWRR_RDPD_SHIFT)
#define PWRR_ON (0 << PWRR_RDPD_SHIFT)
#define PWRR_OFF (1 << PWRR_RDPD_SHIFT)
#if GICV3_SUPPORT_GIC600
@ -115,7 +117,8 @@ static bool gicv3_is_gic600(uintptr_t gicr_base)
{
uint32_t reg = mmio_read_32(gicr_base + GICR_IIDR);
return (reg & IIDR_MODEL_MASK) == IIDR_MODEL_ARM_GIC_600;
return (((reg & IIDR_MODEL_MASK) == IIDR_MODEL_ARM_GIC_600) ||
((reg & IIDR_MODEL_MASK) == IIDR_MODEL_ARM_GIC_600AE));
}
#endif