marvell: comphy: update rx_training procedure
1) Relay only on rx training, remove parts responsible for tx training (trx training). 2) Add extra steps e.g. preconfigure FFE before starting training. 3) Remove some unnecessary steps like RRBS31 loopback setting which shouldn't be relevant for tx_training. Change-Id: Ib1e8567714f9ce33578186a262c339aa4b1c51f2 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
This commit is contained in:
Grzegorz Jaszczyk
Marcin Wojtas
parent
ed84fe8829
commit
8e8ec8cff7
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@ -659,18 +659,32 @@
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(0x3f << HPIPE_SAVED_DFE_VALUES_SAV_F0D_OFFSET)
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#define HPIPE_CDR_CONTROL_REG 0x418
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#define HPIPE_CDR_RX_MAX_DFE_ADAPT_0_OFFSET 14
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#define HPIPE_CDR_RX_MAX_DFE_ADAPT_0_MASK \
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(0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_0_OFFSET)
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#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET 12
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#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK \
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(0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET)
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#define HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET 9
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#define HPIPE_CDR_MAX_DFE_ADAPT_0_MASK \
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(0x7 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET)
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#define HPIPE_CRD_MIDPOINT_PHASE_OS_OFFSET 0
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#define HPIPE_CRD_MIDPOINT_PHASE_OS_MASK \
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(0x3f << HPIPE_CRD_MIDPOINT_PHASE_OS_OFFSET)
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#define HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET 6
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#define HPIPE_CDR_MAX_DFE_ADAPT_1_MASK \
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(0x7 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET)
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#define HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET 9
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#define HPIPE_CDR_MAX_DFE_ADAPT_0_MASK \
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(0x7 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET)
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#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET 12
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#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK \
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(0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET)
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#define HPIPE_CDR_RX_MAX_DFE_ADAPT_0_OFFSET 14
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#define HPIPE_CDR_RX_MAX_DFE_ADAPT_0_MASK \
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(0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_0_OFFSET)
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#define HPIPE_CDR_CONTROL1_REG 0x41c
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#define HPIPE_CRD2_CRD_MIDPOINT_SMALL_THRES_K_OFF 12
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#define HPIPE_CRD2_CRD_MIDPOINT_SMALL_THRES_K_MASK \
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(0xf << HPIPE_CRD2_CRD_MIDPOINT_SMALL_THRES_K_OFF)
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#define HPIPE_CDR_CONTROL2_REG 0x420
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#define HPIPE_CRD2_CRD_MIDPOINT_LARGE_THRES_K_OFF 12
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#define HPIPE_CRD2_CRD_MIDPOINT_LARGE_THRES_K_MASK \
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(0xf << HPIPE_CRD2_CRD_MIDPOINT_LARGE_THRES_K_OFF)
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#define HPIPE_TX_TRAIN_CTRL_11_REG 0x438
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#define HPIPE_TX_STATUS_CHECK_MODE_OFFSET 6
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@ -749,6 +763,30 @@
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#define HPIPE_DFE_CTRL_28_PIPE4_MASK \
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(0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET)
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#define HPIPE_TRX0_REG 0x4cc /*in doc 0x133*4*/
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#define HPIPE_TRX0_GAIN_TRAIN_WITH_SAMPLER_OFF 2
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#define HPIPE_TRX0_GAIN_TRAIN_WITH_SAMPLER_MASK \
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(0x1 << HPIPE_TRX0_GAIN_TRAIN_WITH_SAMPLER_OFF)
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#define HPIPE_TRX0_GAIN_TRAIN_WITH_C_OFF 0
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#define HPIPE_TRX0_GAIN_TRAIN_WITH_C_MASK \
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(0x1 << HPIPE_TRX0_GAIN_TRAIN_WITH_C_OFF)
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#define HPIPE_TRX_REG1 0x4d0 /*in doc 0x134*4*/
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#define HPIPE_TRX_REG1_MIN_BOOST_MODE_OFF 3
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#define HPIPE_TRX_REG1_MIN_BOOST_MODE_MASK \
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(0x1 << HPIPE_TRX_REG1_MIN_BOOST_MODE_OFF)
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#define HPIPE_TRX_REG1_SUMFTAP_EN_OFF 10
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#define HPIPE_TRX_REG1_SUMFTAP_EN_MASK \
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(0x3f << HPIPE_TRX_REG1_SUMFTAP_EN_OFF)
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#define HPIPE_TRX_REG2 0x4d8 /*in doc 0x136*4*/
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#define HPIPE_TRX_REG2_SUMF_BOOST_TARGET_C_OFF 11
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#define HPIPE_TRX_REG2_SUMF_BOOST_TARGET_C_MASK \
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(0x1f << HPIPE_TRX_REG2_SUMF_BOOST_TARGET_C_OFF)
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#define HPIPE_TRX_REG2_SUMF_BOOST_TARGET_K_OFF 7
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#define HPIPE_TRX_REG2_SUMF_BOOST_TARGET_K_MASK \
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(0xf << HPIPE_TRX_REG2_SUMF_BOOST_TARGET_K_OFF)
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#define HPIPE_G1_SETTING_5_REG 0x538
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#define HPIPE_G1_SETTING_5_G1_ICP_OFFSET 0
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#define HPIPE_G1_SETTING_5_G1_ICP_MASK \
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@ -2012,12 +2012,58 @@ static int mvebu_cp110_comphy_usb3_power_on(uint64_t comphy_base,
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return ret;
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}
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static void rx_pre_train(uint64_t comphy_base, uint8_t comphy_index)
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{
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uintptr_t hpipe_addr;
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uint32_t mask, data;
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hpipe_addr = HPIPE_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base),
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comphy_index);
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debug("rx_training preparation\n\n");
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mask = HPIPE_TRX0_GAIN_TRAIN_WITH_C_MASK;
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data = (0x1 << HPIPE_TRX0_GAIN_TRAIN_WITH_C_OFF);
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mask |= HPIPE_TRX0_GAIN_TRAIN_WITH_SAMPLER_MASK;
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data |= (0x0 << HPIPE_TRX0_GAIN_TRAIN_WITH_SAMPLER_OFF);
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reg_set(hpipe_addr + HPIPE_TRX0_REG, data, mask);
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mask = HPIPE_TRX_REG2_SUMF_BOOST_TARGET_C_MASK;
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data = (0x1e << HPIPE_TRX_REG2_SUMF_BOOST_TARGET_C_OFF);
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mask |= HPIPE_TRX_REG2_SUMF_BOOST_TARGET_K_MASK;
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data |= (0x0 << HPIPE_TRX_REG2_SUMF_BOOST_TARGET_K_OFF);
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reg_set(hpipe_addr + HPIPE_TRX_REG2, data, mask);
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mask = HPIPE_TRX_REG1_MIN_BOOST_MODE_MASK;
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data = (0x1 << HPIPE_TRX_REG1_MIN_BOOST_MODE_OFF);
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reg_set(hpipe_addr + HPIPE_TRX_REG1, data, mask);
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mask = HPIPE_CRD2_CRD_MIDPOINT_SMALL_THRES_K_MASK;
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data = (0x8 << HPIPE_CRD2_CRD_MIDPOINT_SMALL_THRES_K_OFF);
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reg_set(hpipe_addr + HPIPE_CDR_CONTROL1_REG, data, mask);
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mask = HPIPE_CRD2_CRD_MIDPOINT_LARGE_THRES_K_MASK;
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data = (0x8 << HPIPE_CRD2_CRD_MIDPOINT_LARGE_THRES_K_OFF);
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reg_set(hpipe_addr + HPIPE_CDR_CONTROL2_REG, data, mask);
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mask = HPIPE_CRD_MIDPOINT_PHASE_OS_MASK;
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data = (0x0 << HPIPE_CRD_MIDPOINT_PHASE_OS_OFFSET);
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reg_set(hpipe_addr + HPIPE_CDR_CONTROL_REG, data, mask);
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mask = HPIPE_TRX_REG1_SUMFTAP_EN_MASK;
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data = (0x38 << HPIPE_TRX_REG1_SUMFTAP_EN_OFF);
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mask |= HPIPE_TRX_REG2_SUMF_BOOST_TARGET_C_MASK;
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data |= (0x1e << HPIPE_TRX_REG2_SUMF_BOOST_TARGET_C_OFF);
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reg_set(hpipe_addr + HPIPE_TRX_REG1, data, mask);
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}
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int mvebu_cp110_comphy_xfi_rx_training(uint64_t comphy_base,
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uint8_t comphy_index)
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{
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uint32_t mask, data, timeout;
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uint32_t g1_ffe_cap_sel, g1_ffe_res_sel, align90, g1_dfe_res;
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uintptr_t hpipe_addr, sd_ip_addr;
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uintptr_t hpipe_addr;
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uint8_t ap_nr, cp_nr;
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@ -2025,30 +2071,10 @@ int mvebu_cp110_comphy_xfi_rx_training(uint64_t comphy_base,
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hpipe_addr = HPIPE_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base),
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comphy_index);
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sd_ip_addr = SD_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base),
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comphy_index);
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debug_enter();
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debug("stage: RF Reset\n");
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/* Release from hard reset */
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mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
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data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
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mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
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data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
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mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
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data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
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reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
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mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
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data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
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mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
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data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
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reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
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/* Wait 50ms - until band gap and ref clock ready */
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mdelay(50);
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rx_pre_train(comphy_base, comphy_index);
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debug("Preparation for rx_training\n\n");
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@ -2068,34 +2094,10 @@ int mvebu_cp110_comphy_xfi_rx_training(uint64_t comphy_base,
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data = 0 << HPIPE_DFE_RES_FORCE_OFFSET;
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reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);
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debug("PRBS31 loppback\n\n");
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/* Configure PRBS counters */
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mask = HPIPE_PHY_TEST_PATTERN_SEL_MASK;
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data = 0xe << HPIPE_PHY_TEST_PATTERN_SEL_OFFSET;
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reg_set(hpipe_addr + HPIPE_PHY_TEST_CONTROL_REG, data, mask);
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mask = HPIPE_PHY_TEST_DATA_MASK;
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data = 0xc4 << HPIPE_PHY_TEST_DATA_OFFSET;
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reg_set(hpipe_addr + HPIPE_PHY_TEST_DATA_REG, data, mask);
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mask = HPIPE_PHY_TEST_EN_MASK;
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data = 0x1 << HPIPE_PHY_TEST_EN_OFFSET;
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reg_set(hpipe_addr + HPIPE_PHY_TEST_CONTROL_REG, data, mask);
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mdelay(10);
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debug("Enable TX/RX training\n\n");
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debug("Enable RX training\n\n");
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mask = HPIPE_TRX_RX_TRAIN_EN_MASK;
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data = 0x1 << HPIPE_TRX_RX_TRAIN_EN_OFFSET;
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mask |= HPIPE_TRX_RX_ANA_IF_CLK_ENE_MASK;
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data |= 0x1 << HPIPE_TRX_RX_ANA_IF_CLK_ENE_OFFSET;
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mask |= HPIPE_TRX_TX_CTRL_CLK_EN_MASK;
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data |= 0x1 << HPIPE_TRX_TX_CTRL_CLK_EN_OFFSET;
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mask |= HPIPE_TRX_UPDATE_THEN_HOLD_MASK;
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data |= 0x1 << HPIPE_TRX_UPDATE_THEN_HOLD_OFFSET;
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mask |= HPIPE_TRX_TX_F0T_EO_BASED_MASK;
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data |= 0x1 << HPIPE_TRX_TX_F0T_EO_BASED_OFFSET;
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reg_set(hpipe_addr + HPIPE_TRX_TRAIN_CTRL_0_REG, data, mask);
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/* Check the result of RX training */
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@ -2180,21 +2182,9 @@ int mvebu_cp110_comphy_xfi_rx_training(uint64_t comphy_base,
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data = 1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET;
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reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);
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/* Use the value from CAL_OS_PH_EXT */
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mask = HPIPE_CAL_RXCLKALIGN_90_EXT_EN_MASK;
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data = 1 << HPIPE_CAL_RXCLKALIGN_90_EXT_EN_OFFSET;
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reg_set(hpipe_addr + HPIPE_RX_CLK_ALIGN90_AND_TX_IDLE_CALIB_CTRL_REG,
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data, mask);
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/* Update align90 */
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mask = HPIPE_CAL_OS_PH_EXT_MASK;
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data = align90 << HPIPE_CAL_OS_PH_EXT_OFFSET;
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reg_set(hpipe_addr + HPIPE_RX_CLK_ALIGN90_AND_TX_IDLE_CALIB_CTRL_REG,
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data, mask);
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/* Force DFE resolution (use gen table value) */
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mask = HPIPE_DFE_RES_FORCE_MASK;
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data = 0x0 << HPIPE_DFE_RES_FORCE_OFFSET;
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data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET;
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reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);
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/* 0x111-G1 DFE_Setting_4 */
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@ -2202,38 +2192,6 @@ int mvebu_cp110_comphy_xfi_rx_training(uint64_t comphy_base,
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data = g1_dfe_res << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET;
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reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask);
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debug("PRBS31 loppback\n\n");
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mask = HPIPE_PHY_TEST_PT_TESTMODE_MASK;
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data = 0x1 << HPIPE_PHY_TEST_PT_TESTMODE_OFFSET;
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reg_set(hpipe_addr + HPIPE_PHY_TEST_OOB_0_REGISTER, data, mask);
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/* Configure PRBS counters */
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mask = HPIPE_PHY_TEST_PATTERN_SEL_MASK;
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data = 0xe << HPIPE_PHY_TEST_PATTERN_SEL_OFFSET;
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reg_set(hpipe_addr + HPIPE_PHY_TEST_CONTROL_REG, data, mask);
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mask = HPIPE_PHY_TEST_DATA_MASK;
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data = 0xc4 << HPIPE_PHY_TEST_DATA_OFFSET;
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reg_set(hpipe_addr + HPIPE_PHY_TEST_DATA_REG, data, mask);
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mask = HPIPE_PHY_TEST_EN_MASK;
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data = 0x1 << HPIPE_PHY_TEST_EN_OFFSET;
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reg_set(hpipe_addr + HPIPE_PHY_TEST_CONTROL_REG, data, mask);
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/* Reset PRBS error counter */
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mask = HPIPE_PHY_TEST_PATTERN_SEL_MASK;
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data = 0x1 << HPIPE_PHY_TEST_RESET_OFFSET;
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reg_set(hpipe_addr + HPIPE_PHY_TEST_CONTROL_REG, data, mask);
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mask = HPIPE_PHY_TEST_PATTERN_SEL_MASK;
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data = 0x0 << HPIPE_PHY_TEST_RESET_OFFSET;
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reg_set(hpipe_addr + HPIPE_PHY_TEST_CONTROL_REG, data, mask);
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mask = HPIPE_PHY_TEST_PT_TESTMODE_MASK;
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data = 0x1 << HPIPE_PHY_TEST_PT_TESTMODE_OFFSET;
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reg_set(hpipe_addr + HPIPE_PHY_TEST_OOB_0_REGISTER, data, mask);
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printf("########################################################\n");
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printf("# To use trained values update the ATF sources:\n");
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printf("# plat/marvell/armada/a8k/<board_type>/board/phy-porting-layer.h ");
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@ -2252,12 +2210,6 @@ int mvebu_cp110_comphy_xfi_rx_training(uint64_t comphy_base,
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printf("};\n\n");
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printf("########################################################\n");
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/* check */
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debug("PRBS error counter[0x%lx] 0x%x\n\n",
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hpipe_addr + HPIPE_PHY_TEST_PRBS_ERROR_COUNTER_1_REG,
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mmio_read_32(hpipe_addr +
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HPIPE_PHY_TEST_PRBS_ERROR_COUNTER_1_REG));
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rx_trainng_done[ap_nr][cp_nr][comphy_index] = 1;
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return 0;
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