doc: Move "About" content from index.rst to a new chapter
The index.rst page is now the primary landing page for the TF-A documentation. It contains quite a lot of content these days, including: - The project purpose and general intro - A list of functionality - A list of planned functionality - A list of supported platforms - "Getting started" links to other documents - Contact information for raising issues This patch creates an "About" chapter in the table of contents and moves some content there. In order, the above listed content: - Stayed where it is. This is the right place for it. - Moved to About->Features - Moved to About->Features (in subsection) - Stayed where it is. Moved in a later patch. - Was expanded in-place - Moved to About->Contact Change-Id: I254bb87560fd09140b9e485cf15246892aa45943 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
This commit is contained in:
Paul Beesley
parent
937f669872
commit
8eb9490b61
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@ -15,3 +15,7 @@ Contributor Acknowledgements
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- Socionext Inc.
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- STMicroelectronics
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- Xilinx, Inc.
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--------------
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*Copyright (c) 2019, Arm Limited. All rights reserved.*
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@ -0,0 +1,17 @@
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Support & Contact
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-----------------
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We welcome any feedback on TF-A. If you think you have found a security
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vulnerability, please report this using the process defined in the TF-A
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:ref:`Security Handling` document.
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For all other feedback, please use the `issue tracker`_ or our `mailing list`_.
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Arm licensees may contact Arm directly via their partner managers.
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.. _issue tracker: https://issues.trustedfirmware.org
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.. _mailing list: https://lists.trustedfirmware.org/mailman/listinfo/tf-a
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--------------
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*Copyright (c) 2019, Arm Limited. All rights reserved.*
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@ -0,0 +1,127 @@
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Feature Overview
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================
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This page provides an overview of the current |TF-A| feature set. For a full
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description of these features and their implementation details, please see
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:ref:`Firmware Design` and supporting documentation.
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The :ref:`Change Log & Release Notes` provides details of changes made since the
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last release.
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Current features
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----------------
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- Initialization of the secure world, for example exception vectors, control
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registers and interrupts for the platform.
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- Library support for CPU specific reset and power down sequences. This
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includes support for errata workarounds and the latest Arm DynamIQ CPUs.
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- Drivers to enable standard initialization of Arm System IP, for example
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Generic Interrupt Controller (GIC), Cache Coherent Interconnect (CCI),
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Cache Coherent Network (CCN), Network Interconnect (NIC) and TrustZone
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Controller (TZC).
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- A generic |SCMI| driver to interface with conforming power controllers, for
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example the Arm System Control Processor (SCP).
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- SMC (Secure Monitor Call) handling, conforming to the `SMC Calling
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Convention`_ using an EL3 runtime services framework.
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- |PSCI| library support for CPU, cluster and system power management
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use-cases.
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This library is pre-integrated with the AArch64 EL3 Runtime Software, and
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is also suitable for integration with other AArch32 EL3 Runtime Software,
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for example an AArch32 Secure OS.
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- A minimal AArch32 Secure Payload (SP\_MIN) to demonstrate |PSCI| library
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integration with AArch32 EL3 Runtime Software.
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- Secure Monitor library code such as world switching, EL1 context management
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and interrupt routing.
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When a Secure-EL1 Payload (SP) is present, for example a Secure OS, the
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AArch64 EL3 Runtime Software must be integrated with a Secure Payload
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Dispatcher (SPD) component to customize the interaction with the SP.
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- A Test SP and SPD to demonstrate AArch64 Secure Monitor functionality and SP
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interaction with PSCI.
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- SPDs for the `OP-TEE Secure OS`_, `NVIDIA Trusted Little Kernel`_
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and `Trusty Secure OS`_.
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- A Trusted Board Boot implementation, conforming to all mandatory TBBR
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requirements. This includes image authentication, Firmware Update (or
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recovery mode), and packaging of the various firmware images into a
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Firmware Image Package (FIP).
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- Pre-integration of TBB with the Arm CryptoCell product, to take advantage of
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its hardware Root of Trust and crypto acceleration services.
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- Reliability, Availability, and Serviceability (RAS) functionality, including
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- A Secure Partition Manager (SPM) to manage Secure Partitions in
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Secure-EL0, which can be used to implement simple management and
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security services.
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- An |SDEI| dispatcher to route interrupt-based |SDEI| events.
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- An Exception Handling Framework (EHF) that allows dispatching of EL3
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interrupts to their registered handlers, to facilitate firmware-first
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error handling.
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- A dynamic configuration framework that enables each of the firmware images
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to be configured at runtime if required by the platform. It also enables
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loading of a hardware configuration (for example, a kernel device tree)
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as part of the FIP, to be passed through the firmware stages.
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- Support for alternative boot flows, for example to support platforms where
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the EL3 Runtime Software is loaded using other firmware or a separate
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secure system processor, or where a non-TF-A ROM expects BL2 to be loaded
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at EL3.
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- Support for the GCC, LLVM and Arm Compiler 6 toolchains.
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- Support for combining several libraries into a "romlib" image that may be
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shared across images to reduce memory footprint. The romlib image is stored
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in ROM but is accessed through a jump-table that may be stored
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in read-write memory, allowing for the library code to be patched.
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- A prototype implementation of a Secure Partition Manager (SPM) that is based
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on the SPCI Alpha 1 and SPRT draft specifications.
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- Support for ARMv8.3 pointer authentication in the normal and secure worlds.
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The use of pointer authentication in the normal world is enabled whenever
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architectural support is available, without the need for additional build
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flags. Use of pointer authentication in the secure world remains an
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experimental configuration at this time and requires the
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``BRANCH_PROTECTION`` option to be set to non-zero.
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- Position-Independent Executable (PIE) support. Initially for BL31 only, with
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further support to be added in a future release.
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Still to come
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-------------
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- Support for additional platforms.
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- Refinements to Position Independent Executable (PIE) support.
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- Refinements to the SPCI-based SPM implementation as the draft SPCI and SPRT
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specifications continue to evolve.
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- Documentation enhancements.
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- Ongoing support for new architectural features, CPUs and System IP.
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- Ongoing support for new Arm system architecture specifications.
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- Ongoing security hardening, optimization and quality improvements.
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.. _SMC Calling Convention: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf
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.. _OP-TEE Secure OS: https://github.com/OP-TEE/optee_os
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.. _NVIDIA Trusted Little Kernel: http://nv-tegra.nvidia.com/gitweb/?p=3rdparty/ote_partner/tlk.git;a=summary
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.. _Trusty Secure OS: https://source.android.com/security/trusty
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--------------
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*Copyright (c) 2019, Arm Limited. All rights reserved.*
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@ -0,0 +1,13 @@
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About
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=====
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.. toctree::
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:maxdepth: 1
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:caption: Contents
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:numbered:
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features
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release-information
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maintainers
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contact
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acknowledgements
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185
docs/index.rst
185
docs/index.rst
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@ -6,6 +6,7 @@ Trusted Firmware-A Documentation
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:hidden:
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Home<self>
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about/index
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getting_started/index
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process/index
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components/index
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@ -14,14 +15,9 @@ Trusted Firmware-A Documentation
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perf/index
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security_advisories/index
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change-log
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acknowledgements
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glossary
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maintainers
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license
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.. contents:: On This Page
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:depth: 3
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Trusted Firmware-A (TF-A) provides a reference implementation of secure world
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software for `Armv7-A and Armv8-A`_, including a `Secure Monitor`_ executing
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at Exception Level 3 (EL3). It implements various Arm interface standards,
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@ -47,101 +43,41 @@ In collaboration with interested parties, we will continue to enhance |TF-A|
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with reference implementations of Arm standards to benefit developers working
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with Armv7-A and Armv8-A TrustZone technology.
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Functionality
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-------------
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Getting Started
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---------------
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- Initialization of the secure world, for example exception vectors, control
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registers and interrupts for the platform.
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The |TF-A| documentation contains guidance for obtaining and building the
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software for existing, supported platforms, as well as supporting information
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for porting the software to a new platform.
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- Library support for CPU specific reset and power down sequences. This
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includes support for errata workarounds and the latest Arm DynamIQ CPUs.
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The **About** chapter gives a high-level overview of |TF-A| features as well as
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some information on the project and how it is organized.
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- Drivers to enable standard initialization of Arm System IP, for example
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Generic Interrupt Controller (GIC), Cache Coherent Interconnect (CCI),
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Cache Coherent Network (CCN), Network Interconnect (NIC) and TrustZone
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Controller (TZC).
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Refer to the documents in the **Getting Started** chapter for information about
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the prerequisites and requirements for building |TF-A|.
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- A generic `SCMI`_ driver to interface with conforming power controllers, for
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example the Arm System Control Processor (SCP).
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The **Processes & Policies** chapter explains the project's release schedule
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and process, how security disclosures are handled, and the guidelines for
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contributing to the project (including the coding style).
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- SMC (Secure Monitor Call) handling, conforming to the `SMC Calling
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Convention`_ using an EL3 runtime services framework.
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The **Components** chapter holds documents that explain specific components
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that make up the |TF-A| software, the :ref:`Exception Handling Framework`, for
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example.
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- `PSCI`_ library support for CPU, cluster and system power management
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use-cases.
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This library is pre-integrated with the AArch64 EL3 Runtime Software, and
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is also suitable for integration with other AArch32 EL3 Runtime Software,
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for example an AArch32 Secure OS.
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In the **System Design** chapter you will find documents that explain the
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design of portions of the software that involve more than one component, such
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as the :ref:`Trusted Board Boot` process.
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- A minimal AArch32 Secure Payload (SP\_MIN) to demonstrate `PSCI`_ library
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integration with AArch32 EL3 Runtime Software.
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**Platform Ports** provides a list of the supported hardware and software-model
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platforms that are supported upstream in |TF-A|. Most of these platforms also
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have additional documentation that has been provided by the maintainers of the
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platform.
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- Secure Monitor library code such as world switching, EL1 context management
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and interrupt routing.
|
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When a Secure-EL1 Payload (SP) is present, for example a Secure OS, the
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AArch64 EL3 Runtime Software must be integrated with a Secure Payload
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Dispatcher (SPD) component to customize the interaction with the SP.
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The results of any performance evaluations are added to the
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**Performance & Testing** chapter.
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- A Test SP and SPD to demonstrate AArch64 Secure Monitor functionality and SP
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interaction with PSCI.
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|
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- SPDs for the `OP-TEE Secure OS`_, `NVIDIA Trusted Little Kernel`_
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and `Trusty Secure OS`_.
|
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|
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- A Trusted Board Boot implementation, conforming to all mandatory TBBR
|
||||
requirements. This includes image authentication, Firmware Update (or
|
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recovery mode), and packaging of the various firmware images into a
|
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Firmware Image Package (FIP).
|
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|
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- Pre-integration of TBB with the Arm CryptoCell product, to take advantage of
|
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its hardware Root of Trust and crypto acceleration services.
|
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|
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- Reliability, Availability, and Serviceability (RAS) functionality, including
|
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|
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- A Secure Partition Manager (SPM) to manage Secure Partitions in
|
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Secure-EL0, which can be used to implement simple management and
|
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security services.
|
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|
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- An |SDEI| dispatcher to route interrupt-based |SDEI| events.
|
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|
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- An Exception Handling Framework (EHF) that allows dispatching of EL3
|
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interrupts to their registered handlers, to facilitate firmware-first
|
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error handling.
|
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|
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- A dynamic configuration framework that enables each of the firmware images
|
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to be configured at runtime if required by the platform. It also enables
|
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loading of a hardware configuration (for example, a kernel device tree)
|
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as part of the FIP, to be passed through the firmware stages.
|
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|
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- Support for alternative boot flows, for example to support platforms where
|
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the EL3 Runtime Software is loaded using other firmware or a separate
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secure system processor, or where a non-TF-A ROM expects BL2 to be loaded
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at EL3.
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|
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- Support for the GCC, LLVM and Arm Compiler 6 toolchains.
|
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|
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- Support for combining several libraries into a "romlib" image that may be
|
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shared across images to reduce memory footprint. The romlib image is stored
|
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in ROM but is accessed through a jump-table that may be stored
|
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in read-write memory, allowing for the library code to be patched.
|
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|
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- A prototype implementation of a Secure Partition Manager (SPM) that is based
|
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on the SPCI Alpha 1 and SPRT draft specifications.
|
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|
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- Support for ARMv8.3 pointer authentication in the normal and secure worlds.
|
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The use of pointer authentication in the normal world is enabled whenever
|
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architectural support is available, without the need for additional build
|
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flags. Use of pointer authentication in the secure world remains an
|
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experimental configuration at this time and requires the
|
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``BRANCH_PROTECTION`` option to be set to non-zero.
|
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|
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- Position-Independent Executable (PIE) support. Initially for BL31 only, with
|
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further support to be added in a future release.
|
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|
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For a full description of functionality and implementation details, please
|
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see :ref:`Firmware Design` and supporting documentation. The
|
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:ref:`Change Log & Release Notes` provides details of changes made since the
|
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last release.
|
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**Security Advisories** holds a list of documents relating to |CVE| entries that
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have previously been raised against the software.
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Platforms
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---------
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@ -224,74 +160,17 @@ This release also contains the following platform support:
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- Texas Instruments K3 SoCs
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- Xilinx Versal and Zynq UltraScale + MPSoC
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Still to come
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-------------
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- Support for additional platforms.
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- Refinements to Position Independent Executable (PIE) support.
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|
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- Refinements to the SPCI-based SPM implementation as the draft SPCI and SPRT
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specifications continue to evolve.
|
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|
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- Documentation enhancements.
|
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|
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- Ongoing support for new architectural features, CPUs and System IP.
|
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|
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- Ongoing support for new Arm system architecture specifications.
|
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|
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- Ongoing security hardening, optimization and quality improvements.
|
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|
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For a full list of detailed issues in the current code, please see the
|
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:ref:`Change Log & Release Notes` and the `issue tracker`_.
|
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|
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Getting started
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---------------
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See the :ref:`User Guide` for instructions on how to download, install, build
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and use TF-A with the Arm `FVP`_\ s.
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See the :ref:`Firmware Design` for information on how TF-A works.
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See the :ref:`Porting Guide` as well for information about how to use this
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software on another Armv7-A or Armv8-A platform.
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See the :ref:`Contributor's Guide` for information on how to contribute to this
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project and the :ref:`Contributor Acknowledgements` file for a list of
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contributors to the project.
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Contact Us
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~~~~~~~~~~
|
||||
|
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We welcome any feedback on TF-A. If you think you have found a security
|
||||
vulnerability, please report this using the process defined in the TF-A
|
||||
:ref:`Security Handling` document.
|
||||
|
||||
For all other feedback, please use the `issue tracker`_ or our `mailing list`_.
|
||||
|
||||
Arm licensees may contact Arm directly via their partner managers.
|
||||
|
||||
--------------
|
||||
|
||||
*Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.*
|
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|
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.. _Armv7-A and Armv8-A: https://developer.arm.com/products/architecture/a-profile
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.. _Secure Monitor: http://www.arm.com/products/processors/technologies/trustzone/tee-smc.php
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.. _Power State Coordination Interface (PSCI): PSCI_
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.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
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.. _Power State Coordination Interface (PSCI): http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
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.. _Trusted Board Boot Requirements CLIENT (TBBR-CLIENT): https://developer.arm.com/docs/den0006/latest/trusted-board-boot-requirements-client-tbbr-client-armv8-a
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.. _SMC Calling Convention: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf
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.. _System Control and Management Interface (SCMI): SCMI_
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.. _SCMI: http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/DEN0056A_System_Control_and_Management_Interface.pdf
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.. _Software Delegated Exception Interface (SDEI): SDEI_
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.. _SDEI: http://infocenter.arm.com/help/topic/com.arm.doc.den0054a/ARM_DEN0054A_Software_Delegated_Exception_Interface.pdf
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.. _System Control and Management Interface (SCMI): http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/DEN0056A_System_Control_and_Management_Interface.pdf
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.. _Software Delegated Exception Interface (SDEI): http://infocenter.arm.com/help/topic/com.arm.doc.den0054a/ARM_DEN0054A_Software_Delegated_Exception_Interface.pdf
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.. _Juno Arm Development Platform: http://www.arm.com/products/tools/development-boards/versatile-express/juno-arm-development-platform.php
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.. _Arm FVP website: FVP_
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.. _FVP: https://developer.arm.com/products/system-design/fixed-virtual-platforms
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.. _Arm FVP website: https://developer.arm.com/products/system-design/fixed-virtual-platforms
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.. _Linaro Release 19.06: http://releases.linaro.org/members/arm/platforms/19.06
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.. _OP-TEE Secure OS: https://github.com/OP-TEE/optee_os
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.. _NVIDIA Trusted Little Kernel: http://nv-tegra.nvidia.com/gitweb/?p=3rdparty/ote_partner/tlk.git;a=summary
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.. _Trusty Secure OS: https://source.android.com/security/trusty
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.. _trustedfirmware.org: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
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.. _issue tracker: https://issues.trustedfirmware.org
|
||||
.. _mailing list: https://lists.trustedfirmware.org/mailman/listinfo/tf-a
|
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.. _SMC Calling Convention: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf
|
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|
|
|
|||
|
|
@ -6,7 +6,6 @@ Processes & Policies
|
|||
:caption: Contents
|
||||
:numbered:
|
||||
|
||||
release-information
|
||||
security
|
||||
platform-compatibility-policy
|
||||
coding-guidelines
|
||||
|
|
|
|||
Loading…
Reference in New Issue