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Merge changes from topic "release/14.0" into integration 

* changes:
  docs: marvell: update PHY porting layer description
  docs: marvell: update path in marvell documentation
  docs: marvell: update build instructions with CN913x
  plat: marvell: octeontx: add support for t9130
  plat: marvell: t9130: add SVC support
  plat: marvell: t9130: update AVS settings
  plat: marvell: t9130: pass actual CP count for load_image
  plat: marvell: armada: a7k: add support to SVC validation mode
  plat: marvell: armada: add support for twin-die combined memory device
This commit is contained in:
Manish Pandey 2020-08-10 23:13:36 +00:00 committed by TrustedFirmware Code Review
parent 37a12f04be 3045dfe10c
commit 8f09da46e2
15 changed files with 619 additions and 53 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
docs/plat/marvell/armada/build.rst
View File

@ -26,7 +26,7 @@ BL33 should be ``~/project/u-boot/u-boot.bin``
*u-boot.bin* should be used and not *u-boot-spl.bin*
Set MSS/SCP image path (mandatory only for Armada80x0)
Set MSS/SCP image path (mandatory only for A7K/8K/CN913x)
.. code:: shell
@ -92,22 +92,31 @@ There are several build options:
- BLE_PATH
Points to BLE (Binary ROM extension) sources folder. Only required for A8K builds.
Points to BLE (Binary ROM extension) sources folder.
Only required for A7K/8K/CN913x builds.
The parameter is optional, its default value is ``plat/marvell/armada/a8k/common/ble``.
- MV_DDR_PATH
For A7/8K, use this parameter to point to mv_ddr driver sources to allow BLE build. For A37x0,
For A7K/8K/CN913x, use this parameter to point to mv_ddr driver sources to allow BLE build. For A37x0,
it is used for ddr_tool build.
Usage example: MV_DDR_PATH=path/to/mv_ddr
The parameter is optional for A7/8K, when this parameter is not set, the mv_ddr
The parameter is optional for A7K/8K/CN913x, when this parameter is not set, the mv_ddr
sources are expected to be located at: drivers/marvell/mv_ddr. However, the parameter
is necessary for A37x0.
For the mv_ddr source location, check the section "Tools and external components installation"
- CP_NUM
Total amount of CPs (South Bridge) connected to AP. When the parameter is omitted,
the build uses the default number of CPs, which is a number of embedded CPs inside the
package: 1 or 2 depending on the SoC used. The parameter is valid for OcteonTX2 CN913x SoC
family (PLAT=t9130), which can have external CPs connected to the MCI ports. Valid
values with CP_NUM are in a range of 1 to 3.
- DDR_TOPOLOGY
For Armada37x0 only, the DDR topology map index/name, default is 0.
@ -191,7 +200,8 @@ There are several build options:
- a70x0
- a70x0_amc (for AMC board)
- a80x0
- a80x0_mcbin (for MacciatoBin)
- a80x0_mcbin (for MacchiatoBin)
- t9130 (OcteonTX2 CN913x)
Special Build Flags
--------------------
@ -199,7 +209,7 @@ Special Build Flags
- PLAT_RECOVERY_IMAGE_ENABLE
When set this option to enable secondary recovery function when build atf.
In order to build UART recovery image this operation should be disabled for
a70x0 and a80x0 because of hardware limitation (boot from secondary image
A7K/8K/CN913x because of hardware limitation (boot from secondary image
can interrupt UART recovery process). This MACRO definition is set in
``plat/marvell/armada/a8k/common/include/platform_def.h`` file.

7
docs/plat/marvell/armada/porting.rst
View File

@ -36,7 +36,7 @@ memory map is required.
.. note::
For a detailed information on how CCU, IOWIN, AXI-MBUS & IOB work, please
refer to the SoC functional spec, and under
``docs/marvell/misc/mvebu-[ccu/iob/amb/io-win].txt`` files.
``docs/plat/marvell/armada/misc/mvebu-[ccu/iob/amb/io-win].rst`` files.
boot loader recovery (marvell_plat_config.c)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@ -110,11 +110,6 @@ Comphy Porting (phy-porting-layer.h or phy-default-porting-layer.h)
parameters need to be suited and the board designer should provide relevant
values.
.. seealso::
For XFI/SFI comphy type there is procedure "rx_training" which eases
process of suiting some of the parameters. Please see *uboot_cmd*
section: rx_training.
The PHY porting layer simplifies updating static values per board type,
which are now grouped in one place.

1
include/drivers/marvell/mochi/cp110_setup.h
View File

@ -24,6 +24,7 @@
#define MVEBU_3900_DEV_ID (0x6025)
#define MVEBU_80X0_DEV_ID (0x8040)
#define MVEBU_80X0_CP115_DEV_ID (0x8045)
#define MVEBU_CN9130_DEV_ID (0x7025)
#define MVEBU_CP110_SA_DEV_ID (0x110)
#define MVEBU_CP110_REF_ID_A1 1
#define MVEBU_CP110_REF_ID_A2 2

1
plat/marvell/armada/a8k/a70x0/board/dram_port.c
View File

@ -46,6 +46,7 @@ static struct mv_ddr_topology_map board_topology_map = {
MV_DDR_TEMP_LOW} }, /* temperature */
MV_DDR_32BIT_ECC_PUP8_BUS_MASK, /* subphys mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
NOT_COMBINED, /* ddr twin-die combined*/
{ {0} }, /* raw spd data */
{0}, /* timing parameters */
{ /* electrical configuration */

1
plat/marvell/armada/a8k/a70x0_amc/board/dram_port.c
View File

@ -46,6 +46,7 @@ static struct mv_ddr_topology_map board_topology_map = {
MV_DDR_TEMP_LOW} }, /* temperature */
MV_DDR_32BIT_ECC_PUP8_BUS_MASK, /* subphys mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
NOT_COMBINED, /* ddr twin-die combined*/
{ {0} }, /* raw spd data */
{0}, /* timing parameters */
{ /* electrical configuration */

1
plat/marvell/armada/a8k/a80x0/board/dram_port.c
View File

@ -58,6 +58,7 @@ static struct mv_ddr_topology_map board_topology_map = {
MV_DDR_64BIT_ECC_PUP8_BUS_MASK, /* subphys mask */
#endif
MV_DDR_CFG_SPD, /* ddr configuration data source */
NOT_COMBINED, /* ddr twin-die combined*/
{ {0} }, /* raw spd data */
{0}, /* timing parameters */
{ /* electrical configuration */

1
plat/marvell/armada/a8k/a80x0_mcbin/board/dram_port.c
View File

@ -48,6 +48,7 @@ static struct mv_ddr_topology_map board_topology_map = {
MV_DDR_TEMP_LOW} }, /* temperature */
MV_DDR_64BIT_BUS_MASK, /* subphys mask */
MV_DDR_CFG_SPD, /* ddr configuration data source */
NOT_COMBINED, /* ddr twin-die combined*/
{ {0} }, /* raw spd data */
{0}, /* timing parameters */
{ /* electrical configuration */

1
plat/marvell/armada/a8k/a80x0_puzzle/board/dram_port.c
View File

@ -54,6 +54,7 @@ static struct mv_ddr_topology_map board_topology_map = {
MV_DDR_TEMP_LOW} }, /* temperature */
MV_DDR_64BIT_BUS_MASK, /* subphys mask */
MV_DDR_CFG_SPD, /* ddr configuration data source */
NOT_COMBINED, /* ddr twin-die combined*/
{ {0} }, /* raw spd data */
{0}, /* timing parameters */
{ /* electrical configuration */

2
plat/marvell/armada/a8k/common/mss/mss_bl2_setup.c
View File

@ -138,6 +138,8 @@ uint32_t bl2_plat_get_cp_count(int ap_idx)
if (revision == MVEBU_80X0_DEV_ID ||
revision == MVEBU_80X0_CP115_DEV_ID)
return 2;
else if (revision == MVEBU_CN9130_DEV_ID)
return CP_COUNT;
else
return 1;
}

106
plat/marvell/armada/a8k/common/plat_ble_setup.c
View File

@ -74,22 +74,9 @@
(0x24 << AVS_LOW_VDD_LIMIT_OFFSET) | \
(0x1 << AVS_SOFT_RESET_OFFSET) | \
(0x1 << AVS_ENABLE_OFFSET))
/* VDD limit is 0.82V for all A3900 devices
* AVS offsets are not the same as in A70x0
*/
#define AVS_A3900_CLK_VALUE ((0x80u << 24) | \
(0x2c2 << 13) | \
(0x2c2 << 3) | \
(0x1 << AVS_SOFT_RESET_OFFSET) | \
(0x1 << AVS_ENABLE_OFFSET))
/* VDD is 0.88V for 2GHz clock */
#define AVS_A3900_HIGH_CLK_VALUE ((0x80u << 24) | \
(0x2f5 << 13) | \
(0x2f5 << 3) | \
(0x1 << AVS_SOFT_RESET_OFFSET) | \
(0x1 << AVS_ENABLE_OFFSET))
#define AVS_CN9130_HIGH_CLK_VALUE ((0x80 << 24) | \
/* VDD is 0.88V for 2GHz clock on CN913x devices */
#define AVS_AP807_CLK_VALUE ((0x80UL << 24) | \
(0x2dc << 13) | \
(0x2dc << 3) | \
(0x1 << AVS_SOFT_RESET_OFFSET) | \
@ -123,7 +110,6 @@
#define EFUSE_AP_LD0_REVID_MASK 0xF
#define EFUSE_AP_LD0_BIN_OFFS 16 /* LD0[80:79] */
#define EFUSE_AP_LD0_BIN_MASK 0x3
#define EFUSE_AP_LD0_SWREV_OFFS 50 /* LD0[115:113] */
#define EFUSE_AP_LD0_SWREV_MASK 0x7
#ifndef MVEBU_SOC_AP807
@ -137,16 +123,18 @@
#define EFUSE_AP_LD0_SVC2_OFFS 26 /* LD0[96:89] */
#define EFUSE_AP_LD0_SVC3_OFFS 34 /* LD0[104:97] */
#define EFUSE_AP_LD0_WP_MASK 0xFF
#define EFUSE_AP_LD0_SWREV_OFFS 50 /* LD0[115:113] */
#else
/* AP807 AVS work points in the LD0 eFuse
* SVC1 work point: LD0[91:81]
* SVC2 work point: LD0[102:92]
* SVC3 work point: LD0[113:103]
*/
#define EFUSE_AP_LD0_SVC1_OFFS 17 /* LD0[91:81] */
#define EFUSE_AP_LD0_SVC2_OFFS 28 /* LD0[102:92] */
#define EFUSE_AP_LD0_SVC3_OFFS 39 /* LD0[113:103] */
#define EFUSE_AP_LD0_WP_MASK 0x3FF
#define EFUSE_AP_LD0_SVC1_OFFS 18 /* LD0[91:81] */
#define EFUSE_AP_LD0_SVC2_OFFS 29 /* LD0[102:92] */
#define EFUSE_AP_LD0_SVC3_OFFS 40 /* LD0[113:103] */
#define EFUSE_AP_LD0_WP_MASK 0x7FF /* 10 data,1 parity */
#define EFUSE_AP_LD0_SWREV_OFFS 51 /* LD0[116:114] */
#endif
#define EFUSE_AP_LD0_SVC4_OFFS 42 /* LD0[112:105] */
@ -229,19 +217,8 @@ static void ble_plat_avs_config(void)
FREQ_MODE_AP_SAR_REG_NUM)));
/* Check which SoC is running and act accordingly */
if (ble_get_ap_type() == CHIP_ID_AP807) {
/* Increase CPU voltage for higher CPU clock */
switch (freq_mode) {
case CPU_2000_DDR_1200_RCLK_1200:
avs_val = AVS_A3900_HIGH_CLK_VALUE;
break;
#ifdef MVEBU_SOC_AP807
case CPU_2200_DDR_1200_RCLK_1200:
avs_val = AVS_CN9130_HIGH_CLK_VALUE;
break;
#endif
default:
avs_val = AVS_A3900_CLK_VALUE;
}
avs_val = AVS_AP807_CLK_VALUE;
} else {
/* Check which SoC is running and act accordingly */
@ -396,6 +373,7 @@ static void ble_plat_svc_config(void)
uint64_t efuse;
uint32_t device_id, single_cluster;
uint16_t svc[4], perr[4], i, sw_ver;
uint8_t avs_data_bits, min_sw_ver, svc_fields;
unsigned int ap_type;
/* Set access to LD0 */
@ -449,22 +427,28 @@ static void ble_plat_svc_config(void)
& EFUSE_AP_LD0_WP_MASK;
INFO("SVC: Efuse WP: [0]=0x%x, [1]=0x%x, [2]=0x%x, [3]=0x%x\n",
svc[0], svc[1], svc[2], svc[3]);
avs_data_bits = 7;
min_sw_ver = 2; /* parity check from sw revision 2 */
svc_fields = 4;
} else {
INFO("SVC: Efuse WP: [0]=0x%x, [1]=0x%x, [2]=0x%x\n",
svc[0], svc[1], svc[2]);
avs_data_bits = 10;
min_sw_ver = 1; /* parity check required from sw revision 1 */
svc_fields = 3;
}
/* Validate parity of SVC workpoint values */
for (i = 0; i < 4; i++) {
for (i = 0; i < svc_fields; i++) {
uint8_t parity, bit;
perr[i] = 0;
for (bit = 1, parity = svc[i] & 1; bit < 7; bit++)
for (bit = 1, parity = (svc[i] & 1); bit < avs_data_bits; bit++)
parity ^= (svc[i] >> bit) & 1;
/* Starting from SW version 2, the parity check is mandatory */
if ((sw_ver > 1) && (parity != ((svc[i] >> 7) & 1)))
/* From SW version 1 or 2 (AP806/AP807), check parity */
if ((sw_ver >= min_sw_ver) &&
(parity != ((svc[i] >> avs_data_bits) & 1)))
perr[i] = 1; /* register the error */
}
@ -554,8 +538,19 @@ static void ble_plat_svc_config(void)
if (perr[0])
goto perror;
avs_workpoint = svc[0];
} else
avs_workpoint = 0;
} else {
#if MARVELL_SVC_TEST
reg_val = mmio_read_32(AVS_EN_CTRL_REG);
avs_workpoint = (reg_val &
AVS_VDD_LOW_LIMIT_MASK) >>
AVS_LOW_VDD_LIMIT_OFFSET;
NOTICE("7040 1600Mhz, avs = 0x%x\n",
avs_workpoint);
#else
NOTICE("SVC: AVS work point not changed\n");
return;
#endif
}
break;
}
} else if (device_id == MVEBU_3900_DEV_ID) {
@ -578,6 +573,31 @@ static void ble_plat_svc_config(void)
avs_workpoint = svc[0];
break;
}
} else if (device_id == MVEBU_CN9130_DEV_ID) {
NOTICE("SVC: DEV ID: %s, FREQ Mode: 0x%x\n",
"CN913x", freq_pidi_mode);
switch (freq_pidi_mode) {
case CPU_2200_DDR_1200_RCLK_1200:
if (perr[0])
goto perror;
avs_workpoint = svc[0];
break;
case CPU_2000_DDR_1200_RCLK_1200:
if (perr[1])
goto perror;
avs_workpoint = svc[1];
break;
case CPU_1600_DDR_1200_RCLK_1200:
if (perr[2])
goto perror;
avs_workpoint = svc[2];
break;
default:
ERROR("SVC: Unsupported Frequency 0x%x\n",
freq_pidi_mode);
return;
}
} else {
ERROR("SVC: Unsupported Device ID 0x%x\n", device_id);
return;
@ -585,13 +605,17 @@ static void ble_plat_svc_config(void)
/* Set AVS control if needed */
if (avs_workpoint == 0) {
ERROR("SVC: AVS work point not changed\n");
ERROR("SVC: You are using a frequency setup which is\n");
ERROR("Not supported by this device\n");
ERROR("This may result in malfunction of the device\n");
return;
}
/* Remove parity bit */
if (ap_type != CHIP_ID_AP807)
avs_workpoint &= 0x7F;
else
avs_workpoint &= 0x3FF;
/* Update WP from EEPROM if needed */
avs_workpoint = avs_update_from_eeprom(avs_workpoint);

158
plat/marvell/octeontx/otx2/t91/t9130/board/dram_port.c Normal file
View File

@ -0,0 +1,158 @@
/*
* Copyright (C) 2018 Marvell International Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
* https://spdx.org/licenses
*/
#include <arch_helpers.h>
#include <common/debug.h>
#include <drivers/mentor/mi2cv.h>
#include <lib/mmio.h>
#include <mv_ddr_if.h>
#include <mvebu_def.h>
#include <plat_marvell.h>
#define MVEBU_CP_MPP_CTRL37_OFFS 20
#define MVEBU_CP_MPP_CTRL38_OFFS 24
#define MVEBU_CP_MPP_CTRL37_I2C0_SCK_ENA 0x2
#define MVEBU_CP_MPP_CTRL38_I2C0_SDA_ENA 0x2
#define MVEBU_MPP_CTRL_MASK 0xf
/*
* This struct provides the DRAM training code with
* the appropriate board DRAM configuration
*/
struct mv_ddr_iface dram_iface_ap0 = {
.ap_base = MVEBU_REGS_BASE_AP(0),
.state = MV_DDR_IFACE_NRDY,
.validation = MV_DDR_MEMORY_CHECK,
.sscg = SSCG_EN,
.id = 0,
.iface_base_addr = 0,
.tm = {
DEBUG_LEVEL_ERROR,
0x1, /* active interfaces */
/* cs_mask, mirror, dqs_swap, ck_swap X subphys */
{ { { {0x1, 0x0, 0, 0},
{0x1, 0x0, 0, 0},
{0x1, 0x0, 0, 0},
{0x1, 0x0, 0, 0},
{0x1, 0x0, 0, 0},
{0x1, 0x0, 0, 0},
{0x1, 0x0, 0, 0},
{0x1, 0x0, 0, 0},
{0x1, 0x0, 0, 0} },
SPEED_BIN_DDR_2400T, /* speed_bin */
MV_DDR_DEV_WIDTH_8BIT, /* sdram device width */
MV_DDR_DIE_CAP_8GBIT, /* die capacity */
MV_DDR_FREQ_SAR, /* frequency */
0, 0, /* cas_l, cas_wl */
MV_DDR_TEMP_LOW} }, /* temperature */
#if DDR32
MV_DDR_32BIT_ECC_PUP8_BUS_MASK, /* subphys mask */
#else
MV_DDR_64BIT_ECC_PUP8_BUS_MASK, /* subphys mask */
#endif
MV_DDR_CFG_SPD, /* ddr configuration data src */
NOT_COMBINED, /* ddr twin-die combined*/
{ {0} }, /* raw spd data */
{0}, /* timing parameters */
{ /* electrical configuration */
{ /* memory electrical configuration */
MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */
{ /* rtt_park 1cs */
MV_DDR_RTT_NOM_PARK_RZQ_DIV4,
/* rtt_park 2cs */
MV_DDR_RTT_NOM_PARK_RZQ_DIV1
},
{ /* rtt_wr 1cs */
MV_DDR_RTT_WR_DYN_ODT_OFF,
/* rtt_wr 2cs */
MV_DDR_RTT_WR_RZQ_DIV2
},
MV_DDR_DIC_RZQ_DIV7 /* dic */
},
{ /* phy electrical configuration */
MV_DDR_OHM_30, /* data_drv_p */
MV_DDR_OHM_30, /* data_drv_n */
MV_DDR_OHM_30, /* ctrl_drv_p */
MV_DDR_OHM_30, /* ctrl_drv_n */
{
MV_DDR_OHM_60, /* odt_p 1cs */
MV_DDR_OHM_120 /* odt_p 2cs */
},
{
MV_DDR_OHM_60, /* odt_n 1cs */
MV_DDR_OHM_120 /* odt_n 2cs */
},
},
{ /* mac electrical configuration */
MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */
MV_DDR_ODT_CFG_ALWAYS_ON,/* odtcfg_write */
MV_DDR_ODT_CFG_NORMAL /* odtcfg_read */
},
},
},
};
/* Pointer to the first DRAM interface in the system */
struct mv_ddr_iface *ptr_iface = &dram_iface_ap0;
struct mv_ddr_iface *mv_ddr_iface_get(void)
{
/* Return current ddr interface */
return ptr_iface;
}
struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
{
/* Return the board topology as defined in the board code */
return &ptr_iface->tm;
}
static void mpp_config(void)
{
uintptr_t reg;
uint32_t val;
reg = MVEBU_CP_MPP_REGS(0, 4);
/* configure CP0 MPP 37 and 38 to i2c */
val = mmio_read_32(reg);
val &= ~((MVEBU_MPP_CTRL_MASK << MVEBU_CP_MPP_CTRL37_OFFS) |
(MVEBU_MPP_CTRL_MASK << MVEBU_CP_MPP_CTRL38_OFFS));
val |= (MVEBU_CP_MPP_CTRL37_I2C0_SCK_ENA <<
MVEBU_CP_MPP_CTRL37_OFFS) |
(MVEBU_CP_MPP_CTRL38_I2C0_SDA_ENA <<
MVEBU_CP_MPP_CTRL38_OFFS);
mmio_write_32(reg, val);
}
/*
* This function may modify the default DRAM parameters
* based on information received from SPD or bootloader
* configuration located on non volatile storage
*/
void plat_marvell_dram_update_topology(void)
{
struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
INFO("Gathering DRAM information\n");
if (tm->cfg_src == MV_DDR_CFG_SPD) {
/* configure MPPs to enable i2c */
mpp_config();
/* initialize i2c */
i2c_init((void *)MVEBU_CP0_I2C_BASE);
/* select SPD memory page 0 to access DRAM configuration */
i2c_write(I2C_SPD_P0_ADDR, 0x0, 1, tm->spd_data.all_bytes, 1);
/* read data from spd */
i2c_read(I2C_SPD_ADDR, 0x0, 1, tm->spd_data.all_bytes,
sizeof(tm->spd_data.all_bytes));
}
}

188
plat/marvell/octeontx/otx2/t91/t9130/board/marvell_plat_config.c Normal file
View File

@ -0,0 +1,188 @@
/*
* Copyright (C) 2018 Marvell International Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
* https://spdx.org/licenses
*/
#include <armada_common.h>
#include <mvebu_def.h>
/*
* If bootrom is currently at BLE there's no need to include the memory
* maps structure at this point
*/
#ifndef IMAGE_BLE
/*****************************************************************************
* AMB Configuration
*****************************************************************************
*/
struct addr_map_win amb_memory_map_cp0[] = {
/* CP0 SPI1 CS0 Direct Mode access */
{0xe800, 0x2000000, AMB_SPI1_CS0_ID},
};
int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size,
uintptr_t base)
{
switch (base) {
case MVEBU_CP_REGS_BASE(0):
*win = amb_memory_map_cp0;
*size = ARRAY_SIZE(amb_memory_map_cp0);
return 0;
case MVEBU_CP_REGS_BASE(1):
case MVEBU_CP_REGS_BASE(2):
default:
*size = 0;
*win = 0;
return 1;
}
}
#endif
/*****************************************************************************
* IO WIN Configuration
*****************************************************************************
*/
struct addr_map_win io_win_memory_map[] = {
#ifndef IMAGE_BLE
/* SB (MCi0) PCIe0-2 on CP1 */
{0x00000000e2000000, 0x3000000, MCI_0_TID},
/* SB (MCi1) PCIe0-2 on CP2 */
{0x00000000e5000000, 0x3000000, MCI_1_TID},
/* SB (MCi0) internal regs */
{0x00000000f4000000, 0x2000000, MCI_0_TID},
/* SB (MCi1) internal regs */
{0x00000000f6000000, 0x2000000, MCI_1_TID},
/* MCI 0 indirect window */
{MVEBU_MCI_REG_BASE_REMAP(0), 0x100000, MCI_0_TID},
/* MCI 1 indirect window */
{MVEBU_MCI_REG_BASE_REMAP(1), 0x100000, MCI_1_TID},
#endif
};
/* Global Control Register - window default target */
uint32_t marvell_get_io_win_gcr_target(int ap_index)
{
/*
* PIDI == iMCIP AP to SB internal MoChi connection.
* In other words CP0
*/
return PIDI_TID;
}
int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win,
uint32_t *size)
{
*win = io_win_memory_map;
if (*win == NULL)
*size = 0;
else
*size = ARRAY_SIZE(io_win_memory_map);
return 0;
}
#ifndef IMAGE_BLE
/*****************************************************************************
* IOB Configuration
*****************************************************************************
*/
struct addr_map_win iob_memory_map_cp0[] = {
/* SPI1_CS0 (RUNIT) window */
{0x00000000e8000000, 0x2000000, RUNIT_TID},
/* PEX2_X1 window */
{0x00000000e1000000, 0x1000000, PEX2_TID},
/* PEX1_X1 window */
{0x00000000e0000000, 0x1000000, PEX1_TID},
/* PEX0_X4 window */
{0x00000000c0000000, 0x20000000, PEX0_TID},
};
struct addr_map_win iob_memory_map_cp1[] = {
/* PEX2_X1 window */
{0x00000000e4000000, 0x1000000, PEX2_TID},
/* PEX1_X1 window */
{0x00000000e3000000, 0x1000000, PEX1_TID},
/* PEX0_X4 window */
{0x00000000e2000000, 0x1000000, PEX0_TID},
};
struct addr_map_win iob_memory_map_cp2[] = {
/* PEX2_X1 window */
{0x00000000e7000000, 0x1000000, PEX2_TID},
/* PEX1_X1 window */
{0x00000000e6000000, 0x1000000, PEX1_TID},
/* PEX0_X4 window */
{0x00000000e5000000, 0x1000000, PEX0_TID},
};
int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size,
uintptr_t base)
{
switch (base) {
case MVEBU_CP_REGS_BASE(0):
*win = iob_memory_map_cp0;
*size = ARRAY_SIZE(iob_memory_map_cp0);
return 0;
case MVEBU_CP_REGS_BASE(1):
*win = iob_memory_map_cp1;
*size = ARRAY_SIZE(iob_memory_map_cp1);
return 0;
case MVEBU_CP_REGS_BASE(2):
*win = iob_memory_map_cp2;
*size = ARRAY_SIZE(iob_memory_map_cp2);
return 0;
default:
*size = 0;
*win = 0;
return 1;
}
}
#endif
/*****************************************************************************
* CCU Configuration
*****************************************************************************
*/
struct addr_map_win ccu_memory_map[] = { /* IO window */
#ifdef IMAGE_BLE
{0x00000000f2000000, 0x6000000, IO_0_TID}, /* IO window */
#else
#if LLC_SRAM
{PLAT_MARVELL_LLC_SRAM_BASE, PLAT_MARVELL_LLC_SRAM_SIZE, DRAM_0_TID},
#endif
{0x00000000f2000000, 0xe000000, IO_0_TID}, /* IO window */
{0x00000000c0000000, 0x30000000, IO_0_TID}, /* IO window */
{0x0000002000000000, 0x70e000000, IO_0_TID}, /* IO for CV-OS */
#endif
};
uint32_t marvell_get_ccu_gcr_target(int ap)
{
return DRAM_0_TID;
}
int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win,
uint32_t *size)
{
*win = ccu_memory_map;
*size = ARRAY_SIZE(ccu_memory_map);
return 0;
}
#ifdef IMAGE_BLE
/*****************************************************************************
* SKIP IMAGE Configuration
*****************************************************************************
*/
void *plat_get_skip_image_data(void)
{
/* No recovery button on CN-9130 board? */
return NULL;
}
#endif

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/*
* Copyright (C) 2018 Marvell International Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
* https://spdx.org/licenses
*/
#ifndef __PHY_PORTING_LAYER_H
#define __PHY_PORTING_LAYER_H
#define MAX_LANE_NR 6
#define XFI_PARAMS static const struct xfi_params
XFI_PARAMS xfi_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
/* AP0 */
{
/* CP 0 */
{
{ 0 }, /* Comphy0 not relevant*/
{ 0 }, /* Comphy1 not relevant*/
{ .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf,
.align90 = 0x5f,
.g1_dfe_res = 0x2, .g1_amp = 0x1c,
.g1_emph = 0xe,
.g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1,
.g1_tx_emph_en = 0x1,
.g1_tx_emph = 0x0, .g1_rx_selmuff = 0x1,
.g1_rx_selmufi = 0x0,
.g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2,
.valid = 1 }, /* Comphy2 */
{ 0 }, /* Comphy3 not relevant*/
{ .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf,
.align90 = 0x5f,
.g1_dfe_res = 0x2, .g1_amp = 0x1c,
.g1_emph = 0xe,
.g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1,
.g1_tx_emph_en = 0x1,
.g1_tx_emph = 0x0, .g1_rx_selmuff = 0x1,
.g1_rx_selmufi = 0x0,
.g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2,
.valid = 1 }, /* Comphy4 */
{ 0 }, /* Comphy5 not relevant*/
},
#if CP_NUM > 1
/* CP 1 */
{
{ 0 }, /* Comphy0 not relevant*/
{ 0 }, /* Comphy1 not relevant*/
{ .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf,
.align90 = 0x5f,
.g1_dfe_res = 0x2, .g1_amp = 0x1c,
.g1_emph = 0xe,
.g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1,
.g1_tx_emph_en = 0x1,
.g1_tx_emph = 0x0, .g1_rx_selmuff = 0x1,
.g1_rx_selmufi = 0x0,
.g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2,
.valid = 1 }, /* Comphy2 */
{ 0 }, /* Comphy3 not relevant*/
/* different from defaults */
{ .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf,
.align90 = 0x5f,
.g1_dfe_res = 0x2, .g1_amp = 0xc,
.g1_emph = 0x5,
.g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1,
.g1_tx_emph_en = 0x1,
.g1_tx_emph = 0x0, .g1_rx_selmuff = 0x1,
.g1_rx_selmufi = 0x0,
.g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2,
.valid = 1}, /* Comphy4 */
{ 0 }, /* Comphy5 not relevant*/
},
#if CP_NUM > 2
/* CP 2 */
{
{ 0 }, /* Comphy0 not relevant*/
{ 0 }, /* Comphy1 not relevant*/
{ .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf,
.align90 = 0x5f,
.g1_dfe_res = 0x2, .g1_amp = 0x1c,
.g1_emph = 0xe,
.g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1,
.g1_tx_emph_en = 0x1,
.g1_tx_emph = 0x0, .g1_rx_selmuff = 0x1,
.g1_rx_selmufi = 0x0,
.g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2,
.valid = 1 }, /* Comphy2 */
{ 0 }, /* Comphy3 not relevant*/
{ .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf,
.align90 = 0x5f,
.g1_dfe_res = 0x2, .g1_amp = 0x1c,
.g1_emph = 0xe,
.g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1,
.g1_tx_emph_en = 0x1,
.g1_tx_emph = 0x0, .g1_rx_selmuff = 0x1,
.g1_rx_selmufi = 0x0,
.g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2,
.valid = 1 }, /* Comphy4 */
{ 0 }, /* Comphy5 not relevant*/
},
#endif
#endif
},
};
#define SATA_PARAMS static const struct sata_params
SATA_PARAMS sata_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
[0 ... AP_NUM-1][0 ... CP_NUM-1][0 ... MAX_LANE_NR-1] = {
.g1_amp = 0x8, .g2_amp = 0xa,
.g3_amp = 0x1e,
.g1_emph = 0x1, .g2_emph = 0x2,
.g3_emph = 0xe,
.g1_emph_en = 0x1, .g2_emph_en = 0x1,
.g3_emph_en = 0x1,
.g1_tx_amp_adj = 0x1, .g2_tx_amp_adj = 0x1,
.g3_tx_amp_adj = 0x1,
.g1_tx_emph_en = 0x0, .g2_tx_emph_en = 0x0,
.g3_tx_emph_en = 0x0,
.g1_tx_emph = 0x1, .g2_tx_emph = 0x1,
.g3_tx_emph = 0x1,
.g3_dfe_res = 0x1, .g3_ffe_res_sel = 0x4,
.g3_ffe_cap_sel = 0xf,
.align90 = 0x61,
.g1_rx_selmuff = 0x3, .g2_rx_selmuff = 0x3,
.g3_rx_selmuff = 0x3,
.g1_rx_selmufi = 0x0, .g2_rx_selmufi = 0x0,
.g3_rx_selmufi = 0x3,
.g1_rx_selmupf = 0x1, .g2_rx_selmupf = 0x1,
.g3_rx_selmupf = 0x2,
.g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0,
.g3_rx_selmupi = 0x2,
.valid = 0x1
},
};
#endif /* __PHY_PORTING_LAYER_H */

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/*
* Copyright (C) 2018 Marvell International Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
* https://spdx.org/licenses
*/
#ifndef __MVEBU_DEF_H__
#define __MVEBU_DEF_H__
#include <a8k_plat_def.h>
/*
* CN-9130 has single CP0 inside the package and 2 additional one
* from MoChi interface. In case of db-9130-modular board the MCI interface
* is routed to:
* - on-board CP115 (MCI0)
* - extension board CP115 (MCI1)
*/
#define CP_COUNT CP_NUM
#define MVEBU_SOC_AP807 1
#define I2C_SPD_ADDR 0x53 /* Access SPD data */
#define I2C_SPD_P0_ADDR 0x36 /* Select SPD data page 0 */
#endif /* __MVEBU_DEF_H__ */

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#
# Copyright (C) 2018 Marvell International Ltd.
#
# SPDX-License-Identifier: BSD-3-Clause
# https://spdx.org/licenses
#
PCI_EP_SUPPORT := 0
CP_NUM := 1
$(eval $(call add_define,CP_NUM))
DOIMAGE_SEC := tools/doimage/secure/sec_img_7K.cfg
MARVELL_MOCHI_DRV := drivers/marvell/mochi/ap807_setup.c
BOARD_DIR := $(shell dirname $(lastword $(MAKEFILE_LIST)))
include plat/marvell/armada/a8k/common/a8k_common.mk
include plat/marvell/armada/common/marvell_common.mk