Merge pull request #1482 from sandrine-bailleux-arm/sb/fix-hcptr
Misc arch.h fixes and cleanup
This commit is contained in:
danh-arm
GitHub
commit
8ff0dfa79c
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@ -12,31 +12,31 @@
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/*******************************************************************************
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* MIDR bit definitions
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******************************************************************************/
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#define MIDR_IMPL_MASK 0xff
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#define MIDR_IMPL_SHIFT 24
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#define MIDR_VAR_SHIFT 20
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#define MIDR_VAR_BITS 4
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#define MIDR_REV_SHIFT 0
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#define MIDR_REV_BITS 4
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#define MIDR_PN_MASK 0xfff
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#define MIDR_PN_SHIFT 4
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#define MIDR_IMPL_MASK U(0xff)
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#define MIDR_IMPL_SHIFT U(24)
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#define MIDR_VAR_SHIFT U(20)
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#define MIDR_VAR_BITS U(4)
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#define MIDR_REV_SHIFT U(0)
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#define MIDR_REV_BITS U(4)
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#define MIDR_PN_MASK U(0xfff)
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#define MIDR_PN_SHIFT U(4)
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/*******************************************************************************
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* MPIDR macros
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******************************************************************************/
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#define MPIDR_MT_MASK (1 << 24)
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#define MPIDR_MT_MASK (U(1) << 24)
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#define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK
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#define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS)
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#define MPIDR_AFFINITY_BITS 8
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#define MPIDR_AFFLVL_MASK 0xff
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#define MPIDR_AFFLVL_SHIFT 3
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#define MPIDR_AFF0_SHIFT 0
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#define MPIDR_AFF1_SHIFT 8
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#define MPIDR_AFF2_SHIFT 16
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#define MPIDR_AFFINITY_MASK 0x00ffffff
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#define MPIDR_AFFLVL0 0
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#define MPIDR_AFFLVL1 1
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#define MPIDR_AFFLVL2 2
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#define MPIDR_AFFINITY_BITS U(8)
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#define MPIDR_AFFLVL_MASK U(0xff)
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#define MPIDR_AFFLVL_SHIFT U(3)
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#define MPIDR_AFF0_SHIFT U(0)
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#define MPIDR_AFF1_SHIFT U(8)
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#define MPIDR_AFF2_SHIFT U(16)
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#define MPIDR_AFFINITY_MASK U(0x00ffffff)
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#define MPIDR_AFFLVL0 U(0)
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#define MPIDR_AFFLVL1 U(1)
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#define MPIDR_AFFLVL2 U(2)
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#define MPIDR_AFFLVL0_VAL(mpidr) \
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(((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK)
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@ -44,39 +44,39 @@
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(((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK)
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#define MPIDR_AFFLVL2_VAL(mpidr) \
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(((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK)
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#define MPIDR_AFFLVL3_VAL(mpidr) 0
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#define MPIDR_AFFLVL3_VAL(mpidr) U(0)
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/*
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* The MPIDR_MAX_AFFLVL count starts from 0. Take care to
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* add one while using this macro to define array sizes.
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*/
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#define MPIDR_MAX_AFFLVL 2
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#define MPIDR_MAX_AFFLVL U(2)
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/* Data Cache set/way op type defines */
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#define DC_OP_ISW 0x0
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#define DC_OP_CISW 0x1
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#define DC_OP_CSW 0x2
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#define DC_OP_ISW U(0x0)
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#define DC_OP_CISW U(0x1)
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#define DC_OP_CSW U(0x2)
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/*******************************************************************************
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* Generic timer memory mapped registers & offsets
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******************************************************************************/
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#define CNTCR_OFF 0x000
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#define CNTFID_OFF 0x020
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#define CNTCR_OFF U(0x000)
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#define CNTFID_OFF U(0x020)
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#define CNTCR_EN (1 << 0)
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#define CNTCR_HDBG (1 << 1)
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#define CNTCR_EN (U(1) << 0)
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#define CNTCR_HDBG (U(1) << 1)
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#define CNTCR_FCREQ(x) ((x) << 8)
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/*******************************************************************************
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* System register bit definitions
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******************************************************************************/
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/* CLIDR definitions */
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#define LOUIS_SHIFT 21
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#define LOC_SHIFT 24
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#define CLIDR_FIELD_WIDTH 3
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#define LOUIS_SHIFT U(21)
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#define LOC_SHIFT U(24)
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#define CLIDR_FIELD_WIDTH U(3)
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/* CSSELR definitions */
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#define LEVEL_SHIFT 1
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#define LEVEL_SHIFT U(1)
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/* ID_PFR0 definitions */
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#define ID_PFR0_AMU_SHIFT U(20)
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@ -84,184 +84,185 @@
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#define ID_PFR0_AMU_MASK U(0xf)
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/* ID_PFR1 definitions */
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#define ID_PFR1_VIRTEXT_SHIFT 12
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#define ID_PFR1_VIRTEXT_MASK 0xf
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#define ID_PFR1_VIRTEXT_SHIFT U(12)
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#define ID_PFR1_VIRTEXT_MASK U(0xf)
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#define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \
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& ID_PFR1_VIRTEXT_MASK)
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#define ID_PFR1_GIC_SHIFT 28
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#define ID_PFR1_GIC_MASK 0xf
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#define ID_PFR1_GIC_SHIFT U(28)
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#define ID_PFR1_GIC_MASK U(0xf)
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/* SCTLR definitions */
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#define SCTLR_RES1_DEF ((1 << 23) | (1 << 22) | (1 << 4) | (1 << 3))
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#define SCTLR_RES1_DEF ((U(1) << 23) | (U(1) << 22) | (U(1) << 4) | \
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(U(1) << 3))
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#if ARM_ARCH_MAJOR == 7
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#define SCTLR_RES1 SCTLR_RES1_DEF
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#else
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#define SCTLR_RES1 (SCTLR_RES1_DEF | (1 << 11))
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#define SCTLR_RES1 (SCTLR_RES1_DEF | (U(1) << 11))
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#endif
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#define SCTLR_M_BIT (1 << 0)
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#define SCTLR_A_BIT (1 << 1)
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#define SCTLR_C_BIT (1 << 2)
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#define SCTLR_CP15BEN_BIT (1 << 5)
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#define SCTLR_ITD_BIT (1 << 7)
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#define SCTLR_Z_BIT (1 << 11)
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#define SCTLR_I_BIT (1 << 12)
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#define SCTLR_V_BIT (1 << 13)
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#define SCTLR_RR_BIT (1 << 14)
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#define SCTLR_NTWI_BIT (1 << 16)
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#define SCTLR_NTWE_BIT (1 << 18)
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#define SCTLR_WXN_BIT (1 << 19)
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#define SCTLR_UWXN_BIT (1 << 20)
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#define SCTLR_EE_BIT (1 << 25)
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#define SCTLR_TRE_BIT (1 << 28)
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#define SCTLR_AFE_BIT (1 << 29)
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#define SCTLR_TE_BIT (1 << 30)
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#define SCTLR_M_BIT (U(1) << 0)
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#define SCTLR_A_BIT (U(1) << 1)
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#define SCTLR_C_BIT (U(1) << 2)
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#define SCTLR_CP15BEN_BIT (U(1) << 5)
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#define SCTLR_ITD_BIT (U(1) << 7)
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#define SCTLR_Z_BIT (U(1) << 11)
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#define SCTLR_I_BIT (U(1) << 12)
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#define SCTLR_V_BIT (U(1) << 13)
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#define SCTLR_RR_BIT (U(1) << 14)
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#define SCTLR_NTWI_BIT (U(1) << 16)
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#define SCTLR_NTWE_BIT (U(1) << 18)
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#define SCTLR_WXN_BIT (U(1) << 19)
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#define SCTLR_UWXN_BIT (U(1) << 20)
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#define SCTLR_EE_BIT (U(1) << 25)
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#define SCTLR_TRE_BIT (U(1) << 28)
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#define SCTLR_AFE_BIT (U(1) << 29)
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#define SCTLR_TE_BIT (U(1) << 30)
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#define SCTLR_RESET_VAL (SCTLR_RES1 | SCTLR_NTWE_BIT | \
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SCTLR_NTWI_BIT | SCTLR_CP15BEN_BIT)
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/* SDCR definitions */
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#define SDCR_SPD(x) ((x) << 14)
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#define SDCR_SPD_LEGACY 0x0
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#define SDCR_SPD_DISABLE 0x2
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#define SDCR_SPD_ENABLE 0x3
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#define SDCR_RESET_VAL 0x0
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#define SDCR_SPD_LEGACY U(0x0)
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#define SDCR_SPD_DISABLE U(0x2)
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#define SDCR_SPD_ENABLE U(0x3)
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#define SDCR_RESET_VAL U(0x0)
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#if !ERROR_DEPRECATED
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#define SDCR_DEF_VAL SDCR_SPD(SDCR_SPD_DISABLE)
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#endif
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/* HSCTLR definitions */
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#define HSCTLR_RES1 ((1 << 29) | (1 << 28) | (1 << 23) | (1 << 22) \
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| (1 << 18) | (1 << 16) | (1 << 11) | (1 << 4) \
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| (1 << 3))
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#define HSCTLR_M_BIT (1 << 0)
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#define HSCTLR_A_BIT (1 << 1)
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#define HSCTLR_C_BIT (1 << 2)
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#define HSCTLR_CP15BEN_BIT (1 << 5)
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#define HSCTLR_ITD_BIT (1 << 7)
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#define HSCTLR_SED_BIT (1 << 8)
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#define HSCTLR_I_BIT (1 << 12)
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#define HSCTLR_WXN_BIT (1 << 19)
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#define HSCTLR_EE_BIT (1 << 25)
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#define HSCTLR_TE_BIT (1 << 30)
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#define HSCTLR_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
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(U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
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(U(1) << 11) | (U(1) << 4) | (U(1) << 3))
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#define HSCTLR_M_BIT (U(1) << 0)
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#define HSCTLR_A_BIT (U(1) << 1)
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#define HSCTLR_C_BIT (U(1) << 2)
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#define HSCTLR_CP15BEN_BIT (U(1) << 5)
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#define HSCTLR_ITD_BIT (U(1) << 7)
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#define HSCTLR_SED_BIT (U(1) << 8)
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#define HSCTLR_I_BIT (U(1) << 12)
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#define HSCTLR_WXN_BIT (U(1) << 19)
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#define HSCTLR_EE_BIT (U(1) << 25)
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#define HSCTLR_TE_BIT (U(1) << 30)
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/* CPACR definitions */
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#define CPACR_FPEN(x) ((x) << 20)
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#define CPACR_FP_TRAP_PL0 0x1
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#define CPACR_FP_TRAP_ALL 0x2
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#define CPACR_FP_TRAP_NONE 0x3
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#define CPACR_FPEN(x) ((x) << 20)
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#define CPACR_FP_TRAP_PL0 U(0x1)
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#define CPACR_FP_TRAP_ALL U(0x2)
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#define CPACR_FP_TRAP_NONE U(0x3)
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/* SCR definitions */
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#define SCR_TWE_BIT (1 << 13)
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#define SCR_TWI_BIT (1 << 12)
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#define SCR_SIF_BIT (1 << 9)
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#define SCR_HCE_BIT (1 << 8)
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#define SCR_SCD_BIT (1 << 7)
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#define SCR_NET_BIT (1 << 6)
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#define SCR_AW_BIT (1 << 5)
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#define SCR_FW_BIT (1 << 4)
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#define SCR_EA_BIT (1 << 3)
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#define SCR_FIQ_BIT (1 << 2)
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#define SCR_IRQ_BIT (1 << 1)
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#define SCR_NS_BIT (1 << 0)
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#define SCR_VALID_BIT_MASK 0x33ff
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#define SCR_RESET_VAL 0x0
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#define SCR_TWE_BIT (U(1) << 13)
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#define SCR_TWI_BIT (U(1) << 12)
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#define SCR_SIF_BIT (U(1) << 9)
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#define SCR_HCE_BIT (U(1) << 8)
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#define SCR_SCD_BIT (U(1) << 7)
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#define SCR_NET_BIT (U(1) << 6)
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#define SCR_AW_BIT (U(1) << 5)
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#define SCR_FW_BIT (U(1) << 4)
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#define SCR_EA_BIT (U(1) << 3)
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#define SCR_FIQ_BIT (U(1) << 2)
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#define SCR_IRQ_BIT (U(1) << 1)
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#define SCR_NS_BIT (U(1) << 0)
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#define SCR_VALID_BIT_MASK U(0x33ff)
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#define SCR_RESET_VAL U(0x0)
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#define GET_NS_BIT(scr) ((scr) & SCR_NS_BIT)
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/* HCR definitions */
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#define HCR_AMO_BIT (1 << 5)
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#define HCR_IMO_BIT (1 << 4)
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#define HCR_FMO_BIT (1 << 3)
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#define HCR_RESET_VAL 0x0
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#define HCR_AMO_BIT (U(1) << 5)
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#define HCR_IMO_BIT (U(1) << 4)
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#define HCR_FMO_BIT (U(1) << 3)
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#define HCR_RESET_VAL U(0x0)
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/* CNTHCTL definitions */
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#define CNTHCTL_RESET_VAL 0x0
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#define PL1PCEN_BIT (1 << 1)
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#define PL1PCTEN_BIT (1 << 0)
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#define CNTHCTL_RESET_VAL U(0x0)
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#define PL1PCEN_BIT (U(1) << 1)
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#define PL1PCTEN_BIT (U(1) << 0)
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/* CNTKCTL definitions */
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#define PL0PTEN_BIT (1 << 9)
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#define PL0VTEN_BIT (1 << 8)
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#define PL0PCTEN_BIT (1 << 0)
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#define PL0VCTEN_BIT (1 << 1)
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#define EVNTEN_BIT (1 << 2)
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#define EVNTDIR_BIT (1 << 3)
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#define EVNTI_SHIFT 4
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#define EVNTI_MASK 0xf
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#define PL0PTEN_BIT (U(1) << 9)
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#define PL0VTEN_BIT (U(1) << 8)
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#define PL0PCTEN_BIT (U(1) << 0)
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#define PL0VCTEN_BIT (U(1) << 1)
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#define EVNTEN_BIT (U(1) << 2)
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#define EVNTDIR_BIT (U(1) << 3)
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#define EVNTI_SHIFT U(4)
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#define EVNTI_MASK U(0xf)
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/* HCPTR definitions */
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#define HCPTR_RES1 ((1 << 13) | (1<<12) | 0x3ff)
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#define TCPAC_BIT (1 << 31)
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#define TAM_BIT (1 << 30)
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#define TTA_BIT (1 << 20)
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#define TCP11_BIT (1 << 10)
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#define TCP10_BIT (1 << 10)
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#define HCPTR_RES1 ((U(1) << 13) | (U(1) << 12) | U(0x3ff))
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#define TCPAC_BIT (U(1) << 31)
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#define TAM_BIT (U(1) << 30)
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#define TTA_BIT (U(1) << 20)
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#define TCP11_BIT (U(1) << 11)
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#define TCP10_BIT (U(1) << 10)
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#define HCPTR_RESET_VAL HCPTR_RES1
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/* VTTBR defintions */
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#define VTTBR_RESET_VAL ULL(0x0)
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#define VTTBR_VMID_MASK ULL(0xff)
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#define VTTBR_VMID_SHIFT 48
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#define VTTBR_BADDR_MASK 0xffffffffffff
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#define VTTBR_BADDR_SHIFT 0
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#define VTTBR_VMID_SHIFT U(48)
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#define VTTBR_BADDR_MASK ULL(0xffffffffffff)
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#define VTTBR_BADDR_SHIFT U(0)
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/* HDCR definitions */
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#define HDCR_RESET_VAL 0x0
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#define HDCR_RESET_VAL U(0x0)
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/* HSTR definitions */
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#define HSTR_RESET_VAL 0x0
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#define HSTR_RESET_VAL U(0x0)
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/* CNTHP_CTL definitions */
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#define CNTHP_CTL_RESET_VAL 0x0
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#define CNTHP_CTL_RESET_VAL U(0x0)
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/* NASCR definitions */
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#define NSASEDIS_BIT (1 << 15)
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#define NSTRCDIS_BIT (1 << 20)
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#define NSASEDIS_BIT (U(1) << 15)
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#define NSTRCDIS_BIT (U(1) << 20)
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/* NOTE: correct typo in the definitions */
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#if !ERROR_DEPRECATED
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#define NASCR_CP11_BIT (1 << 11)
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#define NASCR_CP10_BIT (1 << 10)
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#define NASCR_CP11_BIT (U(1) << 11)
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#define NASCR_CP10_BIT (U(1) << 10)
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#endif
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#define NSACR_CP11_BIT (1 << 11)
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#define NSACR_CP10_BIT (1 << 10)
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#define NSACR_IMP_DEF_MASK (0x7 << 16)
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#define NSACR_CP11_BIT (U(1) << 11)
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#define NSACR_CP10_BIT (U(1) << 10)
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#define NSACR_IMP_DEF_MASK (U(0x7) << 16)
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#define NSACR_ENABLE_FP_ACCESS (NSACR_CP11_BIT | NSACR_CP10_BIT)
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#define NSACR_RESET_VAL 0x0
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#define NSACR_RESET_VAL U(0x0)
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/* CPACR definitions */
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#define ASEDIS_BIT (1 << 31)
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#define TRCDIS_BIT (1 << 28)
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#define CPACR_CP11_SHIFT 22
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#define CPACR_CP10_SHIFT 20
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#define CPACR_ENABLE_FP_ACCESS (0x3 << CPACR_CP11_SHIFT |\
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0x3 << CPACR_CP10_SHIFT)
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#define CPACR_RESET_VAL 0x0
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#define ASEDIS_BIT (U(1) << 31)
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#define TRCDIS_BIT (U(1) << 28)
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#define CPACR_CP11_SHIFT U(22)
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#define CPACR_CP10_SHIFT U(20)
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#define CPACR_ENABLE_FP_ACCESS ((U(0x3) << CPACR_CP11_SHIFT) |\
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(U(0x3) << CPACR_CP10_SHIFT))
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#define CPACR_RESET_VAL U(0x0)
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/* FPEXC definitions */
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#define FPEXC_RES1 ((1 << 10) | (1 << 9) | (1 << 8))
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#define FPEXC_EN_BIT (1 << 30)
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#define FPEXC_RES1 ((U(1) << 10) | (U(1) << 9) | (U(1) << 8))
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#define FPEXC_EN_BIT (U(1) << 30)
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||||
#define FPEXC_RESET_VAL FPEXC_RES1
|
||||
|
||||
/* SPSR/CPSR definitions */
|
||||
#define SPSR_FIQ_BIT (1 << 0)
|
||||
#define SPSR_IRQ_BIT (1 << 1)
|
||||
#define SPSR_ABT_BIT (1 << 2)
|
||||
#define SPSR_AIF_SHIFT 6
|
||||
#define SPSR_AIF_MASK 0x7
|
||||
#define SPSR_FIQ_BIT (U(1) << 0)
|
||||
#define SPSR_IRQ_BIT (U(1) << 1)
|
||||
#define SPSR_ABT_BIT (U(1) << 2)
|
||||
#define SPSR_AIF_SHIFT U(6)
|
||||
#define SPSR_AIF_MASK U(0x7)
|
||||
|
||||
#define SPSR_E_SHIFT 9
|
||||
#define SPSR_E_MASK 0x1
|
||||
#define SPSR_E_LITTLE 0
|
||||
#define SPSR_E_BIG 1
|
||||
#define SPSR_E_SHIFT U(9)
|
||||
#define SPSR_E_MASK U(0x1)
|
||||
#define SPSR_E_LITTLE U(0)
|
||||
#define SPSR_E_BIG U(1)
|
||||
|
||||
#define SPSR_T_SHIFT 5
|
||||
#define SPSR_T_MASK 0x1
|
||||
#define SPSR_T_ARM 0
|
||||
#define SPSR_T_THUMB 1
|
||||
|
||||
#define SPSR_MODE_SHIFT 0
|
||||
#define SPSR_MODE_MASK 0x7
|
||||
#define SPSR_T_SHIFT U(5)
|
||||
#define SPSR_T_MASK U(0x1)
|
||||
#define SPSR_T_ARM U(0)
|
||||
#define SPSR_T_THUMB U(1)
|
||||
|
||||
#define SPSR_MODE_SHIFT U(0)
|
||||
#define SPSR_MODE_MASK U(0x7)
|
||||
|
||||
#define DISABLE_ALL_EXCEPTIONS \
|
||||
(SPSR_FIQ_BIT | SPSR_IRQ_BIT | SPSR_ABT_BIT)
|
||||
|
|
@ -270,63 +271,63 @@
|
|||
* TTBCR definitions
|
||||
*/
|
||||
/* The ARM Trusted Firmware uses the long descriptor format */
|
||||
#define TTBCR_EAE_BIT (1 << 31)
|
||||
#define TTBCR_EAE_BIT (U(1) << 31)
|
||||
|
||||
#define TTBCR_SH1_NON_SHAREABLE (0x0 << 28)
|
||||
#define TTBCR_SH1_OUTER_SHAREABLE (0x2 << 28)
|
||||
#define TTBCR_SH1_INNER_SHAREABLE (0x3 << 28)
|
||||
#define TTBCR_SH1_NON_SHAREABLE (U(0x0) << 28)
|
||||
#define TTBCR_SH1_OUTER_SHAREABLE (U(0x2) << 28)
|
||||
#define TTBCR_SH1_INNER_SHAREABLE (U(0x3) << 28)
|
||||
|
||||
#define TTBCR_RGN1_OUTER_NC (0x0 << 26)
|
||||
#define TTBCR_RGN1_OUTER_WBA (0x1 << 26)
|
||||
#define TTBCR_RGN1_OUTER_WT (0x2 << 26)
|
||||
#define TTBCR_RGN1_OUTER_WBNA (0x3 << 26)
|
||||
#define TTBCR_RGN1_OUTER_NC (U(0x0) << 26)
|
||||
#define TTBCR_RGN1_OUTER_WBA (U(0x1) << 26)
|
||||
#define TTBCR_RGN1_OUTER_WT (U(0x2) << 26)
|
||||
#define TTBCR_RGN1_OUTER_WBNA (U(0x3) << 26)
|
||||
|
||||
#define TTBCR_RGN1_INNER_NC (0x0 << 24)
|
||||
#define TTBCR_RGN1_INNER_WBA (0x1 << 24)
|
||||
#define TTBCR_RGN1_INNER_WT (0x2 << 24)
|
||||
#define TTBCR_RGN1_INNER_WBNA (0x3 << 24)
|
||||
#define TTBCR_RGN1_INNER_NC (U(0x0) << 24)
|
||||
#define TTBCR_RGN1_INNER_WBA (U(0x1) << 24)
|
||||
#define TTBCR_RGN1_INNER_WT (U(0x2) << 24)
|
||||
#define TTBCR_RGN1_INNER_WBNA (U(0x3) << 24)
|
||||
|
||||
#define TTBCR_EPD1_BIT (1 << 23)
|
||||
#define TTBCR_A1_BIT (1 << 22)
|
||||
#define TTBCR_EPD1_BIT (U(1) << 23)
|
||||
#define TTBCR_A1_BIT (U(1) << 22)
|
||||
|
||||
#define TTBCR_T1SZ_SHIFT 16
|
||||
#define TTBCR_T1SZ_MASK (0x7)
|
||||
#define TTBCR_TxSZ_MIN 0
|
||||
#define TTBCR_TxSZ_MAX 7
|
||||
#define TTBCR_T1SZ_SHIFT U(16)
|
||||
#define TTBCR_T1SZ_MASK U(0x7)
|
||||
#define TTBCR_TxSZ_MIN U(0)
|
||||
#define TTBCR_TxSZ_MAX U(7)
|
||||
|
||||
#define TTBCR_SH0_NON_SHAREABLE (0x0 << 12)
|
||||
#define TTBCR_SH0_OUTER_SHAREABLE (0x2 << 12)
|
||||
#define TTBCR_SH0_INNER_SHAREABLE (0x3 << 12)
|
||||
#define TTBCR_SH0_NON_SHAREABLE (U(0x0) << 12)
|
||||
#define TTBCR_SH0_OUTER_SHAREABLE (U(0x2) << 12)
|
||||
#define TTBCR_SH0_INNER_SHAREABLE (U(0x3) << 12)
|
||||
|
||||
#define TTBCR_RGN0_OUTER_NC (0x0 << 10)
|
||||
#define TTBCR_RGN0_OUTER_WBA (0x1 << 10)
|
||||
#define TTBCR_RGN0_OUTER_WT (0x2 << 10)
|
||||
#define TTBCR_RGN0_OUTER_WBNA (0x3 << 10)
|
||||
#define TTBCR_RGN0_OUTER_NC (U(0x0) << 10)
|
||||
#define TTBCR_RGN0_OUTER_WBA (U(0x1) << 10)
|
||||
#define TTBCR_RGN0_OUTER_WT (U(0x2) << 10)
|
||||
#define TTBCR_RGN0_OUTER_WBNA (U(0x3) << 10)
|
||||
|
||||
#define TTBCR_RGN0_INNER_NC (0x0 << 8)
|
||||
#define TTBCR_RGN0_INNER_WBA (0x1 << 8)
|
||||
#define TTBCR_RGN0_INNER_WT (0x2 << 8)
|
||||
#define TTBCR_RGN0_INNER_WBNA (0x3 << 8)
|
||||
#define TTBCR_RGN0_INNER_NC (U(0x0) << 8)
|
||||
#define TTBCR_RGN0_INNER_WBA (U(0x1) << 8)
|
||||
#define TTBCR_RGN0_INNER_WT (U(0x2) << 8)
|
||||
#define TTBCR_RGN0_INNER_WBNA (U(0x3) << 8)
|
||||
|
||||
#define TTBCR_EPD0_BIT (1 << 7)
|
||||
#define TTBCR_T0SZ_SHIFT 0
|
||||
#define TTBCR_T0SZ_MASK (0x7)
|
||||
#define TTBCR_EPD0_BIT (U(1) << 7)
|
||||
#define TTBCR_T0SZ_SHIFT U(0)
|
||||
#define TTBCR_T0SZ_MASK U(0x7)
|
||||
|
||||
#define MODE_RW_SHIFT 0x4
|
||||
#define MODE_RW_MASK 0x1
|
||||
#define MODE_RW_32 0x1
|
||||
#define MODE_RW_SHIFT U(0x4)
|
||||
#define MODE_RW_MASK U(0x1)
|
||||
#define MODE_RW_32 U(0x1)
|
||||
|
||||
#define MODE32_SHIFT 0
|
||||
#define MODE32_MASK 0x1f
|
||||
#define MODE32_usr 0x10
|
||||
#define MODE32_fiq 0x11
|
||||
#define MODE32_irq 0x12
|
||||
#define MODE32_svc 0x13
|
||||
#define MODE32_mon 0x16
|
||||
#define MODE32_abt 0x17
|
||||
#define MODE32_hyp 0x1a
|
||||
#define MODE32_und 0x1b
|
||||
#define MODE32_sys 0x1f
|
||||
#define MODE32_SHIFT U(0)
|
||||
#define MODE32_MASK U(0x1f)
|
||||
#define MODE32_usr U(0x10)
|
||||
#define MODE32_fiq U(0x11)
|
||||
#define MODE32_irq U(0x12)
|
||||
#define MODE32_svc U(0x13)
|
||||
#define MODE32_mon U(0x16)
|
||||
#define MODE32_abt U(0x17)
|
||||
#define MODE32_hyp U(0x1a)
|
||||
#define MODE32_und U(0x1b)
|
||||
#define MODE32_sys U(0x1f)
|
||||
|
||||
#define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK)
|
||||
|
||||
|
|
@ -340,39 +341,39 @@
|
|||
/*
|
||||
* TTBR definitions
|
||||
*/
|
||||
#define TTBR_CNP_BIT U(0x1)
|
||||
#define TTBR_CNP_BIT ULL(0x1)
|
||||
|
||||
/*
|
||||
* CTR definitions
|
||||
*/
|
||||
#define CTR_CWG_SHIFT 24
|
||||
#define CTR_CWG_MASK 0xf
|
||||
#define CTR_ERG_SHIFT 20
|
||||
#define CTR_ERG_MASK 0xf
|
||||
#define CTR_DMINLINE_SHIFT 16
|
||||
#define CTR_DMINLINE_WIDTH 4
|
||||
#define CTR_DMINLINE_MASK ((1 << 4) - 1)
|
||||
#define CTR_L1IP_SHIFT 14
|
||||
#define CTR_L1IP_MASK 0x3
|
||||
#define CTR_IMINLINE_SHIFT 0
|
||||
#define CTR_IMINLINE_MASK 0xf
|
||||
#define CTR_CWG_SHIFT U(24)
|
||||
#define CTR_CWG_MASK U(0xf)
|
||||
#define CTR_ERG_SHIFT U(20)
|
||||
#define CTR_ERG_MASK U(0xf)
|
||||
#define CTR_DMINLINE_SHIFT U(16)
|
||||
#define CTR_DMINLINE_WIDTH U(4)
|
||||
#define CTR_DMINLINE_MASK ((U(1) << 4) - U(1))
|
||||
#define CTR_L1IP_SHIFT U(14)
|
||||
#define CTR_L1IP_MASK U(0x3)
|
||||
#define CTR_IMINLINE_SHIFT U(0)
|
||||
#define CTR_IMINLINE_MASK U(0xf)
|
||||
|
||||
#define MAX_CACHE_LINE_SIZE 0x800 /* 2KB */
|
||||
#define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */
|
||||
|
||||
/* PMCR definitions */
|
||||
#define PMCR_N_SHIFT 11
|
||||
#define PMCR_N_MASK 0x1f
|
||||
#define PMCR_N_SHIFT U(11)
|
||||
#define PMCR_N_MASK U(0x1f)
|
||||
#define PMCR_N_BITS (PMCR_N_MASK << PMCR_N_SHIFT)
|
||||
#define PMCR_LC_BIT (1 << 6)
|
||||
#define PMCR_DP_BIT (1 << 5)
|
||||
#define PMCR_LC_BIT (U(1) << 6)
|
||||
#define PMCR_DP_BIT (U(1) << 5)
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions of register offsets, fields and macros for CPU system
|
||||
* instructions.
|
||||
******************************************************************************/
|
||||
|
||||
#define TLBI_ADDR_SHIFT 0
|
||||
#define TLBI_ADDR_MASK 0xFFFFF000
|
||||
#define TLBI_ADDR_SHIFT U(0)
|
||||
#define TLBI_ADDR_MASK U(0xFFFFF000)
|
||||
#define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK)
|
||||
|
||||
/*******************************************************************************
|
||||
|
|
@ -380,16 +381,16 @@
|
|||
* system level implementation of the Generic Timer.
|
||||
******************************************************************************/
|
||||
#define CNTCTLBASE_CNTFRQ U(0x0)
|
||||
#define CNTNSAR 0x4
|
||||
#define CNTNSAR U(0x4)
|
||||
#define CNTNSAR_NS_SHIFT(x) (x)
|
||||
|
||||
#define CNTACR_BASE(x) (0x40 + ((x) << 2))
|
||||
#define CNTACR_RPCT_SHIFT 0x0
|
||||
#define CNTACR_RVCT_SHIFT 0x1
|
||||
#define CNTACR_RFRQ_SHIFT 0x2
|
||||
#define CNTACR_RVOFF_SHIFT 0x3
|
||||
#define CNTACR_RWVT_SHIFT 0x4
|
||||
#define CNTACR_RWPT_SHIFT 0x5
|
||||
#define CNTACR_BASE(x) (U(0x40) + ((x) << 2))
|
||||
#define CNTACR_RPCT_SHIFT U(0x0)
|
||||
#define CNTACR_RVCT_SHIFT U(0x1)
|
||||
#define CNTACR_RFRQ_SHIFT U(0x2)
|
||||
#define CNTACR_RVOFF_SHIFT U(0x3)
|
||||
#define CNTACR_RWVT_SHIFT U(0x4)
|
||||
#define CNTACR_RWPT_SHIFT U(0x5)
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions of register offsets in the CNTBaseN Frame of the
|
||||
|
|
@ -399,7 +400,7 @@
|
|||
|
||||
/* MAIR macros */
|
||||
#define MAIR0_ATTR_SET(attr, index) ((attr) << ((index) << 3))
|
||||
#define MAIR1_ATTR_SET(attr, index) ((attr) << (((index) - 3) << 3))
|
||||
#define MAIR1_ATTR_SET(attr, index) ((attr) << (((index) - U(3)) << 3))
|
||||
|
||||
/* System register defines The format is: coproc, opt1, CRn, CRm, opt2 */
|
||||
#define SCR p15, 0, c1, c1, 0
|
||||
|
|
@ -537,9 +538,10 @@
|
|||
#define MAIR_NORM_WB_NTR_RA U(0xe)
|
||||
#define MAIR_NORM_WB_NTR_RWA U(0xf)
|
||||
|
||||
#define MAIR_NORM_OUTER_SHIFT 4
|
||||
#define MAIR_NORM_OUTER_SHIFT U(4)
|
||||
|
||||
#define MAKE_MAIR_NORMAL_MEMORY(inner, outer) ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT))
|
||||
#define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \
|
||||
((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT))
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions for system register interface to AMU for ARMv8.4 onwards
|
||||
|
|
|
|||
|
|
@ -26,29 +26,29 @@
|
|||
/*******************************************************************************
|
||||
* MPIDR macros
|
||||
******************************************************************************/
|
||||
#define MPIDR_MT_MASK (U(1) << 24)
|
||||
#define MPIDR_MT_MASK (ULL(1) << 24)
|
||||
#define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK
|
||||
#define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS)
|
||||
#define MPIDR_AFFINITY_BITS U(8)
|
||||
#define MPIDR_AFFLVL_MASK U(0xff)
|
||||
#define MPIDR_AFFLVL_MASK ULL(0xff)
|
||||
#define MPIDR_AFF0_SHIFT U(0)
|
||||
#define MPIDR_AFF1_SHIFT U(8)
|
||||
#define MPIDR_AFF2_SHIFT U(16)
|
||||
#define MPIDR_AFF3_SHIFT U(32)
|
||||
#define MPIDR_AFFINITY_MASK U(0xff00ffffff)
|
||||
#define MPIDR_AFFINITY_MASK ULL(0xff00ffffff)
|
||||
#define MPIDR_AFFLVL_SHIFT U(3)
|
||||
#define MPIDR_AFFLVL0 U(0)
|
||||
#define MPIDR_AFFLVL1 U(1)
|
||||
#define MPIDR_AFFLVL2 U(2)
|
||||
#define MPIDR_AFFLVL3 U(3)
|
||||
#define MPIDR_AFFLVL0 ULL(0x0)
|
||||
#define MPIDR_AFFLVL1 ULL(0x1)
|
||||
#define MPIDR_AFFLVL2 ULL(0x2)
|
||||
#define MPIDR_AFFLVL3 ULL(0x3)
|
||||
#define MPIDR_AFFLVL0_VAL(mpidr) \
|
||||
((mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK)
|
||||
(((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK)
|
||||
#define MPIDR_AFFLVL1_VAL(mpidr) \
|
||||
((mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK)
|
||||
(((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK)
|
||||
#define MPIDR_AFFLVL2_VAL(mpidr) \
|
||||
((mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK)
|
||||
(((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK)
|
||||
#define MPIDR_AFFLVL3_VAL(mpidr) \
|
||||
((mpidr >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK)
|
||||
(((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK)
|
||||
/*
|
||||
* The MPIDR_MAX_AFFLVL count starts from 0. Take care to
|
||||
* add one while using this macro to define array sizes.
|
||||
|
|
@ -57,7 +57,7 @@
|
|||
#define MPIDR_MAX_AFFLVL U(2)
|
||||
|
||||
/* Constant to highlight the assumption that MPIDR allocation starts from 0 */
|
||||
#define FIRST_MPIDR U(0)
|
||||
#define FIRST_MPIDR ULL(0)
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions for CPU system register interface to GICv3
|
||||
|
|
@ -100,7 +100,7 @@
|
|||
/* CSSELR definitions */
|
||||
#define LEVEL_SHIFT U(1)
|
||||
|
||||
/* D$ set/way op type defines */
|
||||
/* Data cache set/way op type defines */
|
||||
#define DCISW U(0x0)
|
||||
#define DCCISW U(0x1)
|
||||
#define DCCSW U(0x2)
|
||||
|
|
@ -112,31 +112,31 @@
|
|||
#define ID_AA64PFR0_EL3_SHIFT U(12)
|
||||
#define ID_AA64PFR0_AMU_SHIFT U(44)
|
||||
#define ID_AA64PFR0_AMU_LENGTH U(4)
|
||||
#define ID_AA64PFR0_AMU_MASK U(0xf)
|
||||
#define ID_AA64PFR0_ELX_MASK U(0xf)
|
||||
#define ID_AA64PFR0_AMU_MASK ULL(0xf)
|
||||
#define ID_AA64PFR0_ELX_MASK ULL(0xf)
|
||||
#define ID_AA64PFR0_SVE_SHIFT U(32)
|
||||
#define ID_AA64PFR0_SVE_MASK U(0xf)
|
||||
#define ID_AA64PFR0_SVE_MASK ULL(0xf)
|
||||
#define ID_AA64PFR0_SVE_LENGTH U(4)
|
||||
#define ID_AA64PFR0_CSV2_SHIFT U(56)
|
||||
#define ID_AA64PFR0_CSV2_MASK U(0xf)
|
||||
#define ID_AA64PFR0_CSV2_MASK ULL(0xf)
|
||||
#define ID_AA64PFR0_CSV2_LENGTH U(4)
|
||||
|
||||
/* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */
|
||||
#define ID_AA64DFR0_PMS_SHIFT U(32)
|
||||
#define ID_AA64DFR0_PMS_LENGTH U(4)
|
||||
#define ID_AA64DFR0_PMS_MASK U(0xf)
|
||||
#define ID_AA64DFR0_PMS_MASK ULL(0xf)
|
||||
|
||||
#define EL_IMPL_NONE U(0)
|
||||
#define EL_IMPL_A64ONLY U(1)
|
||||
#define EL_IMPL_A64_A32 U(2)
|
||||
#define EL_IMPL_NONE ULL(0)
|
||||
#define EL_IMPL_A64ONLY ULL(1)
|
||||
#define EL_IMPL_A64_A32 ULL(2)
|
||||
|
||||
#define ID_AA64PFR0_GIC_SHIFT U(24)
|
||||
#define ID_AA64PFR0_GIC_WIDTH U(4)
|
||||
#define ID_AA64PFR0_GIC_MASK ((U(1) << ID_AA64PFR0_GIC_WIDTH) - 1)
|
||||
#define ID_AA64PFR0_GIC_MASK ((ULL(1) << ID_AA64PFR0_GIC_WIDTH) - ULL(1))
|
||||
|
||||
/* ID_AA64MMFR0_EL1 definitions */
|
||||
#define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0)
|
||||
#define ID_AA64MMFR0_EL1_PARANGE_MASK U(0xf)
|
||||
#define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf)
|
||||
|
||||
#define PARANGE_0000 U(32)
|
||||
#define PARANGE_0001 U(36)
|
||||
|
|
@ -147,24 +147,24 @@
|
|||
#define PARANGE_0110 U(52)
|
||||
|
||||
#define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28)
|
||||
#define ID_AA64MMFR0_EL1_TGRAN4_MASK U(0xf)
|
||||
#define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED U(0x0)
|
||||
#define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED U(0xf)
|
||||
#define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf)
|
||||
#define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0)
|
||||
#define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED ULL(0xf)
|
||||
|
||||
#define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24)
|
||||
#define ID_AA64MMFR0_EL1_TGRAN64_MASK U(0xf)
|
||||
#define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED U(0x0)
|
||||
#define ID_AA64MMFR0_EL1_TGRAN64_NOT_SUPPORTED U(0xf)
|
||||
#define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf)
|
||||
#define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED ULL(0x0)
|
||||
#define ID_AA64MMFR0_EL1_TGRAN64_NOT_SUPPORTED ULL(0xf)
|
||||
|
||||
#define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20)
|
||||
#define ID_AA64MMFR0_EL1_TGRAN16_MASK U(0xf)
|
||||
#define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED U(0x1)
|
||||
#define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED U(0x0)
|
||||
#define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf)
|
||||
#define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1)
|
||||
#define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0)
|
||||
|
||||
/* ID_PFR1_EL1 definitions */
|
||||
#define ID_PFR1_VIRTEXT_SHIFT U(12)
|
||||
#define ID_PFR1_VIRTEXT_MASK U(0xf)
|
||||
#define GET_VIRT_EXT(id) ((id >> ID_PFR1_VIRTEXT_SHIFT) \
|
||||
#define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \
|
||||
& ID_PFR1_VIRTEXT_MASK)
|
||||
|
||||
/* SCTLR definitions */
|
||||
|
|
@ -278,9 +278,9 @@
|
|||
/* HCR definitions */
|
||||
#define HCR_RW_SHIFT U(31)
|
||||
#define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT)
|
||||
#define HCR_AMO_BIT (U(1) << 5)
|
||||
#define HCR_IMO_BIT (U(1) << 4)
|
||||
#define HCR_FMO_BIT (U(1) << 3)
|
||||
#define HCR_AMO_BIT (ULL(1) << 5)
|
||||
#define HCR_IMO_BIT (ULL(1) << 4)
|
||||
#define HCR_FMO_BIT (ULL(1) << 3)
|
||||
|
||||
/* ISR definitions */
|
||||
#define ISR_A_SHIFT U(8)
|
||||
|
|
@ -367,16 +367,16 @@
|
|||
#define TCR_EL1_IPS_SHIFT U(32)
|
||||
#define TCR_EL3_PS_SHIFT U(16)
|
||||
|
||||
#define TCR_TxSZ_MIN U(16)
|
||||
#define TCR_TxSZ_MAX U(39)
|
||||
#define TCR_TxSZ_MIN ULL(16)
|
||||
#define TCR_TxSZ_MAX ULL(39)
|
||||
|
||||
/* (internal) physical address size bits in EL3/EL1 */
|
||||
#define TCR_PS_BITS_4GB U(0x0)
|
||||
#define TCR_PS_BITS_64GB U(0x1)
|
||||
#define TCR_PS_BITS_1TB U(0x2)
|
||||
#define TCR_PS_BITS_4TB U(0x3)
|
||||
#define TCR_PS_BITS_16TB U(0x4)
|
||||
#define TCR_PS_BITS_256TB U(0x5)
|
||||
#define TCR_PS_BITS_4GB ULL(0x0)
|
||||
#define TCR_PS_BITS_64GB ULL(0x1)
|
||||
#define TCR_PS_BITS_1TB ULL(0x2)
|
||||
#define TCR_PS_BITS_4TB ULL(0x3)
|
||||
#define TCR_PS_BITS_16TB ULL(0x4)
|
||||
#define TCR_PS_BITS_256TB ULL(0x5)
|
||||
|
||||
#define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000)
|
||||
#define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000)
|
||||
|
|
@ -385,28 +385,28 @@
|
|||
#define ADDR_MASK_36_TO_39 ULL(0x000000F000000000)
|
||||
#define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000)
|
||||
|
||||
#define TCR_RGN_INNER_NC (U(0x0) << 8)
|
||||
#define TCR_RGN_INNER_WBA (U(0x1) << 8)
|
||||
#define TCR_RGN_INNER_WT (U(0x2) << 8)
|
||||
#define TCR_RGN_INNER_WBNA (U(0x3) << 8)
|
||||
#define TCR_RGN_INNER_NC (ULL(0x0) << 8)
|
||||
#define TCR_RGN_INNER_WBA (ULL(0x1) << 8)
|
||||
#define TCR_RGN_INNER_WT (ULL(0x2) << 8)
|
||||
#define TCR_RGN_INNER_WBNA (ULL(0x3) << 8)
|
||||
|
||||
#define TCR_RGN_OUTER_NC (U(0x0) << 10)
|
||||
#define TCR_RGN_OUTER_WBA (U(0x1) << 10)
|
||||
#define TCR_RGN_OUTER_WT (U(0x2) << 10)
|
||||
#define TCR_RGN_OUTER_WBNA (U(0x3) << 10)
|
||||
#define TCR_RGN_OUTER_NC (ULL(0x0) << 10)
|
||||
#define TCR_RGN_OUTER_WBA (ULL(0x1) << 10)
|
||||
#define TCR_RGN_OUTER_WT (ULL(0x2) << 10)
|
||||
#define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10)
|
||||
|
||||
#define TCR_SH_NON_SHAREABLE (U(0x0) << 12)
|
||||
#define TCR_SH_OUTER_SHAREABLE (U(0x2) << 12)
|
||||
#define TCR_SH_INNER_SHAREABLE (U(0x3) << 12)
|
||||
#define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12)
|
||||
#define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12)
|
||||
#define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12)
|
||||
|
||||
#define TCR_TG0_SHIFT U(14)
|
||||
#define TCR_TG0_MASK U(3)
|
||||
#define TCR_TG0_MASK ULL(3)
|
||||
#define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT)
|
||||
#define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT)
|
||||
#define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT)
|
||||
|
||||
#define TCR_EPD0_BIT (U(1) << 7)
|
||||
#define TCR_EPD1_BIT (U(1) << 23)
|
||||
#define TCR_EPD0_BIT (ULL(1) << 7)
|
||||
#define TCR_EPD1_BIT (ULL(1) << 23)
|
||||
|
||||
#define MODE_SP_SHIFT U(0x0)
|
||||
#define MODE_SP_MASK U(0x1)
|
||||
|
|
@ -458,7 +458,7 @@
|
|||
/*
|
||||
* TTBR Definitions
|
||||
*/
|
||||
#define TTBR_CNP_BIT 0x1
|
||||
#define TTBR_CNP_BIT ULL(0x1)
|
||||
|
||||
/*
|
||||
* CTR_EL0 definitions
|
||||
|
|
@ -639,15 +639,16 @@
|
|||
#define MAIR_NORM_WB_NTR_RA ULL(0xe)
|
||||
#define MAIR_NORM_WB_NTR_RWA ULL(0xf)
|
||||
|
||||
#define MAIR_NORM_OUTER_SHIFT 4
|
||||
#define MAIR_NORM_OUTER_SHIFT U(4)
|
||||
|
||||
#define MAKE_MAIR_NORMAL_MEMORY(inner, outer) ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT))
|
||||
#define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \
|
||||
((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT))
|
||||
|
||||
/* PAR_EL1 fields */
|
||||
#define PAR_F_SHIFT 0
|
||||
#define PAR_F_MASK 1
|
||||
#define PAR_ADDR_SHIFT 12
|
||||
#define PAR_ADDR_MASK (BIT(40) - 1) /* 40-bits-wide page address */
|
||||
#define PAR_F_SHIFT U(0)
|
||||
#define PAR_F_MASK ULL(0x1)
|
||||
#define PAR_ADDR_SHIFT U(12)
|
||||
#define PAR_ADDR_MASK (BIT(40) - ULL(1)) /* 40-bits-wide page address */
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions for system register interface to SPE
|
||||
|
|
@ -723,10 +724,10 @@
|
|||
* RAS system registers
|
||||
*******************************************************************************/
|
||||
#define DISR_EL1 S3_0_C12_C1_1
|
||||
#define DISR_A_BIT 31
|
||||
#define DISR_A_BIT U(31)
|
||||
|
||||
#define ERRIDR_EL1 S3_0_C5_C3_0
|
||||
#define ERRIDR_MASK 0xffff
|
||||
#define ERRIDR_MASK U(0xffff)
|
||||
|
||||
#define ERRSELR_EL1 S3_0_C5_C3_1
|
||||
|
||||
|
|
|
|||
|
|
@ -14,30 +14,30 @@ void trace_power_flow(unsigned long mpidr, unsigned char mode)
|
|||
{
|
||||
switch (mode) {
|
||||
case CPU_UP:
|
||||
trace_log("core %ld:%ld ON\n",
|
||||
trace_log("core %lld:%lld ON\n",
|
||||
(mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS,
|
||||
(mpidr & MPIDR_CPU_MASK));
|
||||
break;
|
||||
case CPU_DOWN:
|
||||
trace_log("core %ld:%ld OFF\n",
|
||||
trace_log("core %lld:%lld OFF\n",
|
||||
(mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS,
|
||||
(mpidr & MPIDR_CPU_MASK));
|
||||
break;
|
||||
case CPU_SUSPEND:
|
||||
trace_log("core %ld:%ld SUSPEND\n",
|
||||
trace_log("core %lld:%lld SUSPEND\n",
|
||||
(mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS,
|
||||
(mpidr & MPIDR_CPU_MASK));
|
||||
break;
|
||||
case CLUSTER_UP:
|
||||
trace_log("cluster %ld ON\n",
|
||||
trace_log("cluster %lld ON\n",
|
||||
(mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS);
|
||||
break;
|
||||
case CLUSTER_DOWN:
|
||||
trace_log("cluster %ld OFF\n",
|
||||
trace_log("cluster %lld OFF\n",
|
||||
(mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS);
|
||||
break;
|
||||
case CLUSTER_SUSPEND:
|
||||
trace_log("cluster %ld SUSPEND\n",
|
||||
trace_log("cluster %lld SUSPEND\n",
|
||||
(mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS);
|
||||
break;
|
||||
default:
|
||||
|
|
|
|||
|
|
@ -14,30 +14,30 @@ void trace_power_flow(unsigned long mpidr, unsigned char mode)
|
|||
{
|
||||
switch (mode) {
|
||||
case CPU_UP:
|
||||
trace_log("core %ld:%ld ON\n",
|
||||
trace_log("core %lld:%lld ON\n",
|
||||
(mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS,
|
||||
(mpidr & MPIDR_CPU_MASK));
|
||||
break;
|
||||
case CPU_DOWN:
|
||||
trace_log("core %ld:%ld OFF\n",
|
||||
trace_log("core %lld:%lld OFF\n",
|
||||
(mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS,
|
||||
(mpidr & MPIDR_CPU_MASK));
|
||||
break;
|
||||
case CPU_SUSPEND:
|
||||
trace_log("core %ld:%ld SUSPEND\n",
|
||||
trace_log("core %lld:%lld SUSPEND\n",
|
||||
(mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS,
|
||||
(mpidr & MPIDR_CPU_MASK));
|
||||
break;
|
||||
case CLUSTER_UP:
|
||||
trace_log("cluster %ld ON\n",
|
||||
trace_log("cluster %lld ON\n",
|
||||
(mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS);
|
||||
break;
|
||||
case CLUSTER_DOWN:
|
||||
trace_log("cluster %ld OFF\n",
|
||||
trace_log("cluster %lld OFF\n",
|
||||
(mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS);
|
||||
break;
|
||||
case CLUSTER_SUSPEND:
|
||||
trace_log("cluster %ld SUSPEND\n",
|
||||
trace_log("cluster %lld SUSPEND\n",
|
||||
(mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS);
|
||||
break;
|
||||
default:
|
||||
|
|
|
|||
Loading…
Reference in New Issue