From b662232d189af5289c8810c628da1640b70ae352 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Tue, 8 Oct 2019 17:36:14 +0200 Subject: [PATCH] drivers: marvell: comphy-a3700: fix USB3 powering on when on lane 2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When USB3 is on lane 2 and indirect register access is used, the polling at the end of the mvebu_a3700_comphy_usb3_power_on function is incorrect. The LOOPBACK_REG0 register should not be used at all. Instead we have to write the LANE_STATUS1 register address (with offset USB3PHY_LANE2_REG_BASE_OFFSET) into the indirect address register and then we should poll indirect data register. This fixes problems on Turris Mox, which uses lane 2 for USB3. Signed-off-by: Marek Behún Change-Id: I968b0cccee5ddbe10a2b5614e52e52d87682aacd --- drivers/marvell/comphy/phy-comphy-3700.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/marvell/comphy/phy-comphy-3700.c b/drivers/marvell/comphy/phy-comphy-3700.c index 2e8c4128e..fa5183bc5 100644 --- a/drivers/marvell/comphy/phy-comphy-3700.c +++ b/drivers/marvell/comphy/phy-comphy-3700.c @@ -721,11 +721,11 @@ static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index, udelay(PLL_SET_DELAY_US); if (comphy_index == COMPHY_LANE2) { - data = COMPHY_LOOPBACK_REG0 + USB3PHY_LANE2_REG_BASE_OFFSET; + data = COMPHY_REG_LANE_STATUS1_ADDR + USB3PHY_LANE2_REG_BASE_OFFSET; mmio_write_32(reg_base + COMPHY_LANE2_INDIR_ADDR_OFFSET, data); - addr = COMPHY_LOOPBACK_REG0 + USB3PHY_LANE2_REG_BASE_OFFSET; + addr = reg_base + COMPHY_LANE2_INDIR_DATA_OFFSET; ret = polling_with_timeout(addr, TXDCLK_PCLK_EN, TXDCLK_PCLK_EN, COMPHY_PLL_TIMEOUT, REG_32BIT); } else {