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Merge pull request #752 from rockchip-linux/rk3399/fixes-s2r-1107 

rk3399: fixes and updates for s2r
This commit is contained in:
danh-arm 2016-11-08 12:17:44 +00:00 committed by GitHub
parent f61bf2c73c 06077161e9
commit 90d2956aea
3 changed files with 40 additions and 51 deletions
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6
plat/rockchip/rk3399/drivers/pmu/pmu.c
View File

@ -1144,11 +1144,12 @@ static int sys_pwr_domain_suspend(void)
}
mmio_setbits_32(PMU_BASE + PMU_PWRDN_CON, BIT(PMU_SCU_B_PWRDWN_EN));
secure_watchdog_disable();
/*
* Disabling PLLs/PWM/DVFS is approaching WFI which is
* the last steps in suspend.
*/
plls_suspend_prepare();
disable_dvfs_plls();
disable_pwms();
disable_nodvfs_plls();
@ -1171,7 +1172,8 @@ static int sys_pwr_domain_resume(void)
/* PWM regulators take time to come up; give 300us to be safe. */
udelay(300);
enable_dvfs_plls();
plls_resume_finish();
secure_watchdog_restore();
/* restore clk_ddrc_bpll_src_en gate */
mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(3),

65
plat/rockchip/rk3399/drivers/soc/soc.c
View File

@ -192,18 +192,26 @@ static void dma_secure_cfg(uint32_t secure)
/* pll suspend */
struct deepsleep_data_s slp_data;
static void pll_suspend_prepare(uint32_t pll_id)
void secure_watchdog_disable(void)
{
int i;
slp_data.sgrf_con[3] = mmio_read_32(SGRF_BASE + SGRF_SOC_CON3_7(3));
if (pll_id == PPLL_ID)
for (i = 0; i < PLL_CON_COUNT; i++)
slp_data.plls_con[pll_id][i] =
mmio_read_32(PMUCRU_BASE + PMUCRU_PPLL_CON(i));
else
for (i = 0; i < PLL_CON_COUNT; i++)
slp_data.plls_con[pll_id][i] =
mmio_read_32(CRU_BASE + CRU_PLL_CON(pll_id, i));
/* disable CA53 wdt pclk */
mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(3),
BITS_WITH_WMASK(WDT_CA53_DIS, WDT_CA53_1BIT_MASK,
PCLK_WDT_CA53_GATE_SHIFT));
/* disable CM0 wdt pclk */
mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(3),
BITS_WITH_WMASK(WDT_CM0_DIS, WDT_CM0_1BIT_MASK,
PCLK_WDT_CM0_GATE_SHIFT));
}
void secure_watchdog_restore(void)
{
mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(3),
slp_data.sgrf_con[3] |
WMSK_BIT(PCLK_WDT_CA53_GATE_SHIFT) |
WMSK_BIT(PCLK_WDT_CM0_GATE_SHIFT));
}
static void set_pll_slow_mode(uint32_t pll_id)
@ -339,23 +347,6 @@ void restore_dpll(void)
restore_pll(DPLL_ID, slp_data.plls_con[DPLL_ID]);
}
void plls_suspend_prepare(void)
{
uint32_t i, pll_id;
for (pll_id = ALPLL_ID; pll_id < END_PLL_ID; pll_id++)
pll_suspend_prepare(pll_id);
for (i = 0; i < CRU_CLKSEL_COUNT; i++)
slp_data.cru_clksel_con[i] =
mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(i));
for (i = 0; i < PMUCRU_CLKSEL_CONUT; i++)
slp_data.pmucru_clksel_con[i] =
mmio_read_32(PMUCRU_BASE +
PMUCRU_CLKSEL_OFFSET + i * REG_SIZE);
}
void clk_gate_con_save(void)
{
uint32_t i = 0;
@ -409,26 +400,6 @@ static void _pll_resume(uint32_t pll_id)
set_pll_normal_mode(pll_id);
}
void plls_resume_finish(void)
{
int i;
for (i = 0; i < CRU_CLKSEL_COUNT; i++) {
/* CRU_CLKSEL_CON96~107 the high 16-bit isb't write_mask */
if (i > 95)
mmio_write_32((CRU_BASE + CRU_CLKSEL_CON(i)),
slp_data.cru_clksel_con[i]);
else
mmio_write_32((CRU_BASE + CRU_CLKSEL_CON(i)),
REG_SOC_WMSK |
slp_data.cru_clksel_con[i]);
}
for (i = 0; i < PMUCRU_CLKSEL_CONUT; i++)
mmio_write_32((PMUCRU_BASE +
PMUCRU_CLKSEL_OFFSET + i * REG_SIZE),
REG_SOC_WMSK | slp_data.pmucru_clksel_con[i]);
}
/**
* enable_dvfs_plls - To resume the specific PLLs
*

20
plat/rockchip/rk3399/drivers/soc/soc.h
View File

@ -73,6 +73,7 @@
#define REG_SOC_WMSK 0xffff0000
#define CLK_GATE_MASK 0x01
#define SGRF_SOC_COUNT 0x17
#define PMUCRU_GATE_COUNT 0x03
#define CRU_GATE_COUNT 0x23
#define PMUCRU_GATE_CON(n) (0x100 + (n) * 4)
@ -111,6 +112,7 @@ struct deepsleep_data_s {
uint32_t cru_clksel_con[CRU_CLKSEL_COUNT];
uint32_t cru_gate_con[CRU_GATE_COUNT];
uint32_t pmucru_gate_con[PMUCRU_GATE_COUNT];
uint32_t sgrf_con[SGRF_SOC_COUNT];
};
/**************************************************
@ -172,6 +174,20 @@ struct deepsleep_data_s {
#define TIMER_FMODE (0x0 << 1)
#define TIMER_RMODE (0x1 << 1)
/**************************************************
* secure WDT
**************************************************/
#define WDT_CM0_EN 0x0
#define WDT_CM0_DIS 0x1
#define WDT_CA53_EN 0x0
#define WDT_CA53_DIS 0x1
#define PCLK_WDT_CA53_GATE_SHIFT 8
#define PCLK_WDT_CM0_GATE_SHIFT 10
#define WDT_CA53_1BIT_MASK 0x1
#define WDT_CM0_1BIT_MASK 0x1
/**************************************************
* cru reg, offset
**************************************************/
@ -330,10 +346,10 @@ static inline void pmu_sgrf_rst_hld(void)
/* funciton*/
void __dead2 soc_global_soft_reset(void);
void plls_suspend_prepare(void);
void secure_watchdog_disable();
void secure_watchdog_restore();
void disable_dvfs_plls(void);
void disable_nodvfs_plls(void);
void plls_resume_finish(void);
void enable_dvfs_plls(void);
void enable_nodvfs_plls(void);
void prepare_abpll_for_ddrctrl(void);