From 90eac1703d555cc007f145ce4c941a2bc6bf58c5 Mon Sep 17 00:00:00 2001 From: Konstantin Porotchkin Date: Sun, 7 Mar 2021 13:12:31 +0200 Subject: [PATCH] plat/marvell: a8k: move efuse definitions to separate header Move efuse definitions to a separate header file for later usage with other FW modules. Change-Id: I2e9465f760d0388c8e5863bc64a4cdc57de2417f Signed-off-by: Konstantin Porotchkin Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/47313 Tested-by: sa_ip-sw-jenkins Reviewed-by: Yi Guo --- .../marvell/armada/a8k/common/efuse_def.h | 33 +++++++++++++++++++ .../armada/a8k/common/include/a8k_plat_def.h | 3 +- .../armada/a8k/common/plat_ble_setup.c | 26 ++++----------- 3 files changed, 42 insertions(+), 20 deletions(-) create mode 100644 include/plat/marvell/armada/a8k/common/efuse_def.h diff --git a/include/plat/marvell/armada/a8k/common/efuse_def.h b/include/plat/marvell/armada/a8k/common/efuse_def.h new file mode 100644 index 000000000..ff1d4a331 --- /dev/null +++ b/include/plat/marvell/armada/a8k/common/efuse_def.h @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2021 Marvell International Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + * https://spdx.org/licenses + */ + +#ifndef EFUSE_DEF_H +#define EFUSE_DEF_H + +#include + +#define MVEBU_AP_EFUSE_SRV_CTRL_REG (MVEBU_AP_GEN_MGMT_BASE + 0x8) +#define EFUSE_SRV_CTRL_LD_SELECT_OFFS 6 +#define EFUSE_SRV_CTRL_LD_SELECT_MASK (1 << EFUSE_SRV_CTRL_LD_SELECT_OFFS) + +#define MVEBU_AP_LD_EFUSE_BASE (MVEBU_AP_GEN_MGMT_BASE + 0xF00) +/* Bits [31:0] - 32 data bits total */ +#define MVEBU_AP_LDX_31_0_EFUSE_OFFS (MVEBU_AP_LD_EFUSE_BASE) +/* Bits [62:32] - 31 data bits total 32nd bit is parity for bits [62:0]*/ +#define MVEBU_AP_LDX_62_32_EFUSE_OFFS (MVEBU_AP_LD_EFUSE_BASE + 0x4) +/* Bits [94:63] - 32 data bits total */ +#define MVEBU_AP_LDX_94_63_EFUSE_OFFS (MVEBU_AP_LD_EFUSE_BASE + 0x8) +/* Bits [125:95] - 31 data bits total, 32nd bit is parity for bits [125:63] */ +#define MVEBU_AP_LDX_125_95_EFUSE_OFFS (MVEBU_AP_LD_EFUSE_BASE + 0xC) +/* Bits [157:126] - 32 data bits total */ +#define MVEBU_AP_LDX_126_157_EFUSE_OFFS (MVEBU_AP_LD_EFUSE_BASE + 0x10) +/* Bits [188:158] - 31 data bits total, 32nd bit is parity for bits [188:126] */ +#define MVEBU_AP_LDX_188_158_EFUSE_OFFS (MVEBU_AP_LD_EFUSE_BASE + 0x14) +/* Bits [220:189] - 32 data bits total */ +#define MVEBU_AP_LDX_220_189_EFUSE_OFFS (MVEBU_AP_LD_EFUSE_BASE + 0x18) + +#endif /* EFUSE_DEF_H */ diff --git a/plat/marvell/armada/a8k/common/include/a8k_plat_def.h b/plat/marvell/armada/a8k/common/include/a8k_plat_def.h index de8031536..3a0fd4b9d 100644 --- a/plat/marvell/armada/a8k/common/include/a8k_plat_def.h +++ b/plat/marvell/armada/a8k/common/include/a8k_plat_def.h @@ -64,7 +64,8 @@ #define MVEBU_AP_GPIO_DATA_IN (MVEBU_AP_GPIO_REGS + 0x10) #define MVEBU_AP_I2C_BASE (MVEBU_REGS_BASE + 0x511000) #define MVEBU_CP0_I2C_BASE (MVEBU_CP_REGS_BASE(0) + 0x701000) -#define MVEBU_AP_EXT_TSEN_BASE (MVEBU_RFU_BASE + 0x8084) +#define MVEBU_AP_GEN_MGMT_BASE (MVEBU_RFU_BASE + 0x8000) +#define MVEBU_AP_EXT_TSEN_BASE (MVEBU_AP_GEN_MGMT_BASE + 0x84) #define MVEBU_AP_MC_TRUSTZONE_REG_LOW(ap, win) (MVEBU_REGS_BASE_AP(ap) + \ 0x20080 + ((win) * 0x8)) diff --git a/plat/marvell/armada/a8k/common/plat_ble_setup.c b/plat/marvell/armada/a8k/common/plat_ble_setup.c index 59a3a3ae1..9c5ee153a 100644 --- a/plat/marvell/armada/a8k/common/plat_ble_setup.c +++ b/plat/marvell/armada/a8k/common/plat_ble_setup.c @@ -14,6 +14,7 @@ #include #include +#include #include #include #include @@ -27,7 +28,6 @@ #define MMAP_RESTORE_SAVED 1 /* SAR clock settings */ -#define MVEBU_AP_GEN_MGMT_BASE (MVEBU_RFU_BASE + 0x8000) #define MVEBU_AP_SAR_REG_BASE(r) (MVEBU_AP_GEN_MGMT_BASE + 0x200 +\ ((r) << 2)) @@ -82,11 +82,6 @@ (0x1 << AVS_SOFT_RESET_OFFSET) | \ (0x1 << AVS_ENABLE_OFFSET)) -#define MVEBU_AP_EFUSE_SRV_CTRL_REG (MVEBU_AP_GEN_MGMT_BASE + 0x8) -#define EFUSE_SRV_CTRL_LD_SELECT_OFFS 6 -#define EFUSE_SRV_CTRL_LD_SEL_USER_MASK (1 << EFUSE_SRV_CTRL_LD_SELECT_OFFS) - - /* * - Identification information in the LD-0 eFuse: * DRO: LD0[74:65] - Not used by the SW @@ -96,14 +91,7 @@ * Cluster 1 PWR: LD0[193] - if set to 1, power down CPU Cluster-1 * resulting in 2 CPUs active only (7020) */ -#define MVEBU_AP_LD_EFUSE_BASE (MVEBU_AP_GEN_MGMT_BASE + 0xF00) -/* Bits [94:63] - 32 data bits total */ -#define MVEBU_AP_LD0_94_63_EFUSE_OFFS (MVEBU_AP_LD_EFUSE_BASE + 0x8) -/* Bits [125:95] - 31 data bits total, 32nd bit is parity for bits [125:63] */ -#define MVEBU_AP_LD0_125_95_EFUSE_OFFS (MVEBU_AP_LD_EFUSE_BASE + 0xC) -/* Bits [220:189] - 32 data bits total */ -#define MVEBU_AP_LD0_220_189_EFUSE_OFFS (MVEBU_AP_LD_EFUSE_BASE + 0x18) -/* Offsets for the above 2 fields combined into single 64-bit value [125:63] */ +/* Offsets for 2 efuse fields combined into single 64-bit value [125:63] */ #define EFUSE_AP_LD0_DRO_OFFS 2 /* LD0[74:65] */ #define EFUSE_AP_LD0_DRO_MASK 0x3FF #define EFUSE_AP_LD0_REVID_OFFS 12 /* LD0[78:75] */ @@ -376,20 +364,20 @@ static void ble_plat_svc_config(void) uint8_t avs_data_bits, min_sw_ver, svc_fields; unsigned int ap_type; - /* Set access to LD0 */ + /* Get test EERPOM data */ avs_workpoint = avs_update_from_eeprom(0); if (avs_workpoint) goto set_aws_wp; /* Set access to LD0 */ reg_val = mmio_read_32(MVEBU_AP_EFUSE_SRV_CTRL_REG); - reg_val &= ~EFUSE_SRV_CTRL_LD_SEL_USER_MASK; + reg_val &= ~EFUSE_SRV_CTRL_LD_SELECT_MASK; mmio_write_32(MVEBU_AP_EFUSE_SRV_CTRL_REG, reg_val); /* Obtain the value of LD0[125:63] */ - efuse = mmio_read_32(MVEBU_AP_LD0_125_95_EFUSE_OFFS); + efuse = mmio_read_32(MVEBU_AP_LDX_125_95_EFUSE_OFFS); efuse <<= 32; - efuse |= mmio_read_32(MVEBU_AP_LD0_94_63_EFUSE_OFFS); + efuse |= mmio_read_32(MVEBU_AP_LDX_94_63_EFUSE_OFFS); /* SW Revision: * Starting from SW revision 1 the SVC flow is supported. @@ -452,7 +440,7 @@ static void ble_plat_svc_config(void) perr[i] = 1; /* register the error */ } - single_cluster = mmio_read_32(MVEBU_AP_LD0_220_189_EFUSE_OFFS); + single_cluster = mmio_read_32(MVEBU_AP_LDX_220_189_EFUSE_OFFS); single_cluster = (single_cluster >> EFUSE_AP_LD0_CLUSTER_DOWN_OFFS) & 1; device_id = cp110_device_id_get(MVEBU_CP_REGS_BASE(0));