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Revert Cortex-A57 r0p0 errata #814670 

This patch reverts the workaround for errata #814670: "A57 DMB barrier does not
guarantee observation of the effects of a cache maintenance operation". Cache
maintenance by set/way operations is performed only for processor power
down. BROADCASTCACHEMAINT = 1'b1 on the Cortex-A57 macro on Juno. Hence this
erratum will have no impact.

Change-Id: I6824044c963b28d59aed39712a6da376dc053b82
This commit is contained in:
Achin Gupta 2014-07-20 19:55:34 +01:00
parent cc8856432e
commit 912e794340
2 changed files with 0 additions and 2 deletions
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1
include/lib/aarch64/arch.h
View File

@ -404,7 +404,6 @@
/* A57 CPUACTLR definitions */
#define CPUACTLR_NO_ALLOC_WBWA (1 << 49)
#define CPUACTLR_DIS_DMB_NULL (1 << 58)
#define CPUACTLR_DCC_AS_DCCI (1 << 44)
/*******************************************************************************

1
lib/aarch64/cpu_helpers.S
View File

@ -56,7 +56,6 @@ a57_setup_begin:
cmp x1, #0 // Minor Revision 0
b.ne smp_setup_begin
mov x1, #CPUACTLR_NO_ALLOC_WBWA
orr x1, x1, #CPUACTLR_DIS_DMB_NULL
orr x1, x1, #CPUACTLR_DCC_AS_DCCI
mrs x0, CPUACTLR_EL1
orr x0, x0, x1