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plat: zynqmp: Add support for CG/EG/EV device detection 

Read ipdisable reg which needs to be used for cg/eg/ev device detection.
ATF runs in EL3 that's why this read can be done directly.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
This commit is contained in:
Siva Durga Prasad Paladugu 2018-05-01 11:10:25 +05:30
parent d9710aeb03
commit 915d4872cb
2 changed files with 77 additions and 3 deletions
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75
plat/xilinx/zynqmp/aarch64/zynqmp_common.c
View File

@ -60,40 +60,96 @@ unsigned int zynqmp_get_uart_clk(void)
#if LOG_LEVEL >= LOG_LEVEL_NOTICE #if LOG_LEVEL >= LOG_LEVEL_NOTICE
static const struct { static const struct {
unsigned int id; unsigned int id;
unsigned int ver;
char *name; char *name;
} zynqmp_devices[] = { } zynqmp_devices[] = {
{ {
.id = 0x10, .id = 0x10,
.name = "3EG", .name = "3EG",
}, },
{
.id = 0x10,
.ver = 0x2c,
.name = "3CG",
},
{ {
.id = 0x11, .id = 0x11,
.name = "2EG", .name = "2EG",
}, },
{
.id = 0x11,
.ver = 0x2c,
.name = "2CG",
},
{ {
.id = 0x20, .id = 0x20,
.name = "5EV", .name = "5EV",
}, },
{
.id = 0x20,
.ver = 0x100,
.name = "5EG",
},
{
.id = 0x20,
.ver = 0x12c,
.name = "5CG",
},
{ {
.id = 0x21, .id = 0x21,
.name = "4EV", .name = "4EV",
}, },
{
.id = 0x21,
.ver = 0x100,
.name = "4EG",
},
{
.id = 0x21,
.ver = 0x12c,
.name = "4CG",
},
{ {
.id = 0x30, .id = 0x30,
.name = "7EV", .name = "7EV",
}, },
{
.id = 0x30,
.ver = 0x100,
.name = "7EG",
},
{
.id = 0x30,
.ver = 0x12c,
.name = "7CG",
},
{ {
.id = 0x38, .id = 0x38,
.name = "9EG", .name = "9EG",
}, },
{
.id = 0x38,
.ver = 0x2c,
.name = "9CG",
},
{ {
.id = 0x39, .id = 0x39,
.name = "6EG", .name = "6EG",
}, },
{
.id = 0x39,
.ver = 0x2c,
.name = "6CG",
},
{ {
.id = 0x40, .id = 0x40,
.name = "11EG", .name = "11EG",
}, },
{ /* For testing purpose only */
.id = 0x50,
.ver = 0x2c,
.name = "15CG",
},
{ {
.id = 0x50, .id = 0x50,
.name = "15EG", .name = "15EG",
@ -144,13 +200,26 @@ static unsigned int zynqmp_get_silicon_id(void)
return id; return id;
} }
static unsigned int zynqmp_get_silicon_id2(void)
{
uint32_t id;
id = mmio_read_32(EFUSE_BASEADDR + EFUSE_IPDISABLE_OFFSET);
id &= EFUSE_IPDISABLE_VERSION;
return id;
}
static char *zynqmp_get_silicon_idcode_name(void) static char *zynqmp_get_silicon_idcode_name(void)
{ {
unsigned int id; unsigned int id, ver;
size_t i;
id = zynqmp_get_silicon_id(); id = zynqmp_get_silicon_id();
for (size_t i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) { ver = zynqmp_get_silicon_id2();
if (zynqmp_devices[i].id == id)
for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
if (zynqmp_devices[i].id == id && zynqmp_devices[i].ver == ver)
return zynqmp_devices[i].name; return zynqmp_devices[i].name;
} }
return "UNKN"; return "UNKN";

5
plat/xilinx/zynqmp/zynqmp_def.h
View File

@ -174,6 +174,11 @@
#define ZYNQMP_CSU_VERSION_OFFSET 0x44 #define ZYNQMP_CSU_VERSION_OFFSET 0x44
/* Efuse */
#define EFUSE_BASEADDR 0xFFCC0000
#define EFUSE_IPDISABLE_OFFSET 0x1018
#define EFUSE_IPDISABLE_VERSION 0x1FFU
/* Access control register defines */ /* Access control register defines */
#define ACTLR_EL3_L2ACTLR_BIT (1 << 6) #define ACTLR_EL3_L2ACTLR_BIT (1 << 6)
#define ACTLR_EL3_CPUACTLR_BIT (1 << 0) #define ACTLR_EL3_CPUACTLR_BIT (1 << 0)