Merge changes from topic "jc/mte_enable" into integration
* changes: Add documentation for CTX_INCLUDE_MTE_REGS Enable MTE support in both secure and non-secure worlds
This commit is contained in:
Soby Mathew
TrustedFirmware Code Review
commit
91624b7fed
10
Makefile
10
Makefile
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@ -522,6 +522,14 @@ ifeq ($(ENABLE_BTI),1)
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$(info Branch Protection is an experimental feature)
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endif
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ifeq ($(CTX_INCLUDE_MTE_REGS),1)
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ifneq (${ARCH},aarch64)
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$(error CTX_INCLUDE_MTE_REGS requires AArch64)
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else
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$(info CTX_INCLUDE_MTE_REGS is an experimental feature)
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endif
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endif
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################################################################################
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# Process platform overrideable behaviour
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################################################################################
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@ -643,6 +651,7 @@ $(eval $(call assert_boolean,CREATE_KEYS))
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$(eval $(call assert_boolean,CTX_INCLUDE_AARCH32_REGS))
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$(eval $(call assert_boolean,CTX_INCLUDE_FPREGS))
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$(eval $(call assert_boolean,CTX_INCLUDE_PAUTH_REGS))
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$(eval $(call assert_boolean,CTX_INCLUDE_MTE_REGS))
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$(eval $(call assert_boolean,DEBUG))
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$(eval $(call assert_boolean,DYN_DISABLE_AUTH))
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$(eval $(call assert_boolean,EL3_EXCEPTION_HANDLING))
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@ -702,6 +711,7 @@ $(eval $(call add_define,CTX_INCLUDE_AARCH32_REGS))
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$(eval $(call add_define,CTX_INCLUDE_FPREGS))
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$(eval $(call add_define,CTX_INCLUDE_PAUTH_REGS))
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$(eval $(call add_define,EL3_EXCEPTION_HANDLING))
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$(eval $(call add_define,CTX_INCLUDE_MTE_REGS))
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$(eval $(call add_define,ENABLE_AMU))
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$(eval $(call add_define,ENABLE_ASSERTIONS))
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$(eval $(call add_define,ENABLE_BTI))
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@ -386,6 +386,14 @@ tsp_args_t *tsp_smc_handler(uint64_t func,
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*/
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tsp_get_magic(service_args);
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#if CTX_INCLUDE_MTE_REGS
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/*
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* Write a dummy value to an MTE register, to simulate usage in the
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* secure world
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*/
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write_gcr_el1(0x99);
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#endif
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/* Determine the function to perform based on the function ID */
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switch (TSP_BARE_FID(func)) {
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case TSP_ADD:
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@ -2581,7 +2581,16 @@ Armv8.5-A
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~~~~~~~~~
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- Branch Target Identification feature is selected by ``BRANCH_PROTECTION``
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option set to 1. This option defaults to 0 and this is an experimental feature.
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option set to 1. This option defaults to 0 and this is an experimental
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feature.
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- Memory Tagging Extension feature is unconditionally enabled for both worlds
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(at EL0 and S-EL0) if it is only supported at EL0. If instead it is
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implemented at all ELs, it is unconditionally enabled for only the normal
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world. To enable it for the secure world as well, the build option
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``CTX_INCLUDE_MTE_REGS`` is required. If the hardware does not implement
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MTE support at all, it is always disabled, no matter what build options
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are used.
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Armv7-A
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~~~~~~~
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@ -383,6 +383,13 @@ Common build options
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registers to be included when saving and restoring the CPU context. Default
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is 0.
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- ``CTX_INCLUDE_MTE_REGS``: Enables register saving/reloading support for
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ARMv8.5 Memory Tagging Extension. A value of 0 will disable
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saving/reloading and restrict the use of MTE to the normal world if the
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CPU has support, while a value of 1 enables the saving/reloading, allowing
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the use of MTE in both the secure and non-secure worlds. Default is 0
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(disabled) and this feature is experimental.
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- ``CTX_INCLUDE_PAUTH_REGS``: Boolean option that, when set to 1, enables
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Pointer Authentication for Secure world. This will cause the ARMv8.3-PAuth
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registers to be included when saving and restoring the CPU context as
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@ -813,6 +820,7 @@ Common build options
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cluster platforms). If this option is enabled, then warm boot path
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enables D-caches immediately after enabling MMU. This option defaults to 0.
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Arm development platform specific build options
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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@ -901,4 +901,12 @@
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******************************************************************************/
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#define SSBS S3_3_C4_C2_6
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/*******************************************************************************
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* Armv8.5 - Memory Tagging Extension Registers
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******************************************************************************/
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#define TFSRE0_EL1 S3_0_C5_C6_1
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#define TFSR_EL1 S3_0_C5_C6_0
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#define RGSR_EL1 S3_0_C1_C0_5
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#define GCR_EL1 S3_0_C1_C0_6
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#endif /* ARCH_H */
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@ -501,6 +501,12 @@ DEFINE_RENAME_SYSREG_READ_FUNC(id_aa64mmfr2_el1, ID_AA64MMFR2_EL1)
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DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeyhi_el1, APIAKeyHi_EL1)
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DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeylo_el1, APIAKeyLo_EL1)
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/* Armv8.5 MTE Registers */
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DEFINE_RENAME_SYSREG_RW_FUNCS(tfsre0_el1, TFSRE0_EL1)
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DEFINE_RENAME_SYSREG_RW_FUNCS(tfsr_el1, TFSR_EL1)
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DEFINE_RENAME_SYSREG_RW_FUNCS(rgsr_el1, RGSR_EL1)
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DEFINE_RENAME_SYSREG_RW_FUNCS(gcr_el1, GCR_EL1)
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#define IS_IN_EL(x) \
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(GET_EL(read_CurrentEl()) == MODE_EL##x)
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@ -123,10 +123,22 @@
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#define CTX_TIMER_SYSREGS_END CTX_AARCH32_END
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#endif /* NS_TIMER_SWITCH */
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#if CTX_INCLUDE_MTE_REGS
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#define CTX_TFSRE0_EL1 (CTX_TIMER_SYSREGS_END + U(0x0))
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#define CTX_TFSR_EL1 (CTX_TIMER_SYSREGS_END + U(0x8))
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#define CTX_RGSR_EL1 (CTX_TIMER_SYSREGS_END + U(0x10))
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#define CTX_GCR_EL1 (CTX_TIMER_SYSREGS_END + U(0x18))
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/* Align to the next 16 byte boundary */
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#define CTX_MTE_REGS_END (CTX_TIMER_SYSREGS_END + U(0x20))
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#else
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#define CTX_MTE_REGS_END CTX_TIMER_SYSREGS_END
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#endif /* CTX_INCLUDE_MTE_REGS */
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/*
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* End of system registers.
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*/
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#define CTX_SYSREGS_END CTX_TIMER_SYSREGS_END
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#define CTX_SYSREGS_END CTX_MTE_REGS_END
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/*******************************************************************************
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* Constants that allow assembler code to access members of and the 'fp_regs'
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@ -145,6 +145,17 @@ func el1_sysregs_context_save
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str x14, [x0, #CTX_CNTKCTL_EL1]
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#endif
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/* Save MTE system registers if the build has instructed so */
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#if CTX_INCLUDE_MTE_REGS
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mrs x15, TFSRE0_EL1
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mrs x16, TFSR_EL1
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stp x15, x16, [x0, #CTX_TFSRE0_EL1]
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mrs x9, RGSR_EL1
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mrs x10, GCR_EL1
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stp x9, x10, [x0, #CTX_RGSR_EL1]
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#endif
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ret
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endfunc el1_sysregs_context_save
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@ -229,6 +240,16 @@ func el1_sysregs_context_restore
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ldr x14, [x0, #CTX_CNTKCTL_EL1]
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msr cntkctl_el1, x14
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#endif
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/* Restore MTE system registers if the build has instructed so */
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#if CTX_INCLUDE_MTE_REGS
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ldp x11, x12, [x0, #CTX_TFSRE0_EL1]
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msr TFSRE0_EL1, x11
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msr TFSR_EL1, x12
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ldp x13, x14, [x0, #CTX_RGSR_EL1]
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msr RGSR_EL1, x13
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msr GCR_EL1, x14
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#endif
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/* No explict ISB required here as ERET covers it */
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ret
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@ -137,17 +137,30 @@ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
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scr_el3 |= SCR_API_BIT | SCR_APK_BIT;
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#endif /* !CTX_INCLUDE_PAUTH_REGS */
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unsigned int mte = get_armv8_5_mte_support();
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/*
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* Enable MTE support unilaterally for normal world if the CPU supports
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* it.
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* Enable MTE support. Support is enabled unilaterally for the normal
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* world, and only for the secure world when CTX_INCLUDE_MTE_REGS is
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* set.
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*/
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if (mte != MTE_UNIMPLEMENTED) {
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if (security_state == NON_SECURE) {
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scr_el3 |= SCR_ATA_BIT;
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}
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unsigned int mte = get_armv8_5_mte_support();
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#if CTX_INCLUDE_MTE_REGS
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assert(mte == MTE_IMPLEMENTED_ELX);
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scr_el3 |= SCR_ATA_BIT;
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#else
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if (mte == MTE_IMPLEMENTED_EL0) {
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/*
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* Can enable MTE across both worlds as no MTE registers are
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* used
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*/
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scr_el3 |= SCR_ATA_BIT;
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} else if (mte == MTE_IMPLEMENTED_ELX && security_state == NON_SECURE) {
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/*
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* Can only enable MTE in Non-Secure world without register
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* saving
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*/
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scr_el3 |= SCR_ATA_BIT;
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}
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#endif
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#ifdef IMAGE_BL31
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/*
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@ -214,6 +214,11 @@ ifeq (${ARCH},aarch32)
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override ENABLE_SPE_FOR_LOWER_ELS := 0
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endif
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# Include Memory Tagging Extension registers in cpu context. This must be set
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# to 1 if the platform wants to use this feature in the Secure world and MTE is
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# enabled at ELX.
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CTX_INCLUDE_MTE_REGS := 0
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ENABLE_AMU := 0
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# By default, enable Scalable Vector Extension if implemented for Non-secure
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