Merge pull request #1691 from vijayenthiran-arm/sgi-dmc620-tzc
Add support for dmc620 tzc driver
This commit is contained in:
Antonio Niño Díaz
GitHub
commit
9165684996
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <debug.h>
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#include <mmio.h>
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#include <tzc_dmc620.h>
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/* Mask to extract bit 31 to 16 */
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#define MASK_31_16 UINT64_C(0x0000ffff0000)
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/* Mask to extract bit 47 to 32 */
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#define MASK_47_32 UINT64_C(0xffff00000000)
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/* Helper macro for getting dmc_base addr of a dmc_inst */
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#define DMC_BASE(plat_data, dmc_inst) \
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((uintptr_t)(plat_data->dmc_base[dmc_inst]))
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/* Pointer to the tzc_dmc620_config_data structure populated by the platform */
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static const tzc_dmc620_config_data_t *g_plat_config_data;
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#if ENABLE_ASSERTIONS
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/*
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* Helper function to check if the DMC-620 instance is present at the
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* base address provided by the platform and also check if at least
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* one dmc instance is present.
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*/
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static void tzc_dmc620_validate_plat_driver_data(
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const tzc_dmc620_driver_data_t *plat_driver_data)
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{
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uint8_t dmc_inst, dmc_count;
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unsigned int dmc_id;
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uintptr_t base;
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assert(plat_driver_data != NULL);
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dmc_count = plat_driver_data->dmc_count;
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assert(dmc_count > 0U);
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for (dmc_inst = 0U; dmc_inst < dmc_count; dmc_inst++) {
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base = DMC_BASE(plat_driver_data, dmc_inst);
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dmc_id = mmio_read_32(base + DMC620_PERIPHERAL_ID_0);
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assert(dmc_id == DMC620_PERIPHERAL_ID_0_VALUE);
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}
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}
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#endif
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/*
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* Program a region with region base and region top addresses of all
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* DMC-620 instances.
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*/
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static void tzc_dmc620_configure_region(int region_no,
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unsigned long long region_base,
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unsigned long long region_top,
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unsigned int sec_attr)
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{
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uint32_t min_31_00, min_47_32;
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uint32_t max_31_00, max_47_32;
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uint8_t dmc_inst, dmc_count;
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uintptr_t base;
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const tzc_dmc620_driver_data_t *plat_driver_data;
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plat_driver_data = g_plat_config_data->plat_drv_data;
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assert(plat_driver_data != NULL);
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/* Do range checks on regions. */
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assert((region_no >= 0U) && (region_no <= DMC620_ACC_ADDR_COUNT));
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/* region_base and (region_top + 1) must be 4KB aligned */
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assert(((region_base | (region_top + 1U)) & (4096U - 1U)) == 0U);
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dmc_count = plat_driver_data->dmc_count;
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for (dmc_inst = 0U; dmc_inst < dmc_count; dmc_inst++) {
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min_31_00 = (region_base & MASK_31_16) | sec_attr;
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min_47_32 = (region_base & MASK_47_32)
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>> DMC620_ACC_ADDR_WIDTH;
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max_31_00 = (region_top & MASK_31_16);
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max_47_32 = (region_top & MASK_47_32)
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>> DMC620_ACC_ADDR_WIDTH;
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/* Extract the base address of the DMC-620 instance */
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base = DMC_BASE(plat_driver_data, dmc_inst);
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/* Configure access address region registers */
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mmio_write_32(base + DMC620_ACC_ADDR_MIN_31_00_NEXT(region_no),
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min_31_00);
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mmio_write_32(base + DMC620_ACC_ADDR_MIN_47_32_NEXT(region_no),
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min_47_32);
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mmio_write_32(base + DMC620_ACC_ADDR_MAX_31_00_NEXT(region_no),
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max_31_00);
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mmio_write_32(base + DMC620_ACC_ADDR_MAX_47_32_NEXT(region_no),
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max_47_32);
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}
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}
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/*
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* Set the action value for all the DMC-620 instances.
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*/
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static void tzc_dmc620_set_action(void)
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{
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uint8_t dmc_inst, dmc_count;
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uintptr_t base;
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const tzc_dmc620_driver_data_t *plat_driver_data;
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plat_driver_data = g_plat_config_data->plat_drv_data;
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dmc_count = plat_driver_data->dmc_count;
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for (dmc_inst = 0U; dmc_inst < dmc_count; dmc_inst++) {
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/* Extract the base address of the DMC-620 instance */
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base = DMC_BASE(plat_driver_data, dmc_inst);
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/* Switch to READY */
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mmio_write_32(base + DMC620_MEMC_CMD, DMC620_MEMC_CMD_GO);
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mmio_write_32(base + DMC620_MEMC_CMD, DMC620_MEMC_CMD_EXECUTE);
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}
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}
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/*
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* Verify whether the DMC-620 configuration is complete by reading back
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* configuration registers and comparing it with the configured value. If
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* configuration is incomplete, loop till the configured value is reflected in
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* the register.
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*/
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static void tzc_dmc620_verify_complete(void)
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{
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uint8_t dmc_inst, dmc_count;
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uintptr_t base;
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const tzc_dmc620_driver_data_t *plat_driver_data;
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plat_driver_data = g_plat_config_data->plat_drv_data;
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dmc_count = plat_driver_data->dmc_count;
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for (dmc_inst = 0U; dmc_inst < dmc_count; dmc_inst++) {
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/* Extract the base address of the DMC-620 instance */
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base = DMC_BASE(plat_driver_data, dmc_inst);
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while ((mmio_read_32(base + DMC620_MEMC_STATUS) &
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DMC620_MEMC_CMD_MASK) != DMC620_MEMC_CMD_GO)
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continue;
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}
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}
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/*
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* Initialize the DMC-620 TrustZone Controller using the region configuration
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* supplied by the platform. The DMC620 controller should be enabled elsewhere
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* before invoking this function.
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*/
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void arm_tzc_dmc620_setup(const tzc_dmc620_config_data_t *plat_config_data)
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{
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int i;
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/* Check if valid pointer is passed */
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assert(plat_config_data != NULL);
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/*
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* Check if access address count passed by the platform is less than or
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* equal to DMC620's access address count
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*/
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assert(plat_config_data->acc_addr_count <= DMC620_ACC_ADDR_COUNT);
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#if ENABLE_ASSERTIONS
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/* Validates the information passed by platform */
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tzc_dmc620_validate_plat_driver_data(plat_config_data->plat_drv_data);
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#endif
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g_plat_config_data = plat_config_data;
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INFO("Configuring DMC-620 TZC settings\n");
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for (i = 0U; i < g_plat_config_data->acc_addr_count; i++)
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tzc_dmc620_configure_region(i,
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g_plat_config_data->plat_acc_addr_data[i].region_base,
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g_plat_config_data->plat_acc_addr_data[i].region_top,
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g_plat_config_data->plat_acc_addr_data[i].sec_attr);
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tzc_dmc620_set_action();
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tzc_dmc620_verify_complete();
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INFO("DMC-620 TZC setup completed\n");
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}
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@ -0,0 +1,104 @@
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef TZC_DMC620_H
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#define TZC_DMC620_H
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#include <utils_def.h>
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/* DMC-620 memc register offsets */
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#define DMC620_MEMC_STATUS U(0x0000)
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#define DMC620_MEMC_CMD U(0x0008)
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/* Mask value to check the status of memc_cmd register */
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#define DMC620_MEMC_CMD_MASK U(0x00000007)
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/* memc_cmd register's action values */
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#define DMC620_MEMC_CMD_GO U(0x00000003)
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#define DMC620_MEMC_CMD_EXECUTE U(0x00000004)
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/* Address offsets of access address next region 0 registers */
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#define DMC620_ACC_ADDR_MIN_31_00_NEXT_BASE U(0x0080)
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#define DMC620_ACC_ADDR_MIN_47_32_NEXT_BASE U(0x0084)
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#define DMC620_ACC_ADDR_MAX_31_00_NEXT_BASE U(0x0088)
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#define DMC620_ACC_ADDR_MAX_47_32_NEXT_BASE U(0x008c)
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/* Length of one block of access address next register region */
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#define DMC620_ACC_ADDR_NEXT_SIZE U(0x0010)
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/* Address offsets of access address next registers */
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#define DMC620_ACC_ADDR_MIN_31_00_NEXT(region_no) \
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(DMC620_ACC_ADDR_MIN_31_00_NEXT_BASE + \
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(region_no * DMC620_ACC_ADDR_NEXT_SIZE))
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#define DMC620_ACC_ADDR_MIN_47_32_NEXT(region_no) \
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(DMC620_ACC_ADDR_MIN_47_32_NEXT_BASE + \
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(region_no * DMC620_ACC_ADDR_NEXT_SIZE))
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#define DMC620_ACC_ADDR_MAX_31_00_NEXT(region_no) \
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(DMC620_ACC_ADDR_MAX_31_00_NEXT_BASE + \
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(region_no * DMC620_ACC_ADDR_NEXT_SIZE))
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#define DMC620_ACC_ADDR_MAX_47_32_NEXT(region_no) \
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(DMC620_ACC_ADDR_MAX_47_32_NEXT_BASE + \
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(region_no * DMC620_ACC_ADDR_NEXT_SIZE))
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/* Number of TZC address regions in DMC-620 */
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#define DMC620_ACC_ADDR_COUNT U(8)
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/* Width of access address registers */
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#define DMC620_ACC_ADDR_WIDTH U(32)
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/* Peripheral ID registers offsets */
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#define DMC620_PERIPHERAL_ID_0 U(0x1fe0)
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/* Default values in id registers */
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#define DMC620_PERIPHERAL_ID_0_VALUE U(0x00000054)
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/* Secure access region attributes. */
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#define TZC_DMC620_REGION_NS_RD U(0x00000001)
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#define TZC_DMC620_REGION_NS_WR U(0x00000002)
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#define TZC_DMC620_REGION_NS_RDWR \
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(TZC_DMC620_REGION_NS_RD | TZC_DMC620_REGION_NS_WR)
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#define TZC_DMC620_REGION_S_RD U(0x00000004)
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#define TZC_DMC620_REGION_S_WR U(0x00000008)
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#define TZC_DMC620_REGION_S_RDWR \
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(TZC_DMC620_REGION_S_RD | TZC_DMC620_REGION_S_WR)
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#define TZC_DMC620_REGION_S_NS_RDWR \
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(TZC_DMC620_REGION_NS_RDWR | TZC_DMC620_REGION_S_RDWR)
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/*
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* Contains pointer to the base addresses of all the DMC-620 instances.
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* 'dmc_count' specifies the number of DMC base addresses contained in the
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* array pointed to by dmc_base.
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*/
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typedef struct tzc_dmc620_driver_data {
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const uintptr_t *dmc_base;
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const unsigned int dmc_count;
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} tzc_dmc620_driver_data_t;
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/*
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* Contains region base, region top addresses and corresponding attributes
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* for configuring TZC access region registers.
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*/
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typedef struct tzc_dmc620_acc_addr_data {
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const unsigned long long region_base;
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const unsigned long long region_top;
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const unsigned int sec_attr;
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} tzc_dmc620_acc_addr_data_t;
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/*
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* Contains platform specific data for configuring TZC region base and
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* region top address. 'acc_addr_count' specifies the number of
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* valid entries in 'plat_acc_addr_data' array.
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*/
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typedef struct tzc_dmc620_config_data {
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const tzc_dmc620_driver_data_t *plat_drv_data;
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const tzc_dmc620_acc_addr_data_t *plat_acc_addr_data;
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const uint8_t acc_addr_count;
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} tzc_dmc620_config_data_t;
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/* Function prototypes */
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void arm_tzc_dmc620_setup(const tzc_dmc620_config_data_t *plat_config_data);
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#endif /* TZC_DMC620_H */
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@ -8,11 +8,16 @@
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#define PLATFORM_DEF_H
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#include <sgi_base_platform_def.h>
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#include <utils_def.h>
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#define PLAT_ARM_CLUSTER_COUNT 2
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#define CSS_SGI_MAX_CPUS_PER_CLUSTER 4
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#define CSS_SGI_MAX_PE_PER_CPU 1
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#define PLAT_CSS_MHU_BASE 0x45000000
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#define PLAT_CSS_MHU_BASE UL(0x45000000)
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/* Base address of DMC-620 instances */
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#define SGI575_DMC620_BASE0 UL(0x4e000000)
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#define SGI575_DMC620_BASE1 UL(0x4e100000)
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#endif /* PLATFORM_DEF_H */
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@ -14,7 +14,9 @@ SGI_CPU_SOURCES := lib/cpus/aarch64/cortex_a75.S
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BL1_SOURCES += ${SGI_CPU_SOURCES}
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BL2_SOURCES += lib/utils/mem_region.c \
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BL2_SOURCES += ${SGI575_BASE}/sgi575_security.c \
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drivers/arm/tzc/tzc_dmc620.c \
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lib/utils/mem_region.c \
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plat/arm/common/arm_nor_psci_mem_protect.c
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BL31_SOURCES += ${SGI_CPU_SOURCES} \
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@ -0,0 +1,39 @@
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <debug.h>
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#include <platform_def.h>
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#include <tzc_dmc620.h>
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uintptr_t sgi575_dmc_base[] = {
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SGI575_DMC620_BASE0,
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SGI575_DMC620_BASE1
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};
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static const tzc_dmc620_driver_data_t sgi575_plat_driver_data = {
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.dmc_base = sgi575_dmc_base,
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.dmc_count = ARRAY_SIZE(sgi575_dmc_base)
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};
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static const tzc_dmc620_acc_addr_data_t sgi575_acc_addr_data[] = {
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{
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.region_base = ARM_AP_TZC_DRAM1_BASE,
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.region_top = ARM_AP_TZC_DRAM1_BASE + ARM_TZC_DRAM1_SIZE - 1,
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.sec_attr = TZC_DMC620_REGION_S_RDWR
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}
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};
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static const tzc_dmc620_config_data_t sgi575_plat_config_data = {
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.plat_drv_data = &sgi575_plat_driver_data,
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.plat_acc_addr_data = sgi575_acc_addr_data,
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.acc_addr_count = ARRAY_SIZE(sgi575_acc_addr_data)
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};
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/* Initialize the secure environment */
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void plat_arm_security_setup(void)
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{
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arm_tzc_dmc620_setup(&sgi575_plat_config_data);
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}
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@ -8,11 +8,16 @@
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#define PLATFORM_DEF_H
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#include <sgi_base_platform_def.h>
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#include <utils_def.h>
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#define PLAT_ARM_CLUSTER_COUNT 2
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#define CSS_SGI_MAX_CPUS_PER_CLUSTER 4
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#define CSS_SGI_MAX_PE_PER_CPU 1
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#define PLAT_CSS_MHU_BASE 0x45400000
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#define PLAT_CSS_MHU_BASE UL(0x45400000)
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/* Base address of DMC-620 instances */
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#define SGICLARKA_DMC620_BASE0 UL(0x4e000000)
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#define SGICLARKA_DMC620_BASE1 UL(0x4e100000)
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#endif /* PLATFORM_DEF_H */
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@ -14,7 +14,9 @@ SGI_CPU_SOURCES := lib/cpus/aarch64/cortex_ares.S
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BL1_SOURCES += ${SGI_CPU_SOURCES}
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BL2_SOURCES += lib/utils/mem_region.c \
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BL2_SOURCES += ${SGICLARKA_BASE}/sgiclarka_security.c \
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drivers/arm/tzc/tzc_dmc620.c \
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lib/utils/mem_region.c \
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plat/arm/common/arm_nor_psci_mem_protect.c
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BL31_SOURCES += ${SGI_CPU_SOURCES} \
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@ -0,0 +1,39 @@
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <debug.h>
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#include <platform_def.h>
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#include <tzc_dmc620.h>
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uintptr_t sgiclarka_dmc_base[] = {
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SGICLARKA_DMC620_BASE0,
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SGICLARKA_DMC620_BASE1
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};
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static const tzc_dmc620_driver_data_t sgiclarka_plat_driver_data = {
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.dmc_base = sgiclarka_dmc_base,
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.dmc_count = ARRAY_SIZE(sgiclarka_dmc_base)
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};
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static const tzc_dmc620_acc_addr_data_t sgiclarka_acc_addr_data[] = {
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{
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.region_base = ARM_AP_TZC_DRAM1_BASE,
|
||||
.region_top = ARM_AP_TZC_DRAM1_BASE + ARM_TZC_DRAM1_SIZE - 1,
|
||||
.sec_attr = TZC_DMC620_REGION_S_RDWR
|
||||
}
|
||||
};
|
||||
|
||||
static const tzc_dmc620_config_data_t sgiclarka_plat_config_data = {
|
||||
.plat_drv_data = &sgiclarka_plat_driver_data,
|
||||
.plat_acc_addr_data = sgiclarka_acc_addr_data,
|
||||
.acc_addr_count = ARRAY_SIZE(sgiclarka_acc_addr_data)
|
||||
};
|
||||
|
||||
/* Initialize the secure environment */
|
||||
void plat_arm_security_setup(void)
|
||||
{
|
||||
arm_tzc_dmc620_setup(&sgiclarka_plat_config_data);
|
||||
}
|
||||
|
|
@ -35,8 +35,7 @@ PLAT_BL_COMMON_SOURCES += ${CSS_ENT_BASE}/sgi_plat.c \
|
|||
|
||||
BL1_SOURCES += ${INTERCONNECT_SOURCES}
|
||||
|
||||
BL2_SOURCES += ${CSS_ENT_BASE}/sgi_security.c \
|
||||
${CSS_ENT_BASE}/sgi_image_load.c
|
||||
BL2_SOURCES += ${CSS_ENT_BASE}/sgi_image_load.c
|
||||
|
||||
BL31_SOURCES += ${INTERCONNECT_SOURCES} \
|
||||
${ENT_GIC_SOURCES} \
|
||||
|
|
|
|||
|
|
@ -1,15 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <arm_config.h>
|
||||
#include <plat_arm.h>
|
||||
|
||||
/*
|
||||
* We assume that all security programming is done by the primary core.
|
||||
*/
|
||||
void plat_arm_security_setup(void)
|
||||
{
|
||||
}
|
||||
Loading…
Reference in New Issue