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Merge "Neovers N1: added support to update presence of External LLC" into integration

This commit is contained in:
Manish Pandey 2020-01-28 08:18:56 +00:00 committed by TrustedFirmware Code Review
parent 0281e60c3d f2d6b4ee57
commit 91ff490d75
4 changed files with 22 additions and 2 deletions
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5
docs/design/cpu-specific-build-macros.rst
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@ -324,6 +324,11 @@ architecture that can be enabled by the platform as desired.
as recommended in section "4.7 Non-Temporal Loads/Stores" of the
`Cortex-A57 Software Optimization Guide`_.
- ``NEOVERSE_N1_EXTERNAL_LLC``: This flag indicates that an external last
level cache(LLC) is present in the system, and that the DataSource field
on the master CHI interface indicates when data is returned from the LLC.
This is used to control how the LL_CACHE* PMU events count.
--------------
*Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved.*

3
include/lib/cpus/aarch64/neoverse_n1.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -35,6 +35,7 @@
#define NEOVERSE_N1_WS_THR_L2_MASK (ULL(3) << 24)
#define NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT (ULL(1) << 51)
#define NEOVERSE_N1_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0)
/*******************************************************************************
* CPU Auxiliary Control register specific definitions.

7
lib/cpus/aarch64/neoverse_n1.S
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@ -465,6 +465,13 @@ func neoverse_n1_reset_func
msr CPUAMCNTENSET_EL0, x0
#endif
#if NEOVERSE_N1_EXTERNAL_LLC
/* Some system may have External LLC, core needs to be made aware */
mrs x0, NEOVERSE_N1_CPUECTLR_EL1
orr x0, x0, NEOVERSE_N1_CPUECTLR_EL1_EXTLLC_BIT
msr NEOVERSE_N1_CPUECTLR_EL1, x0
#endif
#if ERRATA_DSU_936184
bl errata_dsu_936184_wa
#endif

9
lib/cpus/cpu-ops.mk
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@ -1,5 +1,5 @@
#
# Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
# Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@ -20,6 +20,10 @@ WORKAROUND_CVE_2017_5715 ?=1
WORKAROUND_CVE_2018_3639 ?=1
DYNAMIC_WORKAROUND_CVE_2018_3639 ?=0
# Flag to indicate internal or external Last level cache
# By default internal
NEOVERSE_N1_EXTERNAL_LLC ?=0
# Process SKIP_A57_L1_FLUSH_PWR_DWN flag
$(eval $(call assert_boolean,SKIP_A57_L1_FLUSH_PWR_DWN))
$(eval $(call add_define,SKIP_A57_L1_FLUSH_PWR_DWN))
@ -43,6 +47,9 @@ $(eval $(call add_define,WORKAROUND_CVE_2018_3639))
$(eval $(call assert_boolean,DYNAMIC_WORKAROUND_CVE_2018_3639))
$(eval $(call add_define,DYNAMIC_WORKAROUND_CVE_2018_3639))
$(eval $(call assert_boolean,NEOVERSE_N1_EXTERNAL_LLC))
$(eval $(call add_define,NEOVERSE_N1_EXTERNAL_LLC))
ifneq (${DYNAMIC_WORKAROUND_CVE_2018_3639},0)
ifeq (${WORKAROUND_CVE_2018_3639},0)
$(error "Error: WORKAROUND_CVE_2018_3639 must be 1 if DYNAMIC_WORKAROUND_CVE_2018_3639 is 1")