Merge "Neovers N1: added support to update presence of External LLC" into integration
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commit
91ff490d75
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@ -324,6 +324,11 @@ architecture that can be enabled by the platform as desired.
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as recommended in section "4.7 Non-Temporal Loads/Stores" of the
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as recommended in section "4.7 Non-Temporal Loads/Stores" of the
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`Cortex-A57 Software Optimization Guide`_.
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`Cortex-A57 Software Optimization Guide`_.
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- ``NEOVERSE_N1_EXTERNAL_LLC``: This flag indicates that an external last
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level cache(LLC) is present in the system, and that the DataSource field
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on the master CHI interface indicates when data is returned from the LLC.
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This is used to control how the LL_CACHE* PMU events count.
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--------------
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--------------
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*Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved.*
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*Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved.*
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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@ -35,6 +35,7 @@
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#define NEOVERSE_N1_WS_THR_L2_MASK (ULL(3) << 24)
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#define NEOVERSE_N1_WS_THR_L2_MASK (ULL(3) << 24)
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#define NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT (ULL(1) << 51)
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#define NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT (ULL(1) << 51)
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#define NEOVERSE_N1_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0)
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/*******************************************************************************
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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* CPU Auxiliary Control register specific definitions.
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@ -465,6 +465,13 @@ func neoverse_n1_reset_func
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msr CPUAMCNTENSET_EL0, x0
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msr CPUAMCNTENSET_EL0, x0
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#endif
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#endif
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#if NEOVERSE_N1_EXTERNAL_LLC
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/* Some system may have External LLC, core needs to be made aware */
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mrs x0, NEOVERSE_N1_CPUECTLR_EL1
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orr x0, x0, NEOVERSE_N1_CPUECTLR_EL1_EXTLLC_BIT
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msr NEOVERSE_N1_CPUECTLR_EL1, x0
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#endif
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#if ERRATA_DSU_936184
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#if ERRATA_DSU_936184
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bl errata_dsu_936184_wa
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bl errata_dsu_936184_wa
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#endif
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#endif
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@ -1,5 +1,5 @@
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#
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#
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# Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
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# Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
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#
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#
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# SPDX-License-Identifier: BSD-3-Clause
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# SPDX-License-Identifier: BSD-3-Clause
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#
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#
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@ -20,6 +20,10 @@ WORKAROUND_CVE_2017_5715 ?=1
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WORKAROUND_CVE_2018_3639 ?=1
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WORKAROUND_CVE_2018_3639 ?=1
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DYNAMIC_WORKAROUND_CVE_2018_3639 ?=0
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DYNAMIC_WORKAROUND_CVE_2018_3639 ?=0
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# Flag to indicate internal or external Last level cache
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# By default internal
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NEOVERSE_N1_EXTERNAL_LLC ?=0
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# Process SKIP_A57_L1_FLUSH_PWR_DWN flag
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# Process SKIP_A57_L1_FLUSH_PWR_DWN flag
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$(eval $(call assert_boolean,SKIP_A57_L1_FLUSH_PWR_DWN))
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$(eval $(call assert_boolean,SKIP_A57_L1_FLUSH_PWR_DWN))
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$(eval $(call add_define,SKIP_A57_L1_FLUSH_PWR_DWN))
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$(eval $(call add_define,SKIP_A57_L1_FLUSH_PWR_DWN))
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@ -43,6 +47,9 @@ $(eval $(call add_define,WORKAROUND_CVE_2018_3639))
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$(eval $(call assert_boolean,DYNAMIC_WORKAROUND_CVE_2018_3639))
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$(eval $(call assert_boolean,DYNAMIC_WORKAROUND_CVE_2018_3639))
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$(eval $(call add_define,DYNAMIC_WORKAROUND_CVE_2018_3639))
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$(eval $(call add_define,DYNAMIC_WORKAROUND_CVE_2018_3639))
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$(eval $(call assert_boolean,NEOVERSE_N1_EXTERNAL_LLC))
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$(eval $(call add_define,NEOVERSE_N1_EXTERNAL_LLC))
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ifneq (${DYNAMIC_WORKAROUND_CVE_2018_3639},0)
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ifneq (${DYNAMIC_WORKAROUND_CVE_2018_3639},0)
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ifeq (${WORKAROUND_CVE_2018_3639},0)
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ifeq (${WORKAROUND_CVE_2018_3639},0)
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$(error "Error: WORKAROUND_CVE_2018_3639 must be 1 if DYNAMIC_WORKAROUND_CVE_2018_3639 is 1")
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$(error "Error: WORKAROUND_CVE_2018_3639 must be 1 if DYNAMIC_WORKAROUND_CVE_2018_3639 is 1")
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