Synchronise arch.h and arch_helpers.h with TF-A-Tests
The headers forked at some point in the past and have diverged a lot. In order to make it easier to share code between TF-A-Tests and TF-A, this patch synchronises most of the definitions in the mentioned headers. This is not a complete sync, it has to be followed by more cleanup. This patch also removes the read helpers for the AArch32 instructions ats1cpr and ats1hr (they are write-only). Change-Id: Id13ecd7aeb83bd2318cd47156d71a42f1c9f6ba2 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
This commit is contained in:
Antonio Nino Diaz
parent
c4cdd9e464
commit
932b3ae232
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@ -33,10 +33,12 @@
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#define MPIDR_AFF0_SHIFT U(0)
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#define MPIDR_AFF1_SHIFT U(8)
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#define MPIDR_AFF2_SHIFT U(16)
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#define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT
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#define MPIDR_AFFINITY_MASK U(0x00ffffff)
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#define MPIDR_AFFLVL0 U(0)
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#define MPIDR_AFFLVL1 U(1)
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#define MPIDR_AFFLVL2 U(2)
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#define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n
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#define MPIDR_AFFLVL0_VAL(mpidr) \
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(((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK)
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@ -46,6 +48,20 @@
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(((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK)
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#define MPIDR_AFFLVL3_VAL(mpidr) U(0)
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#define MPIDR_AFF_ID(mpid, n) \
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(((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK)
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#define MPID_MASK (MPIDR_MT_MASK |\
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(MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT)|\
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(MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT)|\
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(MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT))
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/*
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* An invalid MPID. This value can be used by functions that return an MPID to
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* indicate an error.
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*/
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#define INVALID_MPID U(0xFFFFFFFF)
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/*
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* The MPIDR_MAX_AFFLVL count starts from 0. Take care to
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* add one while using this macro to define array sizes.
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@ -127,7 +143,7 @@
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#define SDCR_RESET_VAL U(0x0)
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/* HSCTLR definitions */
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#define HSCTLR_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
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#define HSCTLR_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
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(U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
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(U(1) << 11) | (U(1) << 4) | (U(1) << 3))
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@ -167,6 +183,7 @@
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#define GET_NS_BIT(scr) ((scr) & SCR_NS_BIT)
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/* HCR definitions */
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#define HCR_TGE_BIT (U(1) << 27)
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#define HCR_AMO_BIT (U(1) << 5)
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#define HCR_IMO_BIT (U(1) << 4)
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#define HCR_FMO_BIT (U(1) << 3)
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@ -212,10 +229,9 @@
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/* CNTHP_CTL definitions */
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#define CNTHP_CTL_RESET_VAL U(0x0)
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/* NASCR definitions */
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/* NSACR definitions */
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#define NSASEDIS_BIT (U(1) << 15)
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#define NSTRCDIS_BIT (U(1) << 20)
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/* NOTE: correct typo in the definitions */
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#define NSACR_CP11_BIT (U(1) << 11)
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#define NSACR_CP10_BIT (U(1) << 10)
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#define NSACR_IMP_DEF_MASK (U(0x7) << 16)
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@ -262,7 +278,6 @@
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/*
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* TTBCR definitions
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*/
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/* The ARM Trusted Firmware uses the long descriptor format */
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#define TTBCR_EAE_BIT (U(1) << 31)
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#define TTBCR_SH1_NON_SHAREABLE (U(0x0) << 28)
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@ -407,14 +422,30 @@
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#define CNTACR_RWPT_SHIFT U(0x5)
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/*******************************************************************************
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* Definitions of register offsets in the CNTBaseN Frame of the
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* Definitions of register offsets and fields in the CNTBaseN Frame of the
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* system level implementation of the Generic Timer.
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******************************************************************************/
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#define CNTBASE_CNTFRQ U(0x10)
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/* Physical Count register. */
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#define CNTPCT_LO U(0x0)
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/* Counter Frequency register. */
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#define CNTBASEN_CNTFRQ U(0x10)
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/* Physical Timer CompareValue register. */
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#define CNTP_CVAL_LO U(0x20)
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/* Physical Timer Control register. */
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#define CNTP_CTL U(0x2c)
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/* Physical timer control register bit fields shifts and masks */
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#define CNTP_CTL_ENABLE_SHIFT 0
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#define CNTP_CTL_IMASK_SHIFT 1
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#define CNTP_CTL_ISTATUS_SHIFT 2
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#define CNTP_CTL_ENABLE_MASK U(1)
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#define CNTP_CTL_IMASK_MASK U(1)
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#define CNTP_CTL_ISTATUS_MASK U(1)
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/* MAIR macros */
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#define MAIR0_ATTR_SET(attr, index) ((attr) << ((index) << 3))
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#define MAIR1_ATTR_SET(attr, index) ((attr) << (((index) - U(3)) << 3))
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#define MAIR0_ATTR_SET(attr, index) ((attr) << ((index) << U(3)))
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#define MAIR1_ATTR_SET(attr, index) ((attr) << (((index) - U(3)) << U(3)))
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/* System register defines The format is: coproc, opt1, CRn, CRm, opt2 */
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#define SCR p15, 0, c1, c1, 0
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@ -423,6 +454,7 @@
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#define SDCR p15, 0, c1, c3, 1
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#define MPIDR p15, 0, c0, c0, 5
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#define MIDR p15, 0, c0, c0, 0
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#define HVBAR p15, 4, c12, c0, 0
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#define VBAR p15, 0, c12, c0, 0
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#define MVBAR p15, 0, c12, c0, 1
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#define NSACR p15, 0, c1, c1, 2
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@ -443,6 +475,7 @@
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#define TTBR0 p15, 0, c2, c0, 0
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#define TTBR1 p15, 0, c2, c0, 1
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#define TLBIALL p15, 0, c8, c7, 0
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#define TLBIALLH p15, 4, c8, c7, 0
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#define TLBIALLIS p15, 0, c8, c3, 0
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#define TLBIMVA p15, 0, c8, c7, 1
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#define TLBIMVAA p15, 0, c8, c7, 3
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@ -472,6 +505,7 @@
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/* Debug register defines. The format is: coproc, opt1, CRn, CRm, opt2 */
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#define HDCR p15, 4, c1, c1, 1
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#define PMCR p15, 0, c9, c12, 0
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#define CNTHP_TVAL p15, 4, c14, c2, 0
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#define CNTHP_CTL p15, 4, c14, c2, 1
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/* AArch32 coproc registers for 32bit MMU descriptor support */
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@ -507,6 +541,7 @@
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#define VTTBR_64 p15, 6, c2
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#define CNTPCT_64 p15, 0, c14
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#define HTTBR_64 p15, 4, c2
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#define CNTHP_CVAL_64 p15, 6, c14
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#define PAR_64 p15, 0, c7
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/* 64 bit GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRm */
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@ -7,7 +7,7 @@
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#ifndef ARCH_HELPERS_H
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#define ARCH_HELPERS_H
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#include <arch.h> /* for additional register definitions */
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#include <arch.h>
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#include <cdefs.h>
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#include <stdint.h>
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#include <string.h>
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@ -33,13 +33,8 @@ static inline u_register_t read_ ## _name(void) \
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/*
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* The undocumented %Q and %R extended asm are used to implemented the below
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* 64 bit `mrrc` and `mcrr` instructions. It works only on Little Endian
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* systems for GCC versions < 4.6. Above GCC 4.6, both Little Endian and
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* Big Endian systems generate the right instruction encoding.
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* 64 bit `mrrc` and `mcrr` instructions.
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*/
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#if !(__clang__ || __GNUC__ > (4) || __GNUC__ == (4) && __GNUC_MINOR__ >= (6))
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#error "clang or GCC 4.6 or above is required to build AArch32 Trusted Firmware"
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#endif
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#define _DEFINE_COPROCR_WRITE_FUNC_64(_name, coproc, opc1, CRm) \
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static inline void write64_## _name(uint64_t v) \
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@ -78,6 +73,10 @@ static inline void write_ ## _name(const u_register_t v) \
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#define DEFINE_COPROCR_READ_FUNC(_name, ...) \
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_DEFINE_COPROCR_READ_FUNC(_name, __VA_ARGS__)
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/* Define write function for coproc register */
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#define DEFINE_COPROCR_WRITE_FUNC(_name, ...) \
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_DEFINE_COPROCR_WRITE_FUNC(_name, __VA_ARGS__)
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/* Define read & write function for coproc register */
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#define DEFINE_COPROCR_RW_FUNCS(_name, ...) \
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_DEFINE_COPROCR_READ_FUNC(_name, __VA_ARGS__) \
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@ -87,6 +86,10 @@ static inline void write_ ## _name(const u_register_t v) \
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#define DEFINE_COPROCR_READ_FUNC_64(_name, ...) \
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_DEFINE_COPROCR_READ_FUNC_64(_name, __VA_ARGS__)
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/* Define 64 bit write function for coproc register */
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#define DEFINE_COPROCR_WRITE_FUNC_64(_name, ...) \
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_DEFINE_COPROCR_WRITE_FUNC_64(_name, __VA_ARGS__)
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/* Define 64 bit read & write function for coproc register */
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#define DEFINE_COPROCR_RW_FUNCS_64(_name, ...) \
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_DEFINE_COPROCR_READ_FUNC_64(_name, __VA_ARGS__) \
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@ -227,10 +230,13 @@ DEFINE_COPROCR_RW_FUNCS(cntfrq, CNTFRQ)
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DEFINE_COPROCR_RW_FUNCS(cnthctl, CNTHCTL)
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DEFINE_COPROCR_RW_FUNCS(mair0, MAIR0)
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DEFINE_COPROCR_RW_FUNCS(mair1, MAIR1)
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DEFINE_COPROCR_RW_FUNCS(hmair0, HMAIR0)
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DEFINE_COPROCR_RW_FUNCS(ttbcr, TTBCR)
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DEFINE_COPROCR_RW_FUNCS(htcr, HTCR)
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DEFINE_COPROCR_RW_FUNCS(ttbr0, TTBR0)
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DEFINE_COPROCR_RW_FUNCS_64(ttbr0, TTBR0_64)
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DEFINE_COPROCR_RW_FUNCS(ttbr1, TTBR1)
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DEFINE_COPROCR_RW_FUNCS_64(httbr, HTTBR_64)
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DEFINE_COPROCR_RW_FUNCS(vpidr, VPIDR)
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DEFINE_COPROCR_RW_FUNCS(vmpidr, VMPIDR)
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DEFINE_COPROCR_RW_FUNCS_64(vttbr, VTTBR_64)
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@ -238,6 +244,9 @@ DEFINE_COPROCR_RW_FUNCS_64(ttbr1, TTBR1_64)
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DEFINE_COPROCR_RW_FUNCS_64(cntvoff, CNTVOFF_64)
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DEFINE_COPROCR_RW_FUNCS(csselr, CSSELR)
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DEFINE_COPROCR_RW_FUNCS(hstr, HSTR)
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DEFINE_COPROCR_RW_FUNCS(cnthp_ctl_el2, CNTHP_CTL)
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DEFINE_COPROCR_RW_FUNCS(cnthp_tval_el2, CNTHP_TVAL)
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DEFINE_COPROCR_RW_FUNCS_64(cnthp_cval_el2, CNTHP_CVAL_64)
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DEFINE_COPROCR_RW_FUNCS(icc_sre_el1, ICC_SRE)
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DEFINE_COPROCR_RW_FUNCS(icc_sre_el2, ICC_HSRE)
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@ -245,6 +254,7 @@ DEFINE_COPROCR_RW_FUNCS(icc_sre_el3, ICC_MSRE)
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DEFINE_COPROCR_RW_FUNCS(icc_pmr_el1, ICC_PMR)
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DEFINE_COPROCR_RW_FUNCS(icc_rpr_el1, ICC_RPR)
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DEFINE_COPROCR_RW_FUNCS(icc_igrpen1_el3, ICC_MGRPEN1)
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DEFINE_COPROCR_RW_FUNCS(icc_igrpen1_el1, ICC_IGRPEN1)
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DEFINE_COPROCR_RW_FUNCS(icc_igrpen0_el1, ICC_IGRPEN0)
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DEFINE_COPROCR_RW_FUNCS(icc_hppir0_el1, ICC_HPPIR0)
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DEFINE_COPROCR_RW_FUNCS(icc_hppir1_el1, ICC_HPPIR1)
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@ -253,13 +263,17 @@ DEFINE_COPROCR_RW_FUNCS(icc_iar1_el1, ICC_IAR1)
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DEFINE_COPROCR_RW_FUNCS(icc_eoir0_el1, ICC_EOIR0)
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DEFINE_COPROCR_RW_FUNCS(icc_eoir1_el1, ICC_EOIR1)
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DEFINE_COPROCR_RW_FUNCS_64(icc_sgi0r_el1, ICC_SGI0R_EL1_64)
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DEFINE_COPROCR_WRITE_FUNC_64(icc_sgi1r, ICC_SGI1R_EL1_64)
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DEFINE_COPROCR_RW_FUNCS(hdcr, HDCR)
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DEFINE_COPROCR_RW_FUNCS(cnthp_ctl, CNTHP_CTL)
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DEFINE_COPROCR_READ_FUNC(pmcr, PMCR)
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DEFINE_COPROCR_RW_FUNCS(ats1cpr, ATS1CPR)
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DEFINE_COPROCR_RW_FUNCS(ats1hr, ATS1HR)
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/*
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* Address translation
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*/
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DEFINE_COPROCR_WRITE_FUNC(ats1cpr, ATS1CPR)
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DEFINE_COPROCR_WRITE_FUNC(ats1hr, ATS1HR)
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DEFINE_COPROCR_RW_FUNCS_64(par, PAR_64)
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DEFINE_COPROCR_RW_FUNCS(nsacr, NSACR)
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@ -317,9 +331,7 @@ DEFINE_DCOP_PARAM_FUNC(cvac, DCCMVAC)
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#define IS_IN_SVC() (GET_M32(read_cpsr()) == MODE32_svc)
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#define IS_IN_MON() (GET_M32(read_cpsr()) == MODE32_mon)
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#define IS_IN_EL2() IS_IN_HYP()
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/*
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* If EL3 is AArch32, then secure PL1 and monitor mode correspond to EL3
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*/
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/* If EL3 is AArch32, then secure PL1 and monitor mode correspond to EL3 */
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#define IS_IN_EL3() \
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((GET_M32(read_cpsr()) == MODE32_mon) || \
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(IS_IN_SECURE() && (GET_M32(read_cpsr()) != MODE32_usr)))
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@ -355,7 +367,15 @@ static inline unsigned int get_current_el(void)
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#define read_ctr_el0() read_ctr()
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#define write_icc_sgi0r_el1(_v) \
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write64_icc_sgi0r_el1(_v)
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#define write_icc_sgi0r_el1(_v) write64_icc_sgi0r_el1(_v)
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#define read_daif() read_cpsr()
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#define write_daif(flags) write_cpsr(flags)
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#define read_cnthp_cval_el2() read64_cnthp_cval_el2()
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#define write_cnthp_cval_el2(v) write64_cnthp_cval_el2(v)
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#define read_amcntenset0_el0() read_amcntenset0()
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#define read_amcntenset1_el0() read_amcntenset1()
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#endif /* ARCH_HELPERS_H */
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@ -35,12 +35,14 @@
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#define MPIDR_AFF1_SHIFT U(8)
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#define MPIDR_AFF2_SHIFT U(16)
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#define MPIDR_AFF3_SHIFT U(32)
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#define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT
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#define MPIDR_AFFINITY_MASK ULL(0xff00ffffff)
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#define MPIDR_AFFLVL_SHIFT U(3)
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#define MPIDR_AFFLVL0 U(0x0)
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#define MPIDR_AFFLVL1 U(0x1)
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#define MPIDR_AFFLVL2 U(0x2)
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#define MPIDR_AFFLVL3 U(0x3)
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#define MPIDR_AFFLVL0 ULL(0x0)
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#define MPIDR_AFFLVL1 ULL(0x1)
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#define MPIDR_AFFLVL2 ULL(0x2)
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#define MPIDR_AFFLVL3 ULL(0x3)
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#define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n
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#define MPIDR_AFFLVL0_VAL(mpidr) \
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(((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK)
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#define MPIDR_AFFLVL1_VAL(mpidr) \
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@ -56,28 +58,42 @@
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*/
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#define MPIDR_MAX_AFFLVL U(2)
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/* Constant to highlight the assumption that MPIDR allocation starts from 0 */
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#define FIRST_MPIDR ULL(0)
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#define MPID_MASK (MPIDR_MT_MASK | \
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(MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \
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(MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \
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(MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \
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(MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT))
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#define MPIDR_AFF_ID(mpid, n) \
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(((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK)
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/*
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* An invalid MPID. This value can be used by functions that return an MPID to
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* indicate an error.
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*/
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#define INVALID_MPID U(0xFFFFFFFF)
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/*******************************************************************************
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* Definitions for CPU system register interface to GICv3
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******************************************************************************/
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#define ICC_SRE_EL1 S3_0_C12_C12_5
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#define ICC_SRE_EL2 S3_4_C12_C9_5
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#define ICC_SRE_EL3 S3_6_C12_C12_5
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#define ICC_CTLR_EL1 S3_0_C12_C12_4
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#define ICC_CTLR_EL3 S3_6_C12_C12_4
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#define ICC_PMR_EL1 S3_0_C4_C6_0
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#define ICC_RPR_EL1 S3_0_C12_C11_3
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#define ICC_IGRPEN1_EL3 S3_6_c12_c12_7
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#define ICC_IGRPEN0_EL1 S3_0_c12_c12_6
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#define ICC_HPPIR0_EL1 S3_0_c12_c8_2
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#define ICC_HPPIR1_EL1 S3_0_c12_c12_2
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#define ICC_IAR0_EL1 S3_0_c12_c8_0
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#define ICC_IAR1_EL1 S3_0_c12_c12_0
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#define ICC_EOIR0_EL1 S3_0_c12_c8_1
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#define ICC_EOIR1_EL1 S3_0_c12_c12_1
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#define ICC_SGI0R_EL1 S3_0_c12_c11_7
|
||||
#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7
|
||||
#define ICC_SGI1R S3_0_C12_C11_5
|
||||
#define ICC_SRE_EL1 S3_0_C12_C12_5
|
||||
#define ICC_SRE_EL2 S3_4_C12_C9_5
|
||||
#define ICC_SRE_EL3 S3_6_C12_C12_5
|
||||
#define ICC_CTLR_EL1 S3_0_C12_C12_4
|
||||
#define ICC_CTLR_EL3 S3_6_C12_C12_4
|
||||
#define ICC_PMR_EL1 S3_0_C4_C6_0
|
||||
#define ICC_RPR_EL1 S3_0_C12_C11_3
|
||||
#define ICC_IGRPEN1_EL3 S3_6_c12_c12_7
|
||||
#define ICC_IGRPEN0_EL1 S3_0_c12_c12_6
|
||||
#define ICC_HPPIR0_EL1 S3_0_c12_c8_2
|
||||
#define ICC_HPPIR1_EL1 S3_0_c12_c12_2
|
||||
#define ICC_IAR0_EL1 S3_0_c12_c8_0
|
||||
#define ICC_IAR1_EL1 S3_0_c12_c12_0
|
||||
#define ICC_EOIR0_EL1 S3_0_c12_c8_1
|
||||
#define ICC_EOIR1_EL1 S3_0_c12_c12_1
|
||||
#define ICC_SGI0R_EL1 S3_0_c12_c11_7
|
||||
|
||||
/*******************************************************************************
|
||||
* Generic timer memory mapped registers & offsets
|
||||
|
|
@ -140,6 +156,25 @@
|
|||
#define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0)
|
||||
#define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf)
|
||||
|
||||
/* ID_AA64ISAR1_EL1 definitions */
|
||||
#define ID_AA64ISAR1_GPI_SHIFT U(28)
|
||||
#define ID_AA64ISAR1_GPI_WIDTH U(4)
|
||||
#define ID_AA64ISAR1_GPA_SHIFT U(24)
|
||||
#define ID_AA64ISAR1_GPA_WIDTH U(4)
|
||||
#define ID_AA64ISAR1_API_SHIFT U(8)
|
||||
#define ID_AA64ISAR1_API_WIDTH U(4)
|
||||
#define ID_AA64ISAR1_APA_SHIFT U(4)
|
||||
#define ID_AA64ISAR1_APA_WIDTH U(4)
|
||||
|
||||
#define ID_AA64ISAR1_GPI_MASK \
|
||||
(((ULL(1) << ID_AA64ISAR1_GPI_WIDTH) - ULL(1)) << ID_AA64ISAR1_GPI_SHIFT)
|
||||
#define ID_AA64ISAR1_GPA_MASK \
|
||||
(((ULL(1) << ID_AA64ISAR1_GPA_WIDTH) - ULL(1)) << ID_AA64ISAR1_GPA_SHIFT)
|
||||
#define ID_AA64ISAR1_API_MASK \
|
||||
(((ULL(1) << ID_AA64ISAR1_API_WIDTH) - ULL(1)) << ID_AA64ISAR1_API_SHIFT)
|
||||
#define ID_AA64ISAR1_APA_MASK \
|
||||
(((ULL(1) << ID_AA64ISAR1_APA_WIDTH) - ULL(1)) << ID_AA64ISAR1_APA_SHIFT)
|
||||
|
||||
#define PARANGE_0000 U(32)
|
||||
#define PARANGE_0001 U(36)
|
||||
#define PARANGE_0010 U(40)
|
||||
|
|
@ -278,6 +313,7 @@
|
|||
/* HCR definitions */
|
||||
#define HCR_API_BIT (ULL(1) << 41)
|
||||
#define HCR_APK_BIT (ULL(1) << 40)
|
||||
#define HCR_TGE_BIT (ULL(1) << 27)
|
||||
#define HCR_RW_SHIFT U(31)
|
||||
#define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT)
|
||||
#define HCR_AMO_BIT (ULL(1) << 5)
|
||||
|
|
@ -351,6 +387,8 @@
|
|||
#define DISABLE_ALL_EXCEPTIONS \
|
||||
(DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT)
|
||||
|
||||
#define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT)
|
||||
|
||||
/*
|
||||
* RMR_EL3 definitions
|
||||
*/
|
||||
|
|
@ -360,12 +398,12 @@
|
|||
/*
|
||||
* HI-VECTOR address for AArch32 state
|
||||
*/
|
||||
#define HI_VECTOR_BASE U(0xFFFF0000)
|
||||
#define HI_VECTOR_BASE U(0xFFFF0000)
|
||||
|
||||
/*
|
||||
* TCR defintions
|
||||
*/
|
||||
#define TCR_EL3_RES1 ((U(1) << 31) | (U(1) << 23))
|
||||
#define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23))
|
||||
#define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23))
|
||||
#define TCR_EL1_IPS_SHIFT U(32)
|
||||
#define TCR_EL2_PS_SHIFT U(16)
|
||||
|
|
@ -571,10 +609,17 @@
|
|||
#define CNTACR_RWPT_SHIFT U(0x5)
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions of register offsets in the CNTBaseN Frame of the
|
||||
* Definitions of register offsets and fields in the CNTBaseN Frame of the
|
||||
* system level implementation of the Generic Timer.
|
||||
******************************************************************************/
|
||||
#define CNTBASE_CNTFRQ U(0x10)
|
||||
/* Physical Count register. */
|
||||
#define CNTPCT_LO U(0x0)
|
||||
/* Counter Frequency register. */
|
||||
#define CNTBASEN_CNTFRQ U(0x10)
|
||||
/* Physical Timer CompareValue register. */
|
||||
#define CNTP_CVAL_LO U(0x20)
|
||||
/* Physical Timer Control register. */
|
||||
#define CNTP_CTL U(0x2c)
|
||||
|
||||
/* PMCR_EL0 definitions */
|
||||
#define PMCR_EL0_RESET_VAL U(0x0)
|
||||
|
|
@ -753,7 +798,22 @@
|
|||
#define ERXCTLR_EL1 S3_0_C5_C4_1
|
||||
#define ERXSTATUS_EL1 S3_0_C5_C4_2
|
||||
#define ERXADDR_EL1 S3_0_C5_C4_3
|
||||
#define ERXPFGF_EL1 S3_0_C5_C4_4
|
||||
#define ERXPFGCTL_EL1 S3_0_C5_C4_5
|
||||
#define ERXPFGCDN_EL1 S3_0_C5_C4_6
|
||||
#define ERXMISC0_EL1 S3_0_C5_C5_0
|
||||
#define ERXMISC1_EL1 S3_0_C5_C5_1
|
||||
|
||||
#define ERXCTLR_ED_BIT (U(1) << 0)
|
||||
#define ERXCTLR_UE_BIT (U(1) << 4)
|
||||
|
||||
#define ERXPFGCTL_UC_BIT (U(1) << 1)
|
||||
#define ERXPFGCTL_UEU_BIT (U(1) << 2)
|
||||
#define ERXPFGCTL_CDEN_BIT (U(1) << 31)
|
||||
|
||||
/*******************************************************************************
|
||||
* Armv8.3 Pointer Authentication Registers
|
||||
*******************************************************************************/
|
||||
#define APGAKeyLo_EL1 S3_0_C2_C3_0
|
||||
|
||||
#endif /* ARCH_H */
|
||||
|
|
|
|||
|
|
@ -7,8 +7,8 @@
|
|||
#ifndef ARCH_HELPERS_H
|
||||
#define ARCH_HELPERS_H
|
||||
|
||||
#include <arch.h> /* for additional register definitions */
|
||||
#include <cdefs.h> /* For __dead2 */
|
||||
#include <arch.h>
|
||||
#include <cdefs.h>
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
|
|
@ -179,11 +179,13 @@ void disable_mmu_icache_el3(void);
|
|||
#define write_daifclr(val) SYSREG_WRITE_CONST(daifclr, val)
|
||||
#define write_daifset(val) SYSREG_WRITE_CONST(daifset, val)
|
||||
|
||||
DEFINE_SYSREG_READ_FUNC(par_el1)
|
||||
DEFINE_SYSREG_RW_FUNCS(par_el1)
|
||||
DEFINE_SYSREG_READ_FUNC(id_pfr1_el1)
|
||||
DEFINE_SYSREG_READ_FUNC(id_aa64isar1_el1)
|
||||
DEFINE_SYSREG_READ_FUNC(id_aa64pfr0_el1)
|
||||
DEFINE_SYSREG_READ_FUNC(id_aa64dfr0_el1)
|
||||
DEFINE_SYSREG_READ_FUNC(CurrentEl)
|
||||
DEFINE_SYSREG_READ_FUNC(ctr_el0)
|
||||
DEFINE_SYSREG_RW_FUNCS(daif)
|
||||
DEFINE_SYSREG_RW_FUNCS(spsr_el1)
|
||||
DEFINE_SYSREG_RW_FUNCS(spsr_el2)
|
||||
|
|
@ -202,14 +204,20 @@ DEFINE_SYSOP_TYPE_FUNC(dmb, ld)
|
|||
DEFINE_SYSOP_TYPE_FUNC(dsb, ish)
|
||||
DEFINE_SYSOP_TYPE_FUNC(dsb, nsh)
|
||||
DEFINE_SYSOP_TYPE_FUNC(dsb, ishst)
|
||||
DEFINE_SYSOP_TYPE_FUNC(dmb, ish)
|
||||
DEFINE_SYSOP_TYPE_FUNC(dmb, oshld)
|
||||
DEFINE_SYSOP_TYPE_FUNC(dmb, oshst)
|
||||
DEFINE_SYSOP_TYPE_FUNC(dmb, osh)
|
||||
DEFINE_SYSOP_TYPE_FUNC(dmb, nshld)
|
||||
DEFINE_SYSOP_TYPE_FUNC(dmb, nshst)
|
||||
DEFINE_SYSOP_TYPE_FUNC(dmb, nsh)
|
||||
DEFINE_SYSOP_TYPE_FUNC(dmb, ishld)
|
||||
DEFINE_SYSOP_TYPE_FUNC(dmb, ishst)
|
||||
DEFINE_SYSOP_TYPE_FUNC(dmb, ish)
|
||||
DEFINE_SYSOP_FUNC(isb)
|
||||
|
||||
uint32_t get_afflvl_shift(uint32_t);
|
||||
uint32_t mpidr_mask_lower_afflvls(uint64_t, uint32_t);
|
||||
|
||||
|
||||
void __dead2 eret(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3,
|
||||
uint64_t x4, uint64_t x5, uint64_t x6, uint64_t x7);
|
||||
void __dead2 smc(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3,
|
||||
|
|
@ -286,9 +294,15 @@ DEFINE_SYSREG_RW_FUNCS(cptr_el3)
|
|||
|
||||
DEFINE_SYSREG_RW_FUNCS(cpacr_el1)
|
||||
DEFINE_SYSREG_RW_FUNCS(cntfrq_el0)
|
||||
DEFINE_SYSREG_RW_FUNCS(cnthp_ctl_el2)
|
||||
DEFINE_SYSREG_RW_FUNCS(cnthp_tval_el2)
|
||||
DEFINE_SYSREG_RW_FUNCS(cnthp_cval_el2)
|
||||
DEFINE_SYSREG_RW_FUNCS(cntps_ctl_el1)
|
||||
DEFINE_SYSREG_RW_FUNCS(cntps_tval_el1)
|
||||
DEFINE_SYSREG_RW_FUNCS(cntps_cval_el1)
|
||||
DEFINE_SYSREG_RW_FUNCS(cntp_ctl_el0)
|
||||
DEFINE_SYSREG_RW_FUNCS(cntp_tval_el0)
|
||||
DEFINE_SYSREG_RW_FUNCS(cntp_cval_el0)
|
||||
DEFINE_SYSREG_READ_FUNC(cntpct_el0)
|
||||
DEFINE_SYSREG_RW_FUNCS(cnthctl_el2)
|
||||
|
||||
|
|
@ -298,24 +312,23 @@ DEFINE_SYSREG_RW_FUNCS(cntvoff_el2)
|
|||
|
||||
DEFINE_SYSREG_RW_FUNCS(vpidr_el2)
|
||||
DEFINE_SYSREG_RW_FUNCS(vmpidr_el2)
|
||||
DEFINE_SYSREG_RW_FUNCS(cntp_ctl_el0)
|
||||
|
||||
DEFINE_SYSREG_READ_FUNC(isr_el1)
|
||||
|
||||
DEFINE_SYSREG_READ_FUNC(ctr_el0)
|
||||
|
||||
DEFINE_SYSREG_RW_FUNCS(mdcr_el2)
|
||||
DEFINE_SYSREG_RW_FUNCS(mdcr_el3)
|
||||
DEFINE_SYSREG_RW_FUNCS(hstr_el2)
|
||||
DEFINE_SYSREG_RW_FUNCS(cnthp_ctl_el2)
|
||||
DEFINE_SYSREG_RW_FUNCS(pmcr_el0)
|
||||
|
||||
/* GICv3 System Registers */
|
||||
|
||||
DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el1, ICC_SRE_EL1)
|
||||
DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el2, ICC_SRE_EL2)
|
||||
DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el3, ICC_SRE_EL3)
|
||||
DEFINE_RENAME_SYSREG_RW_FUNCS(icc_pmr_el1, ICC_PMR_EL1)
|
||||
DEFINE_RENAME_SYSREG_READ_FUNC(icc_rpr_el1, ICC_RPR_EL1)
|
||||
DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen1_el3, ICC_IGRPEN1_EL3)
|
||||
DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen1_el1, ICC_IGRPEN1_EL1)
|
||||
DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen0_el1, ICC_IGRPEN0_EL1)
|
||||
DEFINE_RENAME_SYSREG_READ_FUNC(icc_hppir0_el1, ICC_HPPIR0_EL1)
|
||||
DEFINE_RENAME_SYSREG_READ_FUNC(icc_hppir1_el1, ICC_HPPIR1_EL1)
|
||||
|
|
@ -324,6 +337,7 @@ DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar1_el1, ICC_IAR1_EL1)
|
|||
DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir0_el1, ICC_EOIR0_EL1)
|
||||
DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir1_el1, ICC_EOIR1_EL1)
|
||||
DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_sgi0r_el1, ICC_SGI0R_EL1)
|
||||
DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sgi1r, ICC_SGI1R)
|
||||
|
||||
DEFINE_RENAME_SYSREG_RW_FUNCS(amcgcr_el0, AMCGCR_EL0)
|
||||
DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr0_el0, AMCNTENCLR0_EL0)
|
||||
|
|
@ -351,11 +365,14 @@ DEFINE_RENAME_SYSREG_READ_FUNC(erxaddr_el1, ERXADDR_EL1)
|
|||
DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc0_el1, ERXMISC0_EL1)
|
||||
DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc1_el1, ERXMISC1_EL1)
|
||||
|
||||
/* Armv8.3 Pointer Authentication Registers */
|
||||
DEFINE_RENAME_SYSREG_RW_FUNCS(apgakeylo_el1, APGAKeyLo_EL1)
|
||||
|
||||
#define IS_IN_EL(x) \
|
||||
(GET_EL(read_CurrentEl()) == MODE_EL##x)
|
||||
|
||||
#define IS_IN_EL1() IS_IN_EL(1)
|
||||
#define IS_IN_EL3() IS_IN_EL(3)
|
||||
#define IS_IN_EL2() IS_IN_EL(2)
|
||||
#define IS_IN_EL3() IS_IN_EL(3)
|
||||
|
||||
static inline unsigned int get_current_el(void)
|
||||
|
|
|
|||
|
|
@ -160,5 +160,6 @@
|
|||
*/
|
||||
#define ASSERT_SYM_PTR_ALIGN(sym) assert(((size_t)(sym) % __alignof__(*(sym))) == 0)
|
||||
|
||||
#define COMPILER_BARRIER() __asm__ volatile ("" ::: "memory")
|
||||
|
||||
#endif /* UTILS_DEF_H */
|
||||
|
|
|
|||
|
|
@ -128,10 +128,10 @@ void arm_configure_sys_timer(void)
|
|||
/*
|
||||
* Initialize CNTFRQ register in Non-secure CNTBase frame.
|
||||
* This is only required for Juno, because it doesn't follow ARM ARM
|
||||
* in that the value updated in CNTFRQ is not reflected in CNTBASE_CNTFRQ.
|
||||
* Hence update the value manually.
|
||||
* in that the value updated in CNTFRQ is not reflected in
|
||||
* CNTBASEN_CNTFRQ. Hence update the value manually.
|
||||
*/
|
||||
mmio_write_32(ARM_SYS_CNT_BASE_NS + CNTBASE_CNTFRQ, freq_val);
|
||||
mmio_write_32(ARM_SYS_CNT_BASE_NS + CNTBASEN_CNTFRQ, freq_val);
|
||||
#endif
|
||||
}
|
||||
#endif /* ARM_SYS_TIMCTL_BASE */
|
||||
|
|
|
|||
Loading…
Reference in New Issue