From 93a5b97ec9e97207769db18ae34886e6b8bf2ea4 Mon Sep 17 00:00:00 2001 From: Sieu Mun Tang Date: Wed, 27 Apr 2022 18:57:29 +0800 Subject: [PATCH] feat(intel): add SMC support for Get USERCODE This patch adds SMC support for enquiring FPGA's User Code. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi Signed-off-by: Jit Loon Lim Signed-off-by: Sieu Mun Tang Change-Id: I82c1fa9390b6f7509b2284d51e199fb8b6a9b1ad --- .../soc/common/include/socfpga_mailbox.h | 1 + .../soc/common/include/socfpga_sip_svc.h | 2 ++ plat/intel/soc/common/socfpga_sip_svc.c | 19 +++++++++++++++++++ 3 files changed, 22 insertions(+) diff --git a/plat/intel/soc/common/include/socfpga_mailbox.h b/plat/intel/soc/common/include/socfpga_mailbox.h index e1c128b21..09dd117f3 100644 --- a/plat/intel/soc/common/include/socfpga_mailbox.h +++ b/plat/intel/soc/common/include/socfpga_mailbox.h @@ -42,6 +42,7 @@ #define MBOX_CMD_CANCEL 0x03 #define MBOX_CMD_VAB_SRC_CERT 0x0B #define MBOX_CMD_GET_IDCODE 0x10 +#define MBOX_CMD_GET_USERCODE 0x13 #define MBOX_CMD_REBOOT_HPS 0x47 /* Reconfiguration Commands */ diff --git a/plat/intel/soc/common/include/socfpga_sip_svc.h b/plat/intel/soc/common/include/socfpga_sip_svc.h index de60bc0d2..0f3cc09bb 100644 --- a/plat/intel/soc/common/include/socfpga_sip_svc.h +++ b/plat/intel/soc/common/include/socfpga_sip_svc.h @@ -62,6 +62,8 @@ #define INTEL_SIP_SMC_FIRMWARE_VERSION 0xC200001F #define INTEL_SIP_SMC_HPS_SET_BRIDGES 0xC2000032 +/* Mailbox Command */ +#define INTEL_SIP_SMC_GET_USERCODE 0xC200003D /* SiP Definitions */ diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c index a77dbd75d..ece235268 100644 --- a/plat/intel/soc/common/socfpga_sip_svc.c +++ b/plat/intel/soc/common/socfpga_sip_svc.c @@ -482,6 +482,21 @@ static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, return INTEL_SIP_SMC_STATUS_OK; } +static int intel_smc_get_usercode(uint32_t *user_code) +{ + int status; + unsigned int resp_len = sizeof(user_code) / MBOX_WORD_BYTE; + + status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_GET_USERCODE, NULL, + 0U, CMD_CASUAL, user_code, &resp_len); + + if (status < 0) { + return INTEL_SIP_SMC_STATUS_ERROR; + } + + return INTEL_SIP_SMC_STATUS_OK; +} + /* Miscellaneous HPS services */ static uint32_t intel_hps_set_bridges(uint64_t enable) { @@ -649,6 +664,10 @@ uintptr_t sip_smc_handler(uint32_t smc_fid, &len_in_resp); SMC_RET3(handle, status, mbox_status, len_in_resp); + case INTEL_SIP_SMC_GET_USERCODE: + status = intel_smc_get_usercode(&retval); + SMC_RET2(handle, status, retval); + case INTEL_SIP_SMC_GET_ROM_PATCH_SHA384: status = intel_fcs_get_rom_patch_sha384(x1, &retval64, &mbox_error);