corstone700: clean-up as per coding style guide
Running checkpatch.pl on the codebase and making required changes Change-Id: I7d3f8764cef632ab2a6d3c355c68f590440b85b8 Signed-off-by: Avinash Mehta <avinash.mehta@arm.com> Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
This commit is contained in:
Avinash Mehta
Abdellatif El Khlifi
parent
c6fe43b726
commit
93cf1f6454
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -8,8 +8,8 @@
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#include <plat/common/platform.h>
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/* The Corstone700 power domain tree descriptor */
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static unsigned char corstone700_power_domain_tree_desc
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[PLAT_ARM_CLUSTER_COUNT + 2];
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static unsigned char corstone700_power_domain_tree_desc[PLAT_ARM_CLUSTER_COUNT
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+ 2];
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/*******************************************************************************
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* This function dynamically constructs the topology according to
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* CLUSTER_COUNT and returns it.
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@ -17,12 +17,14 @@
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#define CORSTONE700_CLUSTER_COUNT U(1)
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#define CORSTONE700_MAX_CPUS_PER_CLUSTER U(4)
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#define CORSTONE700_MAX_PE_PER_CPU U(1)
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#define CORSTONE700_CORE_COUNT (CORSTONE700_CLUSTER_COUNT * \
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CORSTONE700_MAX_CPUS_PER_CLUSTER * \
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CORSTONE700_MAX_PE_PER_CPU)
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#define PLATFORM_CORE_COUNT CORSTONE700_CORE_COUNT
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#define PLAT_ARM_CLUSTER_COUNT CORSTONE700_CLUSTER_COUNT
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#define PLATFORM_CORE_COUNT (PLAT_ARM_CLUSTER_COUNT * \
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CORSTONE700_MAX_CPUS_PER_CLUSTER * \
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CORSTONE700_MAX_PE_PER_CPU)
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/* UART related constants */
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#define PLAT_ARM_BOOT_UART_BASE 0x1a510000
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#define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ
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@ -85,12 +87,12 @@
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ARM_BL_REGIONS)
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/* GIC related constants */
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#define PLAT_ARM_GICD_BASE 0x1C010000
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#define PLAT_ARM_GICC_BASE 0x1C02F000
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#define PLAT_ARM_GICD_BASE 0x1C010000
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#define PLAT_ARM_GICC_BASE 0x1C02F000
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/* MHUv2 Secure Channel receiver and sender */
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#define PLAT_SDK700_MHU0_SEND 0x1B800000
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#define PLAT_SDK700_MHU0_RECV 0x1B810000
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#define PLAT_SDK700_MHU0_SEND 0x1B800000
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#define PLAT_SDK700_MHU0_RECV 0x1B810000
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/* Timer/watchdog related constants */
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#define ARM_SYS_CNTCTL_BASE UL(0x1a200000)
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@ -105,46 +107,46 @@
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* Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The
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* power levels have a 1:1 mapping with the MPIDR affinity levels.
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*/
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#define ARM_PWR_LVL0 MPIDR_AFFLVL0
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#define ARM_PWR_LVL1 MPIDR_AFFLVL1
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#define ARM_PWR_LVL2 MPIDR_AFFLVL2
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#define ARM_PWR_LVL0 MPIDR_AFFLVL0
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#define ARM_PWR_LVL1 MPIDR_AFFLVL1
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#define ARM_PWR_LVL2 MPIDR_AFFLVL2
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/*
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* Macros for local power states in ARM platforms encoded by State-ID field
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* within the power-state parameter.
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*/
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/* Local power state for power domains in Run state. */
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#define ARM_LOCAL_STATE_RUN U(0)
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#define ARM_LOCAL_STATE_RUN U(0)
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/* Local power state for retention. Valid only for CPU power domains */
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#define ARM_LOCAL_STATE_RET U(1)
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#define ARM_LOCAL_STATE_RET U(1)
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/* Local power state for OFF/power-down. Valid for CPU and cluster
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* power domains
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*/
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#define ARM_LOCAL_STATE_OFF U(2)
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#define ARM_LOCAL_STATE_OFF U(2)
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#define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE
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#define PLAT_ARM_NSTIMER_FRAME_ID U(1)
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#define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE
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#define PLAT_ARM_NSTIMER_FRAME_ID U(1)
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#define PLAT_ARM_NS_IMAGE_OFFSET (ARM_DRAM1_BASE + UL(0x8000000))
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#define PLAT_ARM_NS_IMAGE_OFFSET (ARM_DRAM1_BASE + UL(0x8000000))
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
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/*
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* This macro defines the deepest retention state possible. A higher state
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* ID will represent an invalid or a power down state.
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*/
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#define PLAT_MAX_RET_STATE 1
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#define PLAT_MAX_RET_STATE 1
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/*
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* This macro defines the deepest power down states possible. Any state ID
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* higher than this is invalid.
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*/
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#define PLAT_MAX_OFF_STATE 2
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#define PLAT_MAX_OFF_STATE 2
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#define PLATFORM_STACK_SIZE UL(0x440)
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#define PLATFORM_STACK_SIZE UL(0x440)
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#define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \
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#define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \
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ARM_SHARED_RAM_BASE, \
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ARM_SHARED_RAM_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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@ -174,21 +176,21 @@
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#define CORSTONE700_DEVICE_BASE (0x1A000000)
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#define CORSTONE700_DEVICE_SIZE (0x26000000)
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#define CORSTONE700_MAP_DEVICE MAP_REGION_FLAT( \
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CORSTONE700_DEVICE_BASE, \
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CORSTONE700_DEVICE_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define CORSTONE700_MAP_DEVICE MAP_REGION_FLAT( \
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CORSTONE700_DEVICE_BASE,\
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CORSTONE700_DEVICE_SIZE,\
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MT_DEVICE | MT_RW | MT_SECURE)
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#define ARM_IRQ_SEC_PHY_TIMER 29
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#define ARM_IRQ_SEC_PHY_TIMER 29
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#define ARM_IRQ_SEC_SGI_0 8
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#define ARM_IRQ_SEC_SGI_1 9
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#define ARM_IRQ_SEC_SGI_2 10
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#define ARM_IRQ_SEC_SGI_3 11
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#define ARM_IRQ_SEC_SGI_4 12
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#define ARM_IRQ_SEC_SGI_5 13
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#define ARM_IRQ_SEC_SGI_6 14
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#define ARM_IRQ_SEC_SGI_7 15
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#define ARM_IRQ_SEC_SGI_0 8
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#define ARM_IRQ_SEC_SGI_1 9
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#define ARM_IRQ_SEC_SGI_2 10
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#define ARM_IRQ_SEC_SGI_3 11
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#define ARM_IRQ_SEC_SGI_4 12
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#define ARM_IRQ_SEC_SGI_5 13
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#define ARM_IRQ_SEC_SGI_6 14
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#define ARM_IRQ_SEC_SGI_7 15
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/*
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* Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3
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@ -196,7 +198,7 @@
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* as Group 0 interrupts.
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*/
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#define ARM_G1S_IRQ_PROPS(grp) \
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INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \
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INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \
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(grp), GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \
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(grp), GIC_INTR_CFG_EDGE), \
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@ -221,11 +223,11 @@
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* as Group 0 interrupts.
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*/
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#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
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ARM_G1S_IRQ_PROPS(grp), \
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INTR_PROP_DESC(CORSTONE700_IRQ_TZ_WDOG, \
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GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(CORSTONE700_IRQ_SEC_SYS_TIMER, \
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GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_LEVEL) \
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ARM_G1S_IRQ_PROPS(grp), \
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INTR_PROP_DESC(CORSTONE700_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, \
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(grp), GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(CORSTONE700_IRQ_SEC_SYS_TIMER, \
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GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_LEVEL)
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#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp)
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