corstone700: clean-up as per coding style guide
Running checkpatch.pl on the codebase and making required changes Change-Id: I7d3f8764cef632ab2a6d3c355c68f590440b85b8 Signed-off-by: Avinash Mehta <avinash.mehta@arm.com> Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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@ -8,8 +8,8 @@
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#include <plat/common/platform.h>
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#include <plat/common/platform.h>
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/* The Corstone700 power domain tree descriptor */
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/* The Corstone700 power domain tree descriptor */
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static unsigned char corstone700_power_domain_tree_desc
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static unsigned char corstone700_power_domain_tree_desc[PLAT_ARM_CLUSTER_COUNT
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[PLAT_ARM_CLUSTER_COUNT + 2];
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+ 2];
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/*******************************************************************************
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/*******************************************************************************
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* This function dynamically constructs the topology according to
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* This function dynamically constructs the topology according to
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* CLUSTER_COUNT and returns it.
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* CLUSTER_COUNT and returns it.
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@ -17,11 +17,13 @@
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#define CORSTONE700_CLUSTER_COUNT U(1)
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#define CORSTONE700_CLUSTER_COUNT U(1)
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#define CORSTONE700_MAX_CPUS_PER_CLUSTER U(4)
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#define CORSTONE700_MAX_CPUS_PER_CLUSTER U(4)
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#define CORSTONE700_MAX_PE_PER_CPU U(1)
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#define CORSTONE700_MAX_PE_PER_CPU U(1)
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#define CORSTONE700_CORE_COUNT (CORSTONE700_CLUSTER_COUNT * \
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#define PLAT_ARM_CLUSTER_COUNT CORSTONE700_CLUSTER_COUNT
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#define PLATFORM_CORE_COUNT (PLAT_ARM_CLUSTER_COUNT * \
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CORSTONE700_MAX_CPUS_PER_CLUSTER * \
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CORSTONE700_MAX_CPUS_PER_CLUSTER * \
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CORSTONE700_MAX_PE_PER_CPU)
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CORSTONE700_MAX_PE_PER_CPU)
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#define PLATFORM_CORE_COUNT CORSTONE700_CORE_COUNT
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#define PLAT_ARM_CLUSTER_COUNT CORSTONE700_CLUSTER_COUNT
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/* UART related constants */
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/* UART related constants */
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#define PLAT_ARM_BOOT_UART_BASE 0x1a510000
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#define PLAT_ARM_BOOT_UART_BASE 0x1a510000
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@ -175,8 +177,8 @@
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#define CORSTONE700_DEVICE_BASE (0x1A000000)
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#define CORSTONE700_DEVICE_BASE (0x1A000000)
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#define CORSTONE700_DEVICE_SIZE (0x26000000)
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#define CORSTONE700_DEVICE_SIZE (0x26000000)
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#define CORSTONE700_MAP_DEVICE MAP_REGION_FLAT( \
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#define CORSTONE700_MAP_DEVICE MAP_REGION_FLAT( \
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CORSTONE700_DEVICE_BASE, \
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CORSTONE700_DEVICE_BASE,\
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CORSTONE700_DEVICE_SIZE, \
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CORSTONE700_DEVICE_SIZE,\
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MT_DEVICE | MT_RW | MT_SECURE)
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MT_DEVICE | MT_RW | MT_SECURE)
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#define ARM_IRQ_SEC_PHY_TIMER 29
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#define ARM_IRQ_SEC_PHY_TIMER 29
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@ -222,10 +224,10 @@
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*/
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*/
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#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
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#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
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ARM_G1S_IRQ_PROPS(grp), \
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ARM_G1S_IRQ_PROPS(grp), \
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INTR_PROP_DESC(CORSTONE700_IRQ_TZ_WDOG, \
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INTR_PROP_DESC(CORSTONE700_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, \
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GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_LEVEL), \
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(grp), GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(CORSTONE700_IRQ_SEC_SYS_TIMER, \
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INTR_PROP_DESC(CORSTONE700_IRQ_SEC_SYS_TIMER, \
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GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_LEVEL) \
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GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_LEVEL)
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#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp)
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#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp)
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