Tegra: implement per-SoC validate_power_state() handler
The validate_power_state() handler checks the power_state for a valid afflvl and state id. Although the afflvl check is common, the state ids are implementation defined. This patch moves the handler to the tegra/soc folder to allow each SoC to validate the power_state for supported parameters. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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@ -51,27 +51,27 @@ static int system_suspended;
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* The following platform setup functions are weakly defined. They
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* provide typical implementations that will be overridden by a SoC.
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*/
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#pragma weak tegra_prepare_cpu_suspend
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#pragma weak tegra_prepare_cpu_on
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#pragma weak tegra_prepare_cpu_off
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#pragma weak tegra_prepare_cpu_on_finish
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#pragma weak tegra_soc_prepare_cpu_suspend
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#pragma weak tegra_soc_prepare_cpu_on
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#pragma weak tegra_soc_prepare_cpu_off
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#pragma weak tegra_soc_prepare_cpu_on_finish
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int tegra_prepare_cpu_suspend(unsigned int id, unsigned int afflvl)
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int tegra_soc_prepare_cpu_suspend(unsigned int id, unsigned int afflvl)
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{
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return PSCI_E_NOT_SUPPORTED;
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}
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int tegra_prepare_cpu_on(unsigned long mpidr)
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int tegra_soc_prepare_cpu_on(unsigned long mpidr)
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{
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return PSCI_E_SUCCESS;
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}
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int tegra_prepare_cpu_off(unsigned long mpidr)
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int tegra_soc_prepare_cpu_off(unsigned long mpidr)
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{
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return PSCI_E_SUCCESS;
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}
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int tegra_prepare_cpu_on_finish(unsigned long mpidr)
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int tegra_soc_prepare_cpu_on_finish(unsigned long mpidr)
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{
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return PSCI_E_SUCCESS;
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}
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@ -134,17 +134,7 @@ unsigned int tegra_get_sys_suspend_power_state(void)
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******************************************************************************/
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int32_t tegra_validate_power_state(unsigned int power_state)
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{
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/* Sanity check the requested state */
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if (psci_get_pstate_type(power_state) == PSTATE_TYPE_STANDBY) {
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/*
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* It's possible to enter standby only on affinity level 0 i.e.
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* a cpu on Tegra. Ignore any other affinity level.
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*/
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if (psci_get_pstate_afflvl(power_state) != MPIDR_AFFLVL0)
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return PSCI_E_INVALID_PARAMS;
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}
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return PSCI_E_SUCCESS;
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return tegra_soc_validate_power_state(power_state);
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}
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/*******************************************************************************
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@ -171,7 +161,7 @@ int tegra_affinst_on(unsigned long mpidr,
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sec_entry_point[cpu] = sec_entrypoint;
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flush_dcache_range((uint64_t)&sec_entry_point[cpu], sizeof(uint64_t));
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return tegra_prepare_cpu_on(mpidr);
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return tegra_soc_prepare_cpu_on(mpidr);
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}
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/*******************************************************************************
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@ -194,7 +184,7 @@ void tegra_affinst_off(unsigned int afflvl, unsigned int state)
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if (afflvl > MPIDR_AFFLVL0)
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return;
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tegra_prepare_cpu_off(read_mpidr());
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tegra_soc_prepare_cpu_off(read_mpidr());
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}
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/*******************************************************************************
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@ -227,7 +217,7 @@ void tegra_affinst_suspend(unsigned long sec_entrypoint,
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sec_entry_point[cpu] = sec_entrypoint;
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flush_dcache_range((uint64_t)&sec_entry_point[cpu], sizeof(uint64_t));
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tegra_prepare_cpu_suspend(id, afflvl);
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tegra_soc_prepare_cpu_suspend(id, afflvl);
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/* disable GICC */
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tegra_gic_cpuif_deactivate();
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@ -280,7 +270,7 @@ void tegra_affinst_on_finish(unsigned int afflvl, unsigned int state)
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/*
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* Reset hardware settings.
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*/
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tegra_prepare_cpu_on_finish(read_mpidr());
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tegra_soc_prepare_cpu_on_finish(read_mpidr());
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}
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/*******************************************************************************
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@ -338,7 +328,7 @@ int platform_setup_pm(const plat_pm_ops_t **plat_ops)
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/*
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* Reset hardware settings.
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*/
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tegra_prepare_cpu_on_finish(read_mpidr());
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tegra_soc_prepare_cpu_on_finish(read_mpidr());
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/*
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* Initialize PM ops struct
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@ -45,6 +45,9 @@ typedef struct plat_params_from_bl2 {
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uintptr_t bl32_params;
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} plat_params_from_bl2_t;
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/* Declarations for plat_psci_handlers.c */
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int32_t tegra_soc_validate_power_state(unsigned int power_state);
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/* Declarations for plat_setup.c */
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const mmap_region_t *plat_get_mmio_map(void);
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uint64_t plat_get_syscnt_freq(void);
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@ -49,7 +49,35 @@
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static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER];
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int tegra_prepare_cpu_suspend(unsigned int id, unsigned int afflvl)
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int32_t tegra_soc_validate_power_state(unsigned int power_state)
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{
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/* Sanity check the requested afflvl */
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if (psci_get_pstate_type(power_state) == PSTATE_TYPE_STANDBY) {
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/*
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* It's possible to enter standby only on affinity level 0 i.e.
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* a cpu on Tegra. Ignore any other affinity level.
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*/
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if (psci_get_pstate_afflvl(power_state) != MPIDR_AFFLVL0)
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return PSCI_E_INVALID_PARAMS;
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}
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/* Sanity check the requested state id */
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switch (psci_get_pstate_id(power_state)) {
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case PSTATE_ID_CORE_POWERDN:
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case PSTATE_ID_CLUSTER_IDLE:
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case PSTATE_ID_CLUSTER_POWERDN:
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case PSTATE_ID_SOC_POWERDN:
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break;
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default:
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ERROR("unsupported state id\n");
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return PSCI_E_NOT_SUPPORTED;
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}
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return PSCI_E_SUCCESS;
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}
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int tegra_soc_prepare_cpu_suspend(unsigned int id, unsigned int afflvl)
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{
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/* There's nothing to be done for affinity level 1 */
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if (afflvl == MPIDR_AFFLVL1)
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@ -90,7 +118,7 @@ int tegra_prepare_cpu_suspend(unsigned int id, unsigned int afflvl)
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return PSCI_E_NOT_SUPPORTED;
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}
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int tegra_prepare_cpu_on_finish(unsigned long mpidr)
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int tegra_soc_prepare_cpu_on_finish(unsigned long mpidr)
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{
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/*
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* Check if we are exiting from SOC_POWERDN.
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@ -120,7 +148,7 @@ int tegra_prepare_cpu_on_finish(unsigned long mpidr)
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return PSCI_E_SUCCESS;
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}
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int tegra_prepare_cpu_on(unsigned long mpidr)
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int tegra_soc_prepare_cpu_on(unsigned long mpidr)
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{
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int cpu = mpidr & MPIDR_CPU_MASK;
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uint32_t mask = CPU_CORE_RESET_MASK << cpu;
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@ -139,7 +167,7 @@ int tegra_prepare_cpu_on(unsigned long mpidr)
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return PSCI_E_SUCCESS;
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}
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int tegra_prepare_cpu_off(unsigned long mpidr)
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int tegra_soc_prepare_cpu_off(unsigned long mpidr)
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{
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tegra_fc_cpu_off(mpidr & MPIDR_CPU_MASK);
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return PSCI_E_SUCCESS;
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