plat/arm/sgi: add secure memory support for sgi575 and sgiclarka
Remove the platform common plat_arm_security_setup function to allow platform specific implementations of the security setup function implemented in the board directory of the platform. For use by secure software, configure region0 of DMC-620 trustzone controller to protect the upper 16MB of memory of the first DRAM block from non-secure accesses. Change-Id: I9a8c19656702c4fa4f6917b3655b692d443bb568 Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
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9d3b191a48
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9427c745e3
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@ -8,11 +8,16 @@
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#define PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <sgi_base_platform_def.h>
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#include <sgi_base_platform_def.h>
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#include <utils_def.h>
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#define PLAT_ARM_CLUSTER_COUNT 2
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#define PLAT_ARM_CLUSTER_COUNT 2
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#define CSS_SGI_MAX_CPUS_PER_CLUSTER 4
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#define CSS_SGI_MAX_CPUS_PER_CLUSTER 4
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#define CSS_SGI_MAX_PE_PER_CPU 1
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#define CSS_SGI_MAX_PE_PER_CPU 1
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#define PLAT_CSS_MHU_BASE 0x45000000
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#define PLAT_CSS_MHU_BASE UL(0x45000000)
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/* Base address of DMC-620 instances */
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#define SGI575_DMC620_BASE0 UL(0x4e000000)
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#define SGI575_DMC620_BASE1 UL(0x4e100000)
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#endif /* PLATFORM_DEF_H */
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#endif /* PLATFORM_DEF_H */
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@ -14,7 +14,9 @@ SGI_CPU_SOURCES := lib/cpus/aarch64/cortex_a75.S
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BL1_SOURCES += ${SGI_CPU_SOURCES}
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BL1_SOURCES += ${SGI_CPU_SOURCES}
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BL2_SOURCES += lib/utils/mem_region.c \
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BL2_SOURCES += ${SGI575_BASE}/sgi575_security.c \
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drivers/arm/tzc/tzc_dmc620.c \
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lib/utils/mem_region.c \
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plat/arm/common/arm_nor_psci_mem_protect.c
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plat/arm/common/arm_nor_psci_mem_protect.c
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BL31_SOURCES += ${SGI_CPU_SOURCES} \
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BL31_SOURCES += ${SGI_CPU_SOURCES} \
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@ -0,0 +1,39 @@
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <debug.h>
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#include <platform_def.h>
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#include <tzc_dmc620.h>
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uintptr_t sgi575_dmc_base[] = {
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SGI575_DMC620_BASE0,
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SGI575_DMC620_BASE1
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};
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static const tzc_dmc620_driver_data_t sgi575_plat_driver_data = {
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.dmc_base = sgi575_dmc_base,
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.dmc_count = ARRAY_SIZE(sgi575_dmc_base)
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};
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static const tzc_dmc620_acc_addr_data_t sgi575_acc_addr_data[] = {
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{
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.region_base = ARM_AP_TZC_DRAM1_BASE,
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.region_top = ARM_AP_TZC_DRAM1_BASE + ARM_TZC_DRAM1_SIZE - 1,
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.sec_attr = TZC_DMC620_REGION_S_RDWR
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}
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};
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static const tzc_dmc620_config_data_t sgi575_plat_config_data = {
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.plat_drv_data = &sgi575_plat_driver_data,
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.plat_acc_addr_data = sgi575_acc_addr_data,
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.acc_addr_count = ARRAY_SIZE(sgi575_acc_addr_data)
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};
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/* Initialize the secure environment */
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void plat_arm_security_setup(void)
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{
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arm_tzc_dmc620_setup(&sgi575_plat_config_data);
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}
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@ -8,11 +8,16 @@
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#define PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <sgi_base_platform_def.h>
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#include <sgi_base_platform_def.h>
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#include <utils_def.h>
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#define PLAT_ARM_CLUSTER_COUNT 2
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#define PLAT_ARM_CLUSTER_COUNT 2
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#define CSS_SGI_MAX_CPUS_PER_CLUSTER 4
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#define CSS_SGI_MAX_CPUS_PER_CLUSTER 4
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#define CSS_SGI_MAX_PE_PER_CPU 1
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#define CSS_SGI_MAX_PE_PER_CPU 1
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#define PLAT_CSS_MHU_BASE 0x45400000
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#define PLAT_CSS_MHU_BASE UL(0x45400000)
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/* Base address of DMC-620 instances */
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#define SGICLARKA_DMC620_BASE0 UL(0x4e000000)
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#define SGICLARKA_DMC620_BASE1 UL(0x4e100000)
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#endif /* PLATFORM_DEF_H */
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#endif /* PLATFORM_DEF_H */
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@ -14,7 +14,9 @@ SGI_CPU_SOURCES := lib/cpus/aarch64/cortex_ares.S
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BL1_SOURCES += ${SGI_CPU_SOURCES}
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BL1_SOURCES += ${SGI_CPU_SOURCES}
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BL2_SOURCES += lib/utils/mem_region.c \
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BL2_SOURCES += ${SGICLARKA_BASE}/sgiclarka_security.c \
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drivers/arm/tzc/tzc_dmc620.c \
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lib/utils/mem_region.c \
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plat/arm/common/arm_nor_psci_mem_protect.c
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plat/arm/common/arm_nor_psci_mem_protect.c
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BL31_SOURCES += ${SGI_CPU_SOURCES} \
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BL31_SOURCES += ${SGI_CPU_SOURCES} \
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@ -0,0 +1,39 @@
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <debug.h>
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#include <platform_def.h>
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#include <tzc_dmc620.h>
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uintptr_t sgiclarka_dmc_base[] = {
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SGICLARKA_DMC620_BASE0,
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SGICLARKA_DMC620_BASE1
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};
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static const tzc_dmc620_driver_data_t sgiclarka_plat_driver_data = {
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.dmc_base = sgiclarka_dmc_base,
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.dmc_count = ARRAY_SIZE(sgiclarka_dmc_base)
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};
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static const tzc_dmc620_acc_addr_data_t sgiclarka_acc_addr_data[] = {
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{
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.region_base = ARM_AP_TZC_DRAM1_BASE,
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.region_top = ARM_AP_TZC_DRAM1_BASE + ARM_TZC_DRAM1_SIZE - 1,
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.sec_attr = TZC_DMC620_REGION_S_RDWR
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}
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};
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static const tzc_dmc620_config_data_t sgiclarka_plat_config_data = {
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.plat_drv_data = &sgiclarka_plat_driver_data,
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.plat_acc_addr_data = sgiclarka_acc_addr_data,
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.acc_addr_count = ARRAY_SIZE(sgiclarka_acc_addr_data)
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};
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/* Initialize the secure environment */
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void plat_arm_security_setup(void)
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{
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arm_tzc_dmc620_setup(&sgiclarka_plat_config_data);
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}
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@ -35,8 +35,7 @@ PLAT_BL_COMMON_SOURCES += ${CSS_ENT_BASE}/sgi_plat.c \
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BL1_SOURCES += ${INTERCONNECT_SOURCES}
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BL1_SOURCES += ${INTERCONNECT_SOURCES}
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BL2_SOURCES += ${CSS_ENT_BASE}/sgi_security.c \
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BL2_SOURCES += ${CSS_ENT_BASE}/sgi_image_load.c
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${CSS_ENT_BASE}/sgi_image_load.c
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BL31_SOURCES += ${INTERCONNECT_SOURCES} \
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BL31_SOURCES += ${INTERCONNECT_SOURCES} \
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${ENT_GIC_SOURCES} \
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${ENT_GIC_SOURCES} \
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@ -1,15 +0,0 @@
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arm_config.h>
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#include <plat_arm.h>
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/*
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* We assume that all security programming is done by the primary core.
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*/
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void plat_arm_security_setup(void)
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{
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}
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