From bc1a573d5519f121cb872fce1d88fe2e0db07b2c Mon Sep 17 00:00:00 2001 From: "Abdul Halim, Muhammad Hadi Asyrafi" Date: Wed, 5 Aug 2020 22:12:23 +0800 Subject: [PATCH 01/19] fix(intel): refactor NOC header Refactor NOC header to be shareable across both Stratix 10 and Agilex platforms. This patch also removes redundant NOC declarations in system manager header file. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi Change-Id: I6348b67a8b54c2ad19327d6b8c25ae37d25e4b4a Signed-off-by: Jit Loon Lim --- plat/intel/soc/agilex/include/agilex_noc.h | 2 +- .../soc/agilex/include/socfpga_plat_def.h | 2 + plat/intel/soc/common/include/socfpga_noc.h | 82 +++++++++++++++++++ .../common/include/socfpga_system_manager.h | 61 -------------- .../soc/common/soc/socfpga_system_manager.c | 11 +-- .../soc/stratix10/include/socfpga_plat_def.h | 3 +- 6 files changed, 93 insertions(+), 68 deletions(-) create mode 100644 plat/intel/soc/common/include/socfpga_noc.h diff --git a/plat/intel/soc/agilex/include/agilex_noc.h b/plat/intel/soc/agilex/include/agilex_noc.h index 22db3e28f..9aba3c33b 100644 --- a/plat/intel/soc/agilex/include/agilex_noc.h +++ b/plat/intel/soc/agilex/include/agilex_noc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, Intel Corporation. All rights reserved. + * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/plat/intel/soc/agilex/include/socfpga_plat_def.h b/plat/intel/soc/agilex/include/socfpga_plat_def.h index 9c87e450d..6a5cf9b32 100644 --- a/plat/intel/soc/agilex/include/socfpga_plat_def.h +++ b/plat/intel/soc/agilex/include/socfpga_plat_def.h @@ -19,6 +19,8 @@ #define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x2000000 /* Register Mapping */ +#define SOCFPGA_CCU_NOC_REG_BASE 0xf7000000 + #define SOCFPGA_MMC_REG_BASE 0xff808000 #define SOCFPGA_RSTMGR_REG_BASE 0xffd11000 diff --git a/plat/intel/soc/common/include/socfpga_noc.h b/plat/intel/soc/common/include/socfpga_noc.h new file mode 100644 index 000000000..66d0ee72a --- /dev/null +++ b/plat/intel/soc/common/include/socfpga_noc.h @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2020-2022, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SOCFPGA_NOC_H +#define SOCFPGA_NOC_H + +/* Macros */ +#define SOCFPGA_CCU_NOC(_ctrl, _dev) (SOCFPGA_CCU_NOC_REG_BASE \ + + (SOCFPGA_CCU_NOC_##_ctrl##_##_dev)) + +#define SOCFPGA_L4_PER_SCR(_reg) (SOCFPGA_L4_PER_SCR_REG_BASE \ + + (SOCFPGA_NOC_FW_L4_PER_SCR_##_reg)) + +#define SOCFPGA_L4_SYS_SCR(_reg) (SOCFPGA_L4_SYS_SCR_REG_BASE \ + + (SOCFPGA_NOC_FW_L4_SYS_SCR_##_reg)) + +/* L3 Interconnect Register Map */ +#define SOCFPGA_NOC_FW_L4_PER_SCR_NAND_REGISTER 0x0000 +#define SOCFPGA_NOC_FW_L4_PER_SCR_NAND_DATA 0x0004 +#define SOCFPGA_NOC_FW_L4_PER_SCR_USB0_REGISTER 0x000c +#define SOCFPGA_NOC_FW_L4_PER_SCR_USB1_REGISTER 0x0010 +#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_MASTER0 0x001c +#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_MASTER1 0x0020 +#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_SLAVE0 0x0024 +#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_SLAVE1 0x0028 +#define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC0 0x002c +#define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC1 0x0030 +#define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC2 0x0034 +#define SOCFPGA_NOC_FW_L4_PER_SCR_SDMMC 0x0040 +#define SOCFPGA_NOC_FW_L4_PER_SCR_GPIO0 0x0044 +#define SOCFPGA_NOC_FW_L4_PER_SCR_GPIO1 0x0048 +#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C0 0x0050 +#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C1 0x0054 +#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C2 0x0058 +#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C3 0x005c +#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C4 0x0060 +#define SOCFPGA_NOC_FW_L4_PER_SCR_SP_TIMER0 0x0064 +#define SOCFPGA_NOC_FW_L4_PER_SCR_SP_TIMER1 0x0068 +#define SOCFPGA_NOC_FW_L4_PER_SCR_UART0 0x006c +#define SOCFPGA_NOC_FW_L4_PER_SCR_UART1 0x0070 + +#define SOCFPGA_NOC_FW_L4_SYS_SCR_DMA_ECC 0x0008 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC 0x000c +#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC 0x0010 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC 0x0014 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC 0x0018 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC 0x001c +#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC 0x0020 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_ECC 0x002c +#define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_READ_ECC 0x0030 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC 0x0034 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_OCRAM_ECC 0x0038 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_SDMMC_ECC 0x0040 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_USB0_ECC 0x0044 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_USB1_ECC 0x0048 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_CLK_MGR 0x004c +#define SOCFPGA_NOC_FW_L4_SYS_SCR_IO_MGR 0x0054 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_RST_MGR 0x0058 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_SYS_MGR 0x005c +#define SOCFPGA_NOC_FW_L4_SYS_SCR_OSC0_TIMER 0x0060 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_OSC1_TIMER 0x0064 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG0 0x0068 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG1 0x006c +#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG2 0x0070 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG3 0x0074 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_DAP 0x0078 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES 0x0090 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_L4_NOC_QOS 0x0094 + +/* CCU NOC Register Map */ + +#define SOCFPGA_CCU_NOC_CPU0_RAM0 0x04688 +#define SOCFPGA_CCU_NOC_IOM_RAM0 0x18628 + +#define SOCFPGA_CCU_NOC_ADMASK_P_MASK BIT(0) +#define SOCFPGA_CCU_NOC_ADMASK_NS_MASK BIT(1) + +#endif + diff --git a/plat/intel/soc/common/include/socfpga_system_manager.h b/plat/intel/soc/common/include/socfpga_system_manager.h index 2b13f1fd3..b037cc61c 100644 --- a/plat/intel/soc/common/include/socfpga_system_manager.h +++ b/plat/intel/soc/common/include/socfpga_system_manager.h @@ -58,67 +58,6 @@ #define SOCFPGA_SYSMGR(_reg) (SOCFPGA_SYSMGR_REG_BASE \ + (SOCFPGA_SYSMGR_##_reg)) -#define SOCFPGA_L4_PER_SCR(_reg) (SOCFPGA_L4_PER_SCR_REG_BASE \ - + (SOCFPGA_NOC_FW_L4_PER_SCR_##_reg)) - -#define SOCFPGA_L4_SYS_SCR(_reg) (SOCFPGA_L4_SYS_SCR_REG_BASE \ - + (SOCFPGA_NOC_FW_L4_SYS_SCR_##_reg)) - -/* L3 Interconnect Register Map */ -#define SOCFPGA_NOC_FW_L4_PER_SCR_NAND_REGISTER 0x0000 -#define SOCFPGA_NOC_FW_L4_PER_SCR_NAND_DATA 0x0004 -#define SOCFPGA_NOC_FW_L4_PER_SCR_USB0_REGISTER 0x000c -#define SOCFPGA_NOC_FW_L4_PER_SCR_USB1_REGISTER 0x0010 -#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_MASTER0 0x001c -#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_MASTER1 0x0020 -#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_SLAVE0 0x0024 -#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_SLAVE1 0x0028 -#define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC0 0x002c -#define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC1 0x0030 -#define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC2 0x0034 -#define SOCFPGA_NOC_FW_L4_PER_SCR_SDMMC 0x0040 -#define SOCFPGA_NOC_FW_L4_PER_SCR_GPIO0 0x0044 -#define SOCFPGA_NOC_FW_L4_PER_SCR_GPIO1 0x0048 -#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C0 0x0050 -#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C1 0x0054 -#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C2 0x0058 -#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C3 0x005c -#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C4 0x0060 -#define SOCFPGA_NOC_FW_L4_PER_SCR_SP_TIMER0 0x0064 -#define SOCFPGA_NOC_FW_L4_PER_SCR_SP_TIMER1 0x0068 -#define SOCFPGA_NOC_FW_L4_PER_SCR_UART0 0x006c -#define SOCFPGA_NOC_FW_L4_PER_SCR_UART1 0x0070 - -#define SOCFPGA_NOC_FW_L4_SYS_SCR_DMA_ECC 0x0008 -#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC 0x000c -#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC 0x0010 -#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC 0x0014 -#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC 0x0018 -#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC 0x001c -#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC 0x0020 -#define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_ECC 0x002c -#define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_READ_ECC 0x0030 -#define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC 0x0034 -#define SOCFPGA_NOC_FW_L4_SYS_SCR_OCRAM_ECC 0x0038 -#define SOCFPGA_NOC_FW_L4_SYS_SCR_SDMMC_ECC 0x0040 -#define SOCFPGA_NOC_FW_L4_SYS_SCR_USB0_ECC 0x0044 -#define SOCFPGA_NOC_FW_L4_SYS_SCR_USB1_ECC 0x0048 -#define SOCFPGA_NOC_FW_L4_SYS_SCR_CLK_MGR 0x004c -#define SOCFPGA_NOC_FW_L4_SYS_SCR_IO_MGR 0x0054 -#define SOCFPGA_NOC_FW_L4_SYS_SCR_RST_MGR 0x0058 -#define SOCFPGA_NOC_FW_L4_SYS_SCR_SYS_MGR 0x005c -#define SOCFPGA_NOC_FW_L4_SYS_SCR_OSC0_TIMER 0x0060 -#define SOCFPGA_NOC_FW_L4_SYS_SCR_OSC1_TIMER 0x0064 -#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG0 0x0068 -#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG1 0x006c -#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG2 0x0070 -#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG3 0x0074 -#define SOCFPGA_NOC_FW_L4_SYS_SCR_DAP 0x0078 -#define SOCFPGA_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES 0x0090 -#define SOCFPGA_NOC_FW_L4_SYS_SCR_L4_NOC_QOS 0x0094 - -#define SOCFPGA_CCU_NOC_CPU0_RAMSPACE0_0 0xf7004688 -#define SOCFPGA_CCU_NOC_IOM_RAMSPACE0_0 0xf7018628 void enable_ns_peripheral_access(void); void enable_ns_bridge_access(void); diff --git a/plat/intel/soc/common/soc/socfpga_system_manager.c b/plat/intel/soc/common/soc/socfpga_system_manager.c index a64053ca6..ee7c7846d 100644 --- a/plat/intel/soc/common/soc/socfpga_system_manager.c +++ b/plat/intel/soc/common/soc/socfpga_system_manager.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, Intel Corporation. All rights reserved. + * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,6 +7,7 @@ #include #include +#include "socfpga_noc.h" #include "socfpga_system_manager.h" void enable_nonsecure_access(void) @@ -92,10 +93,10 @@ void enable_ns_peripheral_access(void) mmio_write_32(SOCFPGA_L4_SYS_SCR(L4_NOC_QOS), DISABLE_L4_FIREWALL); #if PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10 - mmio_clrbits_32(SOCFPGA_CCU_NOC_CPU0_RAMSPACE0_0, 0x03); - mmio_clrbits_32(SOCFPGA_CCU_NOC_IOM_RAMSPACE0_0, 0x03); - - mmio_write_32(SOCFPGA_SYSMGR(SDMMC), SYSMGR_SDMMC_DRVSEL(3)); + mmio_clrbits_32(SOCFPGA_CCU_NOC(CPU0, RAM0), + SOCFPGA_CCU_NOC_ADMASK_P_MASK | SOCFPGA_CCU_NOC_ADMASK_NS_MASK); + mmio_clrbits_32(SOCFPGA_CCU_NOC(IOM, RAM0), + SOCFPGA_CCU_NOC_ADMASK_P_MASK | SOCFPGA_CCU_NOC_ADMASK_NS_MASK); #endif } diff --git a/plat/intel/soc/stratix10/include/socfpga_plat_def.h b/plat/intel/soc/stratix10/include/socfpga_plat_def.h index b84a56749..2defeb9f4 100644 --- a/plat/intel/soc/stratix10/include/socfpga_plat_def.h +++ b/plat/intel/soc/stratix10/include/socfpga_plat_def.h @@ -1,5 +1,4 @@ /* - * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -19,6 +18,8 @@ #define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x1000000 /* Register Mapping */ +#define SOCFPGA_CCU_NOC_REG_BASE 0xf7000000 + #define SOCFPGA_MMC_REG_BASE 0xff808000 #define SOCFPGA_RSTMGR_REG_BASE 0xffd11000 From afa0b1a82a404c616da2da8f52cdcd587938955f Mon Sep 17 00:00:00 2001 From: "Abdul Halim, Muhammad Hadi Asyrafi" Date: Thu, 6 Aug 2020 10:21:54 +0800 Subject: [PATCH 02/19] feat(intel): create source file for firewall configuration Move codes that previously were part of system_manager driver into firewall driver which are more appropriate based on their functionalities. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi Change-Id: I35e9d792f35ee7491c2f306781417a0c8faae3fd Signed-off-by: Jit Loon Lim --- plat/intel/soc/agilex/platform.mk | 2 +- plat/intel/soc/common/include/socfpga_noc.h | 14 +++++++++++++- .../soc/common/include/socfpga_system_manager.h | 11 ----------- ...socfpga_system_manager.c => socfpga_firewall.c} | 11 +++++++++-- plat/intel/soc/stratix10/platform.mk | 2 +- 5 files changed, 24 insertions(+), 16 deletions(-) rename plat/intel/soc/common/soc/{socfpga_system_manager.c => socfpga_firewall.c} (96%) diff --git a/plat/intel/soc/agilex/platform.mk b/plat/intel/soc/agilex/platform.mk index 10a3eec42..17bfbdd8e 100644 --- a/plat/intel/soc/agilex/platform.mk +++ b/plat/intel/soc/agilex/platform.mk @@ -48,10 +48,10 @@ BL2_SOURCES += \ plat/intel/soc/common/socfpga_image_load.c \ plat/intel/soc/common/socfpga_storage.c \ plat/intel/soc/common/soc/socfpga_emac.c \ + plat/intel/soc/common/soc/socfpga_firewall.c \ plat/intel/soc/common/soc/socfpga_handoff.c \ plat/intel/soc/common/soc/socfpga_mailbox.c \ plat/intel/soc/common/soc/socfpga_reset_manager.c \ - plat/intel/soc/common/soc/socfpga_system_manager.c \ plat/intel/soc/common/drivers/qspi/cadence_qspi.c \ plat/intel/soc/common/drivers/wdt/watchdog.c \ plat/intel/soc/common/drivers/ccu/ncore_ccu.c diff --git a/plat/intel/soc/common/include/socfpga_noc.h b/plat/intel/soc/common/include/socfpga_noc.h index 66d0ee72a..ecf5bcc51 100644 --- a/plat/intel/soc/common/include/socfpga_noc.h +++ b/plat/intel/soc/common/include/socfpga_noc.h @@ -8,6 +8,13 @@ #define SOCFPGA_NOC_H /* Macros */ +#define SCR_AXI_AP_MASK BIT(24) +#define SCR_FPGA2SOC_MASK BIT(16) +#define SCR_MPU_MASK BIT(0) +#define DISABLE_L4_FIREWALL (SCR_AXI_AP_MASK | SCR_FPGA2SOC_MASK \ + | SCR_MPU_MASK) +#define DISABLE_BRIDGE_FIREWALL 0x0ffe0101 + #define SOCFPGA_CCU_NOC(_ctrl, _dev) (SOCFPGA_CCU_NOC_REG_BASE \ + (SOCFPGA_CCU_NOC_##_ctrl##_##_dev)) @@ -78,5 +85,10 @@ #define SOCFPGA_CCU_NOC_ADMASK_P_MASK BIT(0) #define SOCFPGA_CCU_NOC_ADMASK_NS_MASK BIT(1) -#endif +/* Function Definitions */ +void enable_ns_peripheral_access(void); +void enable_ns_bridge_access(void); +void enable_ns_ocram_access(void); + +#endif diff --git a/plat/intel/soc/common/include/socfpga_system_manager.h b/plat/intel/soc/common/include/socfpga_system_manager.h index b037cc61c..a77734d17 100644 --- a/plat/intel/soc/common/include/socfpga_system_manager.h +++ b/plat/intel/soc/common/include/socfpga_system_manager.h @@ -42,13 +42,6 @@ #define IDLE_DATA_SOC2FPGA BIT(4) #define IDLE_DATA_MASK (IDLE_DATA_LWSOC2FPGA | IDLE_DATA_SOC2FPGA) -#define SCR_AXI_AP_MASK BIT(24) -#define SCR_FPGA2SOC_MASK BIT(16) -#define SCR_MPU_MASK BIT(0) -#define DISABLE_L4_FIREWALL (SCR_AXI_AP_MASK | SCR_FPGA2SOC_MASK \ - | SCR_MPU_MASK) -#define DISABLE_BRIDGE_FIREWALL 0x0ffe0101 - #define SYSMGR_ECC_OCRAM_MASK BIT(1) #define SYSMGR_ECC_DDR0_MASK BIT(16) #define SYSMGR_ECC_DDR1_MASK BIT(17) @@ -58,8 +51,4 @@ #define SOCFPGA_SYSMGR(_reg) (SOCFPGA_SYSMGR_REG_BASE \ + (SOCFPGA_SYSMGR_##_reg)) - -void enable_ns_peripheral_access(void); -void enable_ns_bridge_access(void); - #endif /* SOCFPGA_SYSTEMMANAGER_H */ diff --git a/plat/intel/soc/common/soc/socfpga_system_manager.c b/plat/intel/soc/common/soc/socfpga_firewall.c similarity index 96% rename from plat/intel/soc/common/soc/socfpga_system_manager.c rename to plat/intel/soc/common/soc/socfpga_firewall.c index ee7c7846d..b6cf32190 100644 --- a/plat/intel/soc/common/soc/socfpga_system_manager.c +++ b/plat/intel/soc/common/soc/socfpga_firewall.c @@ -8,6 +8,7 @@ #include #include "socfpga_noc.h" +#include "socfpga_plat_def.h" #include "socfpga_system_manager.h" void enable_nonsecure_access(void) @@ -93,12 +94,18 @@ void enable_ns_peripheral_access(void) mmio_write_32(SOCFPGA_L4_SYS_SCR(L4_NOC_QOS), DISABLE_L4_FIREWALL); #if PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10 + enable_ns_ocram_access(); + mmio_write_32(SOCFPGA_SYSMGR(SDMMC), SYSMGR_SDMMC_DRVSEL(3)); +#endif + +} + +void enable_ns_ocram_access(void) +{ mmio_clrbits_32(SOCFPGA_CCU_NOC(CPU0, RAM0), SOCFPGA_CCU_NOC_ADMASK_P_MASK | SOCFPGA_CCU_NOC_ADMASK_NS_MASK); mmio_clrbits_32(SOCFPGA_CCU_NOC(IOM, RAM0), SOCFPGA_CCU_NOC_ADMASK_P_MASK | SOCFPGA_CCU_NOC_ADMASK_NS_MASK); -#endif - } void enable_ns_bridge_access(void) diff --git a/plat/intel/soc/stratix10/platform.mk b/plat/intel/soc/stratix10/platform.mk index d9d88d418..21dc2d44c 100644 --- a/plat/intel/soc/stratix10/platform.mk +++ b/plat/intel/soc/stratix10/platform.mk @@ -47,10 +47,10 @@ BL2_SOURCES += \ plat/intel/soc/common/socfpga_image_load.c \ plat/intel/soc/common/socfpga_storage.c \ plat/intel/soc/common/soc/socfpga_emac.c \ + plat/intel/soc/common/soc/socfpga_firewall.c \ plat/intel/soc/common/soc/socfpga_handoff.c \ plat/intel/soc/common/soc/socfpga_mailbox.c \ plat/intel/soc/common/soc/socfpga_reset_manager.c \ - plat/intel/soc/common/soc/socfpga_system_manager.c \ plat/intel/soc/common/drivers/qspi/cadence_qspi.c \ plat/intel/soc/common/drivers/wdt/watchdog.c From ae19fef33707700a91b0b672aa784e084a6ca500 Mon Sep 17 00:00:00 2001 From: "Abdul Halim, Muhammad Hadi Asyrafi" Date: Wed, 5 Aug 2020 22:40:46 +0800 Subject: [PATCH 03/19] feat(intel): enable firewall for OCRAM in BL31 Set OCRAM as secure region and required privileged access in BL31 to prevent software running in normal world (non-secure) accessing memory region in OCRAM which may contain sensitive information (e.g. FSBL, handoff data) Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi Change-Id: Ib6b24efd69f49cd3f9aa4ef2ea9f1af5ce582bd6 Signed-off-by: Jit Loon Lim --- plat/intel/soc/agilex/bl31_plat_setup.c | 5 ++++- plat/intel/soc/agilex/platform.mk | 4 ++-- plat/intel/soc/common/drivers/ccu/ncore_ccu.c | 1 + plat/intel/soc/common/include/socfpga_noc.h | 1 + plat/intel/soc/common/soc/socfpga_firewall.c | 8 ++++++++ plat/intel/soc/stratix10/bl31_plat_setup.c | 5 ++++- plat/intel/soc/stratix10/platform.mk | 4 ++-- 7 files changed, 22 insertions(+), 6 deletions(-) diff --git a/plat/intel/soc/agilex/bl31_plat_setup.c b/plat/intel/soc/agilex/bl31_plat_setup.c index 66d6b8f48..b1b9514c3 100644 --- a/plat/intel/soc/agilex/bl31_plat_setup.c +++ b/plat/intel/soc/agilex/bl31_plat_setup.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved. - * Copyright (c) 2019-2020, Intel Corporation. All rights reserved. + * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,6 +14,7 @@ #include #include +#include "ccu/ncore_ccu.h" #include "socfpga_mailbox.h" #include "socfpga_private.h" @@ -114,6 +115,8 @@ void bl31_platform_setup(void) (uint64_t)plat_secondary_cpus_bl31_entry); mailbox_hps_stage_notify(HPS_EXECUTION_STATE_SSBL); + + ncore_enable_ocram_firewall(); } const mmap_region_t plat_agilex_mmap[] = { diff --git a/plat/intel/soc/agilex/platform.mk b/plat/intel/soc/agilex/platform.mk index 17bfbdd8e..89df46add 100644 --- a/plat/intel/soc/agilex/platform.mk +++ b/plat/intel/soc/agilex/platform.mk @@ -26,6 +26,7 @@ PLAT_BL_COMMON_SOURCES := \ lib/xlat_tables/xlat_tables_common.c \ plat/intel/soc/common/aarch64/platform_common.c \ plat/intel/soc/common/aarch64/plat_helpers.S \ + plat/intel/soc/common/drivers/ccu/ncore_ccu.c \ plat/intel/soc/common/socfpga_delay_timer.c BL2_SOURCES += \ @@ -53,8 +54,7 @@ BL2_SOURCES += \ plat/intel/soc/common/soc/socfpga_mailbox.c \ plat/intel/soc/common/soc/socfpga_reset_manager.c \ plat/intel/soc/common/drivers/qspi/cadence_qspi.c \ - plat/intel/soc/common/drivers/wdt/watchdog.c \ - plat/intel/soc/common/drivers/ccu/ncore_ccu.c + plat/intel/soc/common/drivers/wdt/watchdog.c BL31_SOURCES += \ drivers/arm/cci/cci.c \ diff --git a/plat/intel/soc/common/drivers/ccu/ncore_ccu.c b/plat/intel/soc/common/drivers/ccu/ncore_ccu.c index d4716cf8a..d9a238ed2 100644 --- a/plat/intel/soc/common/drivers/ccu/ncore_ccu.c +++ b/plat/intel/soc/common/drivers/ccu/ncore_ccu.c @@ -118,6 +118,7 @@ void ncore_enable_ocram_firewall(void) mmio_setbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF4), OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK); } + uint32_t init_ncore_ccu(void) { uint32_t status; diff --git a/plat/intel/soc/common/include/socfpga_noc.h b/plat/intel/soc/common/include/socfpga_noc.h index ecf5bcc51..e3c0f73fb 100644 --- a/plat/intel/soc/common/include/socfpga_noc.h +++ b/plat/intel/soc/common/include/socfpga_noc.h @@ -90,5 +90,6 @@ void enable_ns_peripheral_access(void); void enable_ns_bridge_access(void); void enable_ns_ocram_access(void); +void enable_ocram_firewall(void); #endif diff --git a/plat/intel/soc/common/soc/socfpga_firewall.c b/plat/intel/soc/common/soc/socfpga_firewall.c index b6cf32190..515784bc9 100644 --- a/plat/intel/soc/common/soc/socfpga_firewall.c +++ b/plat/intel/soc/common/soc/socfpga_firewall.c @@ -113,3 +113,11 @@ void enable_ns_bridge_access(void) mmio_write_32(SOCFPGA_SOC2FPGA_SCR_REG_BASE, DISABLE_BRIDGE_FIREWALL); mmio_write_32(SOCFPGA_LWSOC2FPGA_SCR_REG_BASE, DISABLE_BRIDGE_FIREWALL); } + +void enable_ocram_firewall(void) +{ + mmio_setbits_32(SOCFPGA_CCU_NOC(CPU0, RAM0), + SOCFPGA_CCU_NOC_ADMASK_P_MASK | SOCFPGA_CCU_NOC_ADMASK_NS_MASK); + mmio_setbits_32(SOCFPGA_CCU_NOC(IOM, RAM0), + SOCFPGA_CCU_NOC_ADMASK_P_MASK | SOCFPGA_CCU_NOC_ADMASK_NS_MASK); +} diff --git a/plat/intel/soc/stratix10/bl31_plat_setup.c b/plat/intel/soc/stratix10/bl31_plat_setup.c index f804c8ebf..be0fae563 100644 --- a/plat/intel/soc/stratix10/bl31_plat_setup.c +++ b/plat/intel/soc/stratix10/bl31_plat_setup.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved. - * Copyright (c) 2019-2020, Intel Corporation. All rights reserved. + * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,6 +17,7 @@ #include #include "socfpga_mailbox.h" +#include "socfpga_noc.h" #include "socfpga_private.h" #include "socfpga_reset_manager.h" #include "socfpga_system_manager.h" @@ -122,6 +123,8 @@ void bl31_platform_setup(void) (uint64_t)plat_secondary_cpus_bl31_entry); mailbox_hps_stage_notify(HPS_EXECUTION_STATE_SSBL); + + enable_ocram_firewall(); } const mmap_region_t plat_stratix10_mmap[] = { diff --git a/plat/intel/soc/stratix10/platform.mk b/plat/intel/soc/stratix10/platform.mk index 21dc2d44c..b7808ae4f 100644 --- a/plat/intel/soc/stratix10/platform.mk +++ b/plat/intel/soc/stratix10/platform.mk @@ -26,7 +26,8 @@ PLAT_BL_COMMON_SOURCES := \ lib/xlat_tables/xlat_tables_common.c \ plat/intel/soc/common/aarch64/platform_common.c \ plat/intel/soc/common/aarch64/plat_helpers.S \ - plat/intel/soc/common/socfpga_delay_timer.c + plat/intel/soc/common/socfpga_delay_timer.c \ + plat/intel/soc/common/soc/socfpga_firewall.c BL2_SOURCES += \ common/desc_image_load.c \ @@ -47,7 +48,6 @@ BL2_SOURCES += \ plat/intel/soc/common/socfpga_image_load.c \ plat/intel/soc/common/socfpga_storage.c \ plat/intel/soc/common/soc/socfpga_emac.c \ - plat/intel/soc/common/soc/socfpga_firewall.c \ plat/intel/soc/common/soc/socfpga_handoff.c \ plat/intel/soc/common/soc/socfpga_mailbox.c \ plat/intel/soc/common/soc/socfpga_reset_manager.c \ From f0c40b897f8a25bc50c53239dcf750dd395ebabf Mon Sep 17 00:00:00 2001 From: Sieu Mun Tang Date: Wed, 27 Apr 2022 18:24:06 +0800 Subject: [PATCH 04/19] feat(intel): support SiP SVC version This command supports to return SiP SVC major and minor version. Signed-off-by: Sieu Mun Tang Signed-off-by: Jit Loon Lim Change-Id: Ia8bf678b8de0278aeaae748f24bdd05f8c9f9b47 --- plat/intel/soc/common/include/socfpga_sip_svc.h | 7 +++++-- plat/intel/soc/common/socfpga_sip_svc.c | 5 +++++ 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/plat/intel/soc/common/include/socfpga_sip_svc.h b/plat/intel/soc/common/include/socfpga_sip_svc.h index 4d31c779b..df2a2fba4 100644 --- a/plat/intel/soc/common/include/socfpga_sip_svc.h +++ b/plat/intel/soc/common/include/socfpga_sip_svc.h @@ -59,14 +59,17 @@ SYSMGR_ECC_DDR0_MASK |\ SYSMGR_ECC_DDR1_MASK) +/* Non-mailbox SMC Call */ +#define INTEL_SIP_SMC_SVC_VERSION 0xC2000200 + /* SMC function IDs for SiP Service queries */ #define SIP_SVC_CALL_COUNT 0x8200ff00 #define SIP_SVC_UID 0x8200ff01 #define SIP_SVC_VERSION 0x8200ff03 /* SiP Service Calls version numbers */ -#define SIP_SVC_VERSION_MAJOR 0 -#define SIP_SVC_VERSION_MINOR 1 +#define SIP_SVC_VERSION_MAJOR 1 +#define SIP_SVC_VERSION_MINOR 0 /* Structure Definitions */ diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c index 23359579a..a856be429 100644 --- a/plat/intel/soc/common/socfpga_sip_svc.c +++ b/plat/intel/soc/common/socfpga_sip_svc.c @@ -548,6 +548,11 @@ uintptr_t sip_smc_handler(uint32_t smc_fid, &mbox_error); SMC_RET4(handle, status, mbox_error, x1, retval64); + case INTEL_SIP_SMC_SVC_VERSION: + SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, + SIP_SVC_VERSION_MAJOR, + SIP_SVC_VERSION_MINOR); + default: return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags); From ec4f28ecec8887a685d6119c096ad346da1ea53e Mon Sep 17 00:00:00 2001 From: "Abdul Halim, Muhammad Hadi Asyrafi" Date: Fri, 29 May 2020 12:13:17 +0800 Subject: [PATCH 05/19] fix(intel): modify how configuration type is handled This patch creates macros to handle different configuration types. These changes will help in adding new configuration types in the future. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi Signed-off-by: Jit Loon Lim Change-Id: I5826a8e5942228a9ed376212f0df43b1605c0199 --- plat/intel/soc/common/include/socfpga_sip_svc.h | 5 +++++ plat/intel/soc/common/socfpga_sip_svc.c | 13 ++++++++----- 2 files changed, 13 insertions(+), 5 deletions(-) diff --git a/plat/intel/soc/common/include/socfpga_sip_svc.h b/plat/intel/soc/common/include/socfpga_sip_svc.h index df2a2fba4..9ca2bae31 100644 --- a/plat/intel/soc/common/include/socfpga_sip_svc.h +++ b/plat/intel/soc/common/include/socfpga_sip_svc.h @@ -82,6 +82,11 @@ struct fpga_config_info { int block_number; }; +typedef enum { + FULL_CONFIG = 0, + PARTIAL_CONFIG, +} config_type; + /* Function Definitions */ bool is_address_in_ddr_range(uint64_t addr, uint64_t size); diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c index a856be429..e45aaa5bd 100644 --- a/plat/intel/soc/common/socfpga_sip_svc.c +++ b/plat/intel/soc/common/socfpga_sip_svc.c @@ -20,9 +20,10 @@ #define FPGA_CONFIG_BUFFER_SIZE 4 static int current_block, current_buffer; -static int read_block, max_blocks, is_partial_reconfig; +static int read_block, max_blocks; static uint32_t send_id, rcv_id; static uint32_t bytes_per_block, blocks_submitted; +static bool is_full_reconfig; /* SiP Service UUID */ @@ -97,7 +98,7 @@ static uint32_t intel_mailbox_fpga_config_isdone(uint32_t query_type) if (query_type != 1) { /* full reconfiguration */ - if (!is_partial_reconfig) + if (is_full_reconfig) socfpga_bridges_enable(); /* Enable bridge */ } @@ -184,7 +185,7 @@ static int intel_fpga_config_completed_write(uint32_t *completed_addr, return status; } -static int intel_fpga_config_start(uint32_t config_type) +static int intel_fpga_config_start(uint32_t type) { uint32_t argument = 0x1; uint32_t response[3]; @@ -192,7 +193,9 @@ static int intel_fpga_config_start(uint32_t config_type) unsigned int size = 0; unsigned int resp_len = ARRAY_SIZE(response); - is_partial_reconfig = config_type; + if ((config_type)type == FULL_CONFIG) { + is_full_reconfig = true; + } mailbox_clear_response(); @@ -223,7 +226,7 @@ static int intel_fpga_config_start(uint32_t config_type) current_buffer = 0; /* full reconfiguration */ - if (!is_partial_reconfig) { + if (is_full_reconfig) { /* Disable bridge */ socfpga_bridges_disable(); } From 7e954dfc2ba83262f7596dd0f17de75163e49e5e Mon Sep 17 00:00:00 2001 From: Siew Chin Lim Date: Tue, 11 May 2021 21:12:22 +0800 Subject: [PATCH 06/19] feat(intel): allow to access all register addresses if DEBUG=1 Allow to access all register addresses from SMC call if compile the code with DEBUG=1 for debugging purpose. Signed-off-by: Siew Chin Lim Signed-off-by: Jit Loon Lim Change-Id: Idd31827fb71307efbdbcceeaa05f6cb072842e10 --- plat/intel/soc/common/socfpga_sip_svc.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c index e45aaa5bd..5b08653ad 100644 --- a/plat/intel/soc/common/socfpga_sip_svc.c +++ b/plat/intel/soc/common/socfpga_sip_svc.c @@ -290,6 +290,10 @@ static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size) static int is_out_of_sec_range(uint64_t reg_addr) { +#if DEBUG + return 0; +#endif + switch (reg_addr) { case(0xF8011100): /* ECCCTRL1 */ case(0xF8011104): /* ECCCTRL2 */ From 44eb782e15c9af532f2455b37bd53ca93830f6e2 Mon Sep 17 00:00:00 2001 From: Chee Hong Ang Date: Wed, 13 May 2020 11:44:04 +0800 Subject: [PATCH 07/19] feat(intel): add SMC/PSCI services for DCMF version support Support get/store RSU DCMF version: INTEL_SIP_SMC_RSU_DCMF_VERSION - Get current DCMF version INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION - Store current DCMF version Signed-off-by: Chee Hong Ang Signed-off-by: Jit Loon Lim Change-Id: I85ffbc0efc859736899d4812f040fd7be17c8d8d --- plat/intel/soc/common/socfpga_sip_svc.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c index 5b08653ad..dc3a94b63 100644 --- a/plat/intel/soc/common/socfpga_sip_svc.c +++ b/plat/intel/soc/common/socfpga_sip_svc.c @@ -25,6 +25,9 @@ static uint32_t send_id, rcv_id; static uint32_t bytes_per_block, blocks_submitted; static bool is_full_reconfig; +/* RSU DCMF version */ +static uint32_t rsu_dcmf_ver[4] = {0}; + /* SiP Service UUID */ DEFINE_SVC_UUID2(intl_svc_uid, @@ -400,6 +403,17 @@ static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz, return INTEL_SIP_SMC_STATUS_OK; } +static uint32_t intel_rsu_copy_dcmf_version(uint64_t dcmf_ver_1_0, + uint64_t dcmf_ver_3_2) +{ + rsu_dcmf_ver[0] = dcmf_ver_1_0; + rsu_dcmf_ver[1] = dcmf_ver_1_0 >> 32; + rsu_dcmf_ver[2] = dcmf_ver_3_2; + rsu_dcmf_ver[3] = dcmf_ver_3_2 >> 32; + + return INTEL_SIP_SMC_STATUS_OK; +} + /* Mailbox services */ static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, unsigned int len, @@ -538,6 +552,15 @@ uintptr_t sip_smc_handler(uint32_t smc_fid, SMC_RET2(handle, status, retval); } + case INTEL_SIP_SMC_RSU_DCMF_VERSION: + SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, + ((uint64_t)rsu_dcmf_ver[1] << 32) | rsu_dcmf_ver[0], + ((uint64_t)rsu_dcmf_ver[3] << 32) | rsu_dcmf_ver[2]); + + case INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION: + status = intel_rsu_copy_dcmf_version(x1, x2); + SMC_RET1(handle, status); + case INTEL_SIP_SMC_ECC_DBE: status = intel_ecc_dbe_notification(x1); SMC_RET1(handle, status); From b7f3044e8725d9af997999547630892cf9e2f0ad Mon Sep 17 00:00:00 2001 From: "Abdul Halim, Muhammad Hadi Asyrafi" Date: Thu, 18 Jun 2020 16:21:29 +0800 Subject: [PATCH 08/19] feat(intel): enable SMC SoC FPGA bridges enable/disable Enable SoC FPGA bridges enable/disable from non-secure world through secure monitor calls Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi Change-Id: I4474abab9731923a61ff0e7eb2c2fa32048001cb Signed-off-by: Jit Loon Lim --- plat/intel/soc/common/include/socfpga_sip_svc.h | 1 + plat/intel/soc/common/socfpga_sip_svc.c | 16 ++++++++++++++++ 2 files changed, 17 insertions(+) diff --git a/plat/intel/soc/common/include/socfpga_sip_svc.h b/plat/intel/soc/common/include/socfpga_sip_svc.h index 9ca2bae31..63b28fb98 100644 --- a/plat/intel/soc/common/include/socfpga_sip_svc.h +++ b/plat/intel/soc/common/include/socfpga_sip_svc.h @@ -49,6 +49,7 @@ /* Send Mailbox Command */ #define INTEL_SIP_SMC_MBOX_SEND_CMD 0xC200001E +#define INTEL_SIP_SMC_HPS_SET_BRIDGES 0xC2000032 /* SiP Definitions */ diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c index dc3a94b63..13ef80984 100644 --- a/plat/intel/soc/common/socfpga_sip_svc.c +++ b/plat/intel/soc/common/socfpga_sip_svc.c @@ -440,6 +440,18 @@ static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, return INTEL_SIP_SMC_STATUS_OK; } +/* Miscellaneous HPS services */ +static uint32_t intel_hps_set_bridges(uint64_t enable) +{ + if (enable != 0U) { + socfpga_bridges_enable(); + } else { + socfpga_bridges_disable(); + } + + return INTEL_SIP_SMC_STATUS_OK; +} + /* * This function is responsible for handling all SiP calls from the NS world */ @@ -583,6 +595,10 @@ uintptr_t sip_smc_handler(uint32_t smc_fid, SIP_SVC_VERSION_MAJOR, SIP_SVC_VERSION_MINOR); + case INTEL_SIP_SMC_HPS_SET_BRIDGES: + status = intel_hps_set_bridges(x1); + SMC_RET1(handle, status); + default: return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags); From 4c26957be253a7ab3acb316f42bf3ee10c409ed2 Mon Sep 17 00:00:00 2001 From: Chee Hong Ang Date: Wed, 1 Jul 2020 14:22:25 +0800 Subject: [PATCH 09/19] feat(intel): add RSU 'Max Retry' SiP SMC services Add SiP SMC services to store/retrieve 'Max Retry' counter for Remote System Update (RSU). Signed-off-by: Chee Hong Ang Signed-off-by: Jit Loon Lim Change-Id: I17c1f0107ead64e6160954d26407f399003bcbd9 --- plat/intel/soc/common/include/socfpga_sip_svc.h | 2 ++ plat/intel/soc/common/socfpga_sip_svc.c | 9 +++++++++ 2 files changed, 11 insertions(+) diff --git a/plat/intel/soc/common/include/socfpga_sip_svc.h b/plat/intel/soc/common/include/socfpga_sip_svc.h index 63b28fb98..664611f96 100644 --- a/plat/intel/soc/common/include/socfpga_sip_svc.h +++ b/plat/intel/soc/common/include/socfpga_sip_svc.h @@ -39,6 +39,8 @@ #define INTEL_SIP_SMC_RSU_RETRY_COUNTER 0xC200000F #define INTEL_SIP_SMC_RSU_DCMF_VERSION 0xC2000010 #define INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION 0xC2000011 +#define INTEL_SIP_SMC_RSU_MAX_RETRY 0xC2000012 +#define INTEL_SIP_SMC_RSU_COPY_MAX_RETRY 0xC2000013 /* ECC */ diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c index 13ef80984..daba7f521 100644 --- a/plat/intel/soc/common/socfpga_sip_svc.c +++ b/plat/intel/soc/common/socfpga_sip_svc.c @@ -28,6 +28,8 @@ static bool is_full_reconfig; /* RSU DCMF version */ static uint32_t rsu_dcmf_ver[4] = {0}; +/* RSU Max Retry */ +static uint32_t rsu_max_retry; /* SiP Service UUID */ DEFINE_SVC_UUID2(intl_svc_uid, @@ -573,6 +575,13 @@ uintptr_t sip_smc_handler(uint32_t smc_fid, status = intel_rsu_copy_dcmf_version(x1, x2); SMC_RET1(handle, status); + case INTEL_SIP_SMC_RSU_MAX_RETRY: + SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, rsu_max_retry); + + case INTEL_SIP_SMC_RSU_COPY_MAX_RETRY: + rsu_max_retry = x1; + SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK); + case INTEL_SIP_SMC_ECC_DBE: status = intel_ecc_dbe_notification(x1); SMC_RET1(handle, status); From 984e236e0dee46708534a23c637271a931ceb67e Mon Sep 17 00:00:00 2001 From: Sieu Mun Tang Date: Thu, 28 Apr 2022 22:21:01 +0800 Subject: [PATCH 10/19] feat(intel): add SiP service for DCMF status This patch adds 2 additional RSU SiP services for Intel SoCFPGA platforms: - INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS stores current DCMF status in BL31 - INTEL_SIP_SMC_RSU_DCMF_STATUS is calling function for non-secure software to retrieve stored DCMF status Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi Signed-off-by: Jit Loon Lim Signed-off-by: Sieu Mun Tang Change-Id: Ic7a3e6988c71ad4bf66c58a1d669956524dfdf11 --- .../soc/common/include/socfpga_sip_svc.h | 2 ++ plat/intel/soc/common/socfpga_sip_svc.c | 24 ++++++++++++++++++- 2 files changed, 25 insertions(+), 1 deletion(-) diff --git a/plat/intel/soc/common/include/socfpga_sip_svc.h b/plat/intel/soc/common/include/socfpga_sip_svc.h index 664611f96..aab7bbf35 100644 --- a/plat/intel/soc/common/include/socfpga_sip_svc.h +++ b/plat/intel/soc/common/include/socfpga_sip_svc.h @@ -41,6 +41,8 @@ #define INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION 0xC2000011 #define INTEL_SIP_SMC_RSU_MAX_RETRY 0xC2000012 #define INTEL_SIP_SMC_RSU_COPY_MAX_RETRY 0xC2000013 +#define INTEL_SIP_SMC_RSU_DCMF_STATUS 0xC2000014 +#define INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS 0xC2000015 /* ECC */ diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c index daba7f521..adaa30aca 100644 --- a/plat/intel/soc/common/socfpga_sip_svc.c +++ b/plat/intel/soc/common/socfpga_sip_svc.c @@ -25,11 +25,12 @@ static uint32_t send_id, rcv_id; static uint32_t bytes_per_block, blocks_submitted; static bool is_full_reconfig; -/* RSU DCMF version */ +/* RSU static variables */ static uint32_t rsu_dcmf_ver[4] = {0}; /* RSU Max Retry */ static uint32_t rsu_max_retry; +static uint16_t rsu_dcmf_stat[4] = {0}; /* SiP Service UUID */ DEFINE_SVC_UUID2(intl_svc_uid, @@ -416,6 +417,16 @@ static uint32_t intel_rsu_copy_dcmf_version(uint64_t dcmf_ver_1_0, return INTEL_SIP_SMC_STATUS_OK; } +static uint32_t intel_rsu_copy_dcmf_status(uint64_t dcmf_stat) +{ + rsu_dcmf_stat[0] = 0xFFFF & (dcmf_stat >> (0 * 16)); + rsu_dcmf_stat[1] = 0xFFFF & (dcmf_stat >> (1 * 16)); + rsu_dcmf_stat[2] = 0xFFFF & (dcmf_stat >> (2 * 16)); + rsu_dcmf_stat[3] = 0xFFFF & (dcmf_stat >> (3 * 16)); + + return INTEL_SIP_SMC_STATUS_OK; +} + /* Mailbox services */ static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, unsigned int len, @@ -575,6 +586,17 @@ uintptr_t sip_smc_handler(uint32_t smc_fid, status = intel_rsu_copy_dcmf_version(x1, x2); SMC_RET1(handle, status); + case INTEL_SIP_SMC_RSU_DCMF_STATUS: + SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, + ((uint64_t)rsu_dcmf_stat[3] << 48) | + ((uint64_t)rsu_dcmf_stat[2] << 32) | + ((uint64_t)rsu_dcmf_stat[1] << 16) | + rsu_dcmf_stat[0]); + + case INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS: + status = intel_rsu_copy_dcmf_status(x1); + SMC_RET1(handle, status); + case INTEL_SIP_SMC_RSU_MAX_RETRY: SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, rsu_max_retry); From ef51b097bfa906bf1cee8ee641a1b7bcc8c5f3c0 Mon Sep 17 00:00:00 2001 From: "Abdul Halim, Muhammad Hadi Asyrafi" Date: Thu, 5 Nov 2020 18:00:03 +0800 Subject: [PATCH 11/19] fix(intel): fix fpga config write return mechanism This revert commit 279c8015fefcb544eb311b9052f417fc02ab84aa. The previous change breaks this feature compatibility with Linux driver. Hence, the fix for the earlier issue is going to be fixed in uboot instead. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi Signed-off-by: Jit Loon Lim Signed-off-by: Sieu Mun Tang Change-Id: I93220243bad65ed53322050d990544c7df4ce66b --- plat/intel/soc/common/socfpga_sip_svc.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c index adaa30aca..de47e05f7 100644 --- a/plat/intel/soc/common/socfpga_sip_svc.c +++ b/plat/intel/soc/common/socfpga_sip_svc.c @@ -270,8 +270,9 @@ static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size) intel_fpga_sdm_write_all(); if (!is_address_in_ddr_range(mem, size) || - is_fpga_config_buffer_full()) + is_fpga_config_buffer_full()) { return INTEL_SIP_SMC_STATUS_REJECTED; + } for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE; @@ -288,8 +289,9 @@ static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size) } } - if (is_fpga_config_buffer_full()) + if (is_fpga_config_buffer_full()) { return INTEL_SIP_SMC_STATUS_BUSY; + } return INTEL_SIP_SMC_STATUS_OK; } From e0fc2d1907b1c8a062c44a435be77a12ffeed84b Mon Sep 17 00:00:00 2001 From: "Abdul Halim, Muhammad Hadi Asyrafi" Date: Fri, 20 Nov 2020 11:06:00 +0800 Subject: [PATCH 12/19] fix(intel): use macro as return value SMC function should strictly return INTEL_SIP_SMC_STATUS macro. Directly returning value of variable status might cause confusion in calling software. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi Change-Id: Iea17f4feaa5c917e8b995471f3019dba6ea8dcd3 Signed-off-by: Jit Loon Lim --- plat/intel/soc/common/socfpga_sip_svc.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c index de47e05f7..77b91b284 100644 --- a/plat/intel/soc/common/socfpga_sip_svc.c +++ b/plat/intel/soc/common/socfpga_sip_svc.c @@ -211,8 +211,9 @@ static int intel_fpga_config_start(uint32_t type) status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RECONFIG, &argument, size, CMD_CASUAL, response, &resp_len); - if (status < 0) - return status; + if (status < 0) { + return INTEL_SIP_SMC_STATUS_ERROR; + } max_blocks = response[0]; bytes_per_block = response[1]; @@ -237,7 +238,7 @@ static int intel_fpga_config_start(uint32_t type) socfpga_bridges_disable(); } - return 0; + return INTEL_SIP_SMC_STATUS_OK; } static bool is_fpga_config_buffer_full(void) From 07915a4fd5848fbac69dcbf28f00353eed10a942 Mon Sep 17 00:00:00 2001 From: "Abdul Halim, Muhammad Hadi Asyrafi" Date: Fri, 20 Nov 2020 11:41:59 +0800 Subject: [PATCH 13/19] fix(intel): get config status OK status Config status have different OK requirement between MBOX_CONFIG_STATUS and MBOX_RECONFIG_STATUS request. This patch adds the checking to differentiate between both command. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi Change-Id: I45a4c3de460b031757dbcbd0b3a8055cb0a55aff Signed-off-by: Jit Loon Lim --- plat/intel/soc/common/soc/socfpga_mailbox.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/plat/intel/soc/common/soc/socfpga_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c index be900c967..fbb6b465e 100644 --- a/plat/intel/soc/common/soc/socfpga_mailbox.c +++ b/plat/intel/soc/common/soc/socfpga_mailbox.c @@ -507,11 +507,13 @@ int intel_mailbox_get_config_status(uint32_t cmd, bool init_done) return MBOX_CFGSTAT_STATE_ERROR_HARDWARE; } - if ((res & SOFTFUNC_STATUS_CONF_DONE) == 0U) + if ((res & SOFTFUNC_STATUS_CONF_DONE) == 0U) { return MBOX_CFGSTAT_STATE_CONFIG; + } - if (init_done && (res & SOFTFUNC_STATUS_INIT_DONE) == 0U) + if (init_done && (res & SOFTFUNC_STATUS_INIT_DONE) == 0U) { return MBOX_CFGSTAT_STATE_CONFIG; + } return MBOX_RET_OK; } From 276a43663e8e315fa1bf0aa4824051d88705858b Mon Sep 17 00:00:00 2001 From: Sieu Mun Tang Date: Thu, 28 Apr 2022 22:40:58 +0800 Subject: [PATCH 14/19] fix(intel): bit-wise configuration flag handling Change configuration type handling to bit-wise flag. This is to align with Linux's FPGA Manager definitions and promotes better compatibility. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi Signed-off-by: Jit Loon Lim Signed-off-by: Sieu Mun Tang Change-Id: I5aaf91d3fec538fe3f4fe8395d9adb47ec969434 --- .../soc/common/include/socfpga_sip_svc.h | 25 +++++++++--------- plat/intel/soc/common/socfpga_sip_svc.c | 26 +++++++++++-------- 2 files changed, 28 insertions(+), 23 deletions(-) diff --git a/plat/intel/soc/common/include/socfpga_sip_svc.h b/plat/intel/soc/common/include/socfpga_sip_svc.h index aab7bbf35..2917d0ae1 100644 --- a/plat/intel/soc/common/include/socfpga_sip_svc.h +++ b/plat/intel/soc/common/include/socfpga_sip_svc.h @@ -27,6 +27,12 @@ #define INTEL_SIP_SMC_FPGA_CONFIG_ISDONE 0xC2000004 #define INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM 0xC2000005 +/* FPGA Bitstream Flag */ +#define FLAG_PARTIAL_CONFIG BIT(0) +#define FLAG_AUTHENTICATION BIT(1) +#define CONFIG_TEST_FLAG(_flag, _type) (((flag) & FLAG_##_type) \ + == FLAG_##_type) + /* Secure Register Access */ #define INTEL_SIP_SMC_REG_READ 0xC2000007 #define INTEL_SIP_SMC_REG_WRITE 0xC2000008 @@ -60,21 +66,21 @@ /* ECC DBE */ #define WARM_RESET_WFI_FLAG BIT(31) -#define SYSMGR_ECC_DBE_COLD_RST_MASK (SYSMGR_ECC_OCRAM_MASK |\ +#define SYSMGR_ECC_DBE_COLD_RST_MASK (SYSMGR_ECC_OCRAM_MASK |\ SYSMGR_ECC_DDR0_MASK |\ SYSMGR_ECC_DDR1_MASK) /* Non-mailbox SMC Call */ -#define INTEL_SIP_SMC_SVC_VERSION 0xC2000200 +#define INTEL_SIP_SMC_SVC_VERSION 0xC2000200 /* SMC function IDs for SiP Service queries */ -#define SIP_SVC_CALL_COUNT 0x8200ff00 -#define SIP_SVC_UID 0x8200ff01 -#define SIP_SVC_VERSION 0x8200ff03 +#define SIP_SVC_CALL_COUNT 0x8200ff00 +#define SIP_SVC_UID 0x8200ff01 +#define SIP_SVC_VERSION 0x8200ff03 /* SiP Service Calls version numbers */ -#define SIP_SVC_VERSION_MAJOR 1 -#define SIP_SVC_VERSION_MINOR 0 +#define SIP_SVC_VERSION_MAJOR 1 +#define SIP_SVC_VERSION_MINOR 0 /* Structure Definitions */ @@ -87,11 +93,6 @@ struct fpga_config_info { int block_number; }; -typedef enum { - FULL_CONFIG = 0, - PARTIAL_CONFIG, -} config_type; - /* Function Definitions */ bool is_address_in_ddr_range(uint64_t addr, uint64_t size); diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c index 77b91b284..56a88ab68 100644 --- a/plat/intel/soc/common/socfpga_sip_svc.c +++ b/plat/intel/soc/common/socfpga_sip_svc.c @@ -23,7 +23,7 @@ static int current_block, current_buffer; static int read_block, max_blocks; static uint32_t send_id, rcv_id; static uint32_t bytes_per_block, blocks_submitted; -static bool is_full_reconfig; +static bool bridge_disable; /* RSU static variables */ static uint32_t rsu_dcmf_ver[4] = {0}; @@ -102,10 +102,9 @@ static uint32_t intel_mailbox_fpga_config_isdone(uint32_t query_type) return INTEL_SIP_SMC_STATUS_ERROR; } - if (query_type != 1) { - /* full reconfiguration */ - if (is_full_reconfig) - socfpga_bridges_enable(); /* Enable bridge */ + if (bridge_disable) { + socfpga_bridges_enable(); /* Enable bridge */ + bridge_disable = false; } return INTEL_SIP_SMC_STATUS_OK; @@ -191,7 +190,7 @@ static int intel_fpga_config_completed_write(uint32_t *completed_addr, return status; } -static int intel_fpga_config_start(uint32_t type) +static int intel_fpga_config_start(uint32_t flag) { uint32_t argument = 0x1; uint32_t response[3]; @@ -199,8 +198,13 @@ static int intel_fpga_config_start(uint32_t type) unsigned int size = 0; unsigned int resp_len = ARRAY_SIZE(response); - if ((config_type)type == FULL_CONFIG) { - is_full_reconfig = true; + if (!CONFIG_TEST_FLAG(flag, PARTIAL_CONFIG)) { + bridge_disable = true; + } + + if (CONFIG_TEST_FLAG(flag, AUTHENTICATION)) { + size = 1; + bridge_disable = false; } mailbox_clear_response(); @@ -212,6 +216,7 @@ static int intel_fpga_config_start(uint32_t type) CMD_CASUAL, response, &resp_len); if (status < 0) { + bridge_disable = false; return INTEL_SIP_SMC_STATUS_ERROR; } @@ -232,9 +237,8 @@ static int intel_fpga_config_start(uint32_t type) read_block = 0; current_buffer = 0; - /* full reconfiguration */ - if (is_full_reconfig) { - /* Disable bridge */ + /* Disable bridge on full reconfiguration */ + if (bridge_disable) { socfpga_bridges_disable(); } From e40910e2dc3fa59bcce83ec1cf9a33b3e85012c4 Mon Sep 17 00:00:00 2001 From: "Abdul Halim, Muhammad Hadi Asyrafi" Date: Tue, 29 Dec 2020 16:49:23 +0800 Subject: [PATCH 15/19] fix(intel): configuration status based on start request Configuration status command now returns the result based on the last config start command made to the runtime software. The status type can be either: - NO_REQUEST (default) - RECONFIGURATION - BITSTREAM_AUTH Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi Change-Id: I97406abe09b49b9d9a5b43e62fe09eb23c729bff Signed-off-by: Jit Loon Lim --- plat/intel/soc/common/socfpga_sip_svc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c index 56a88ab68..f583a5572 100644 --- a/plat/intel/soc/common/socfpga_sip_svc.c +++ b/plat/intel/soc/common/socfpga_sip_svc.c @@ -95,7 +95,7 @@ static uint32_t intel_mailbox_fpga_config_isdone(uint32_t query_type) else ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, true); - if (ret) { + if (ret != 0U) { if (ret == MBOX_CFGSTAT_STATE_CONFIG) return INTEL_SIP_SMC_STATUS_BUSY; else From c34b2a7a1a38dba88b6b668a81bd07c757525830 Mon Sep 17 00:00:00 2001 From: "Abdul Halim, Muhammad Hadi Asyrafi" Date: Fri, 5 Feb 2021 11:50:58 +0800 Subject: [PATCH 16/19] feat(intel): add SMC for enquiring firmware version This command allows non-secure world software to enquire the version of currently running Secure Device Manager (SDM) firmware. This will be useful in maintaining backward-compatibility as well as ensuring software cross-compabitility. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi Signed-off-by: Jit Loon Lim Signed-off-by: Sieu Mun Tang Change-Id: Ibc23734d1135db74423da5e29655f9d32472a3b0 --- plat/intel/soc/common/include/socfpga_sip_svc.h | 1 + plat/intel/soc/common/socfpga_sip_svc.c | 11 +++++++++++ 2 files changed, 12 insertions(+) diff --git a/plat/intel/soc/common/include/socfpga_sip_svc.h b/plat/intel/soc/common/include/socfpga_sip_svc.h index 2917d0ae1..de60bc0d2 100644 --- a/plat/intel/soc/common/include/socfpga_sip_svc.h +++ b/plat/intel/soc/common/include/socfpga_sip_svc.h @@ -59,6 +59,7 @@ /* Send Mailbox Command */ #define INTEL_SIP_SMC_MBOX_SEND_CMD 0xC200001E +#define INTEL_SIP_SMC_FIRMWARE_VERSION 0xC200001F #define INTEL_SIP_SMC_HPS_SET_BRIDGES 0xC2000032 diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c index f583a5572..d7733274b 100644 --- a/plat/intel/soc/common/socfpga_sip_svc.c +++ b/plat/intel/soc/common/socfpga_sip_svc.c @@ -435,6 +435,13 @@ static uint32_t intel_rsu_copy_dcmf_status(uint64_t dcmf_stat) } /* Mailbox services */ +static uint32_t intel_smc_fw_version(uint32_t *fw_version) +{ + *fw_version = 0U; + + return INTEL_SIP_SMC_STATUS_OK; +} + static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, unsigned int len, uint32_t urgent, uint32_t *response, @@ -615,6 +622,10 @@ uintptr_t sip_smc_handler(uint32_t smc_fid, status = intel_ecc_dbe_notification(x1); SMC_RET1(handle, status); + case INTEL_SIP_SMC_FIRMWARE_VERSION: + status = intel_smc_fw_version(&retval); + SMC_RET1(handle, status); + case INTEL_SIP_SMC_MBOX_SEND_CMD: x5 = SMC_GET_GP(handle, CTX_GPREG_X5); x6 = SMC_GET_GP(handle, CTX_GPREG_X6); From c026dfe38cfae379457a6ef53130bd5ebc9d7808 Mon Sep 17 00:00:00 2001 From: Sieu Mun Tang Date: Wed, 27 Apr 2022 18:54:10 +0800 Subject: [PATCH 17/19] fix(intel): extend SDM command to return the SDM firmware version Updates intel_smc_fw_version function to read SDM firmware version in major/minor ACDS release number. Update CONFIG_STATUS Response Data [1] bit0-23. Return INTEL_SIP_SMC_STATUS_ERROR if unexpected firmware version is being retrieved. Signed-off-by: Sieu Mun Tang Signed-off-by: Jit Loon Lim Change-Id: I018ccbb961786a75dc6eb873b0f232e71341e1d2 --- .../soc/common/include/socfpga_mailbox.h | 4 ++++ plat/intel/soc/common/socfpga_sip_svc.c | 19 +++++++++++++++++-- 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/plat/intel/soc/common/include/socfpga_mailbox.h b/plat/intel/soc/common/include/socfpga_mailbox.h index a6a3565b5..e1c128b21 100644 --- a/plat/intel/soc/common/include/socfpga_mailbox.h +++ b/plat/intel/soc/common/include/socfpga_mailbox.h @@ -145,6 +145,10 @@ #define RSU_VERSION_ACMF BIT(8) #define RSU_VERSION_ACMF_MASK 0xff00 +/* Config Status Macros */ +#define CONFIG_STATUS_WORD_SIZE 16U +#define CONFIG_STATUS_FW_VER_OFFSET 1 +#define CONFIG_STATUS_FW_VER_MASK 0x00FFFFFF /* Mailbox Function Definitions */ diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c index d7733274b..a77dbd75d 100644 --- a/plat/intel/soc/common/socfpga_sip_svc.c +++ b/plat/intel/soc/common/socfpga_sip_svc.c @@ -437,7 +437,22 @@ static uint32_t intel_rsu_copy_dcmf_status(uint64_t dcmf_stat) /* Mailbox services */ static uint32_t intel_smc_fw_version(uint32_t *fw_version) { - *fw_version = 0U; + int status; + unsigned int resp_len = CONFIG_STATUS_WORD_SIZE; + uint32_t resp_data[CONFIG_STATUS_WORD_SIZE] = {0U}; + + status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CONFIG_STATUS, NULL, 0U, + CMD_CASUAL, resp_data, &resp_len); + + if (status < 0) { + return INTEL_SIP_SMC_STATUS_ERROR; + } + + if (resp_len <= CONFIG_STATUS_FW_VER_OFFSET) { + return INTEL_SIP_SMC_STATUS_ERROR; + } + + *fw_version = resp_data[CONFIG_STATUS_FW_VER_OFFSET] & CONFIG_STATUS_FW_VER_MASK; return INTEL_SIP_SMC_STATUS_OK; } @@ -624,7 +639,7 @@ uintptr_t sip_smc_handler(uint32_t smc_fid, case INTEL_SIP_SMC_FIRMWARE_VERSION: status = intel_smc_fw_version(&retval); - SMC_RET1(handle, status); + SMC_RET2(handle, status, retval); case INTEL_SIP_SMC_MBOX_SEND_CMD: x5 = SMC_GET_GP(handle, CTX_GPREG_X5); From 93a5b97ec9e97207769db18ae34886e6b8bf2ea4 Mon Sep 17 00:00:00 2001 From: Sieu Mun Tang Date: Wed, 27 Apr 2022 18:57:29 +0800 Subject: [PATCH 18/19] feat(intel): add SMC support for Get USERCODE This patch adds SMC support for enquiring FPGA's User Code. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi Signed-off-by: Jit Loon Lim Signed-off-by: Sieu Mun Tang Change-Id: I82c1fa9390b6f7509b2284d51e199fb8b6a9b1ad --- .../soc/common/include/socfpga_mailbox.h | 1 + .../soc/common/include/socfpga_sip_svc.h | 2 ++ plat/intel/soc/common/socfpga_sip_svc.c | 19 +++++++++++++++++++ 3 files changed, 22 insertions(+) diff --git a/plat/intel/soc/common/include/socfpga_mailbox.h b/plat/intel/soc/common/include/socfpga_mailbox.h index e1c128b21..09dd117f3 100644 --- a/plat/intel/soc/common/include/socfpga_mailbox.h +++ b/plat/intel/soc/common/include/socfpga_mailbox.h @@ -42,6 +42,7 @@ #define MBOX_CMD_CANCEL 0x03 #define MBOX_CMD_VAB_SRC_CERT 0x0B #define MBOX_CMD_GET_IDCODE 0x10 +#define MBOX_CMD_GET_USERCODE 0x13 #define MBOX_CMD_REBOOT_HPS 0x47 /* Reconfiguration Commands */ diff --git a/plat/intel/soc/common/include/socfpga_sip_svc.h b/plat/intel/soc/common/include/socfpga_sip_svc.h index de60bc0d2..0f3cc09bb 100644 --- a/plat/intel/soc/common/include/socfpga_sip_svc.h +++ b/plat/intel/soc/common/include/socfpga_sip_svc.h @@ -62,6 +62,8 @@ #define INTEL_SIP_SMC_FIRMWARE_VERSION 0xC200001F #define INTEL_SIP_SMC_HPS_SET_BRIDGES 0xC2000032 +/* Mailbox Command */ +#define INTEL_SIP_SMC_GET_USERCODE 0xC200003D /* SiP Definitions */ diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c index a77dbd75d..ece235268 100644 --- a/plat/intel/soc/common/socfpga_sip_svc.c +++ b/plat/intel/soc/common/socfpga_sip_svc.c @@ -482,6 +482,21 @@ static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, return INTEL_SIP_SMC_STATUS_OK; } +static int intel_smc_get_usercode(uint32_t *user_code) +{ + int status; + unsigned int resp_len = sizeof(user_code) / MBOX_WORD_BYTE; + + status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_GET_USERCODE, NULL, + 0U, CMD_CASUAL, user_code, &resp_len); + + if (status < 0) { + return INTEL_SIP_SMC_STATUS_ERROR; + } + + return INTEL_SIP_SMC_STATUS_OK; +} + /* Miscellaneous HPS services */ static uint32_t intel_hps_set_bridges(uint64_t enable) { @@ -649,6 +664,10 @@ uintptr_t sip_smc_handler(uint32_t smc_fid, &len_in_resp); SMC_RET3(handle, status, mbox_status, len_in_resp); + case INTEL_SIP_SMC_GET_USERCODE: + status = intel_smc_get_usercode(&retval); + SMC_RET2(handle, status, retval); + case INTEL_SIP_SMC_GET_ROM_PATCH_SHA384: status = intel_fcs_get_rom_patch_sha384(x1, &retval64, &mbox_error); From 52cf9c2cd4882534d02e8996e4ff1143ee59290e Mon Sep 17 00:00:00 2001 From: Kris Chaplin Date: Fri, 25 Jun 2021 11:31:52 +0100 Subject: [PATCH 19/19] feat(intel): add SMC support for HWMON voltage and temp sensor Add support to read temperature and voltage using SMC command Signed-off-by: Kris Chaplin Signed-off-by: Jit Loon Lim Change-Id: I806611610043906b720b5096728a5deb5d652b1d --- .../soc/common/include/socfpga_mailbox.h | 7 +++ .../soc/common/include/socfpga_sip_svc.h | 5 +++ plat/intel/soc/common/soc/socfpga_mailbox.c | 19 ++++++++ plat/intel/soc/common/socfpga_sip_svc.c | 45 +++++++++++++++++-- 4 files changed, 72 insertions(+), 4 deletions(-) diff --git a/plat/intel/soc/common/include/socfpga_mailbox.h b/plat/intel/soc/common/include/socfpga_mailbox.h index 09dd117f3..b260a627e 100644 --- a/plat/intel/soc/common/include/socfpga_mailbox.h +++ b/plat/intel/soc/common/include/socfpga_mailbox.h @@ -51,6 +51,11 @@ #define MBOX_RECONFIG_DATA 0x08 #define MBOX_RECONFIG_STATUS 0x09 +/* HWMON Commands */ +#define MBOX_HWMON_READVOLT 0x18 +#define MBOX_HWMON_READTEMP 0x19 + + /* QSPI Commands */ #define MBOX_CMD_QSPI_OPEN 0x32 #define MBOX_CMD_QSPI_CLOSE 0x33 @@ -178,5 +183,7 @@ int mailbox_rsu_get_spt_offset(uint32_t *resp_buf, uint32_t resp_buf_len); int mailbox_rsu_status(uint32_t *resp_buf, uint32_t resp_buf_len); int mailbox_rsu_update(uint32_t *flash_offset); int mailbox_hps_stage_notify(uint32_t execution_stage); +int mailbox_hwmon_readtemp(uint32_t chan, uint32_t *resp_buf); +int mailbox_hwmon_readvolt(uint32_t chan, uint32_t *resp_buf); #endif /* SOCFPGA_MBOX_H */ diff --git a/plat/intel/soc/common/include/socfpga_sip_svc.h b/plat/intel/soc/common/include/socfpga_sip_svc.h index 0f3cc09bb..43f3dc41a 100644 --- a/plat/intel/soc/common/include/socfpga_sip_svc.h +++ b/plat/intel/soc/common/include/socfpga_sip_svc.h @@ -50,6 +50,11 @@ #define INTEL_SIP_SMC_RSU_DCMF_STATUS 0xC2000014 #define INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS 0xC2000015 +/* Hardware monitor */ +#define INTEL_SIP_SMC_HWMON_READTEMP 0xC2000020 +#define INTEL_SIP_SMC_HWMON_READVOLT 0xC2000021 +#define TEMP_CHANNEL_MAX (1 << 15) +#define VOLT_CHANNEL_MAX (1 << 15) /* ECC */ #define INTEL_SIP_SMC_ECC_DBE 0xC200000D diff --git a/plat/intel/soc/common/soc/socfpga_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c index fbb6b465e..8ecd6db60 100644 --- a/plat/intel/soc/common/soc/socfpga_mailbox.c +++ b/plat/intel/soc/common/soc/socfpga_mailbox.c @@ -529,3 +529,22 @@ int intel_mailbox_is_fpga_not_ready(void) return ret; } + +int mailbox_hwmon_readtemp(uint32_t chan, uint32_t *resp_buf) +{ + unsigned int resp_len = sizeof(resp_buf); + + return mailbox_send_cmd(MBOX_JOB_ID, MBOX_HWMON_READTEMP, &chan, 1U, + CMD_CASUAL, resp_buf, + &resp_len); + +} + +int mailbox_hwmon_readvolt(uint32_t chan, uint32_t *resp_buf) +{ + unsigned int resp_len = sizeof(resp_buf); + + return mailbox_send_cmd(MBOX_JOB_ID, MBOX_HWMON_READVOLT, &chan, 1U, + CMD_CASUAL, resp_buf, + &resp_len); +} diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c index ece235268..f22c2ee39 100644 --- a/plat/intel/soc/common/socfpga_sip_svc.c +++ b/plat/intel/soc/common/socfpga_sip_svc.c @@ -90,16 +90,18 @@ static uint32_t intel_mailbox_fpga_config_isdone(uint32_t query_type) { uint32_t ret; - if (query_type == 1) + if (query_type == 1U) { ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS, false); - else + } else { ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, true); + } if (ret != 0U) { - if (ret == MBOX_CFGSTAT_STATE_CONFIG) + if (ret == MBOX_CFGSTAT_STATE_CONFIG) { return INTEL_SIP_SMC_STATUS_BUSY; - else + } else { return INTEL_SIP_SMC_STATUS_ERROR; + } } if (bridge_disable) { @@ -434,6 +436,33 @@ static uint32_t intel_rsu_copy_dcmf_status(uint64_t dcmf_stat) return INTEL_SIP_SMC_STATUS_OK; } +/* Intel HWMON services */ +static uint32_t intel_hwmon_readtemp(uint32_t chan, uint32_t *retval) +{ + if (chan > TEMP_CHANNEL_MAX) { + return INTEL_SIP_SMC_STATUS_ERROR; + } + + if (mailbox_hwmon_readtemp(chan, retval) < 0) { + return INTEL_SIP_SMC_STATUS_ERROR; + } + + return INTEL_SIP_SMC_STATUS_OK; +} + +static uint32_t intel_hwmon_readvolt(uint32_t chan, uint32_t *retval) +{ + if (chan > VOLT_CHANNEL_MAX) { + return INTEL_SIP_SMC_STATUS_ERROR; + } + + if (mailbox_hwmon_readvolt(chan, retval) < 0) { + return INTEL_SIP_SMC_STATUS_ERROR; + } + + return INTEL_SIP_SMC_STATUS_OK; +} + /* Mailbox services */ static uint32_t intel_smc_fw_version(uint32_t *fw_version) { @@ -682,6 +711,14 @@ uintptr_t sip_smc_handler(uint32_t smc_fid, status = intel_hps_set_bridges(x1); SMC_RET1(handle, status); + case INTEL_SIP_SMC_HWMON_READTEMP: + status = intel_hwmon_readtemp(x1, &retval); + SMC_RET2(handle, status, retval); + + case INTEL_SIP_SMC_HWMON_READVOLT: + status = intel_hwmon_readvolt(x1, &retval); + SMC_RET2(handle, status, retval); + default: return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags);