Merge pull request #902 from vwadekar/tegra186-sip-mce-calls
Tegra186: Support AARCH32/64 encoding for MCE calls
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94e0ed6052
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@ -86,7 +86,7 @@ uint64_t tegra_sip_handler(uint32_t smc_fid,
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/* Check if this is a SoC specific SiP */
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err = plat_sip_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags);
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if (err == 0)
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SMC_RET1(handle, err);
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SMC_RET1(handle, (uint64_t)err);
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switch (smc_fid) {
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@ -52,27 +52,27 @@ extern uint32_t tegra186_system_powerdn_state;
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/*******************************************************************************
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* Tegra186 SiP SMCs
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******************************************************************************/
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#define TEGRA_SIP_SYSTEM_SHUTDOWN_STATE 0x82FFFE01
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#define TEGRA_SIP_GET_ACTMON_CLK_COUNTERS 0x82FFFE02
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#define TEGRA_SIP_MCE_CMD_ENTER_CSTATE 0x82FFFF00
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#define TEGRA_SIP_MCE_CMD_UPDATE_CSTATE_INFO 0x82FFFF01
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#define TEGRA_SIP_MCE_CMD_UPDATE_CROSSOVER_TIME 0x82FFFF02
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#define TEGRA_SIP_MCE_CMD_READ_CSTATE_STATS 0x82FFFF03
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#define TEGRA_SIP_MCE_CMD_WRITE_CSTATE_STATS 0x82FFFF04
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#define TEGRA_SIP_MCE_CMD_IS_SC7_ALLOWED 0x82FFFF05
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#define TEGRA_SIP_MCE_CMD_ONLINE_CORE 0x82FFFF06
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#define TEGRA_SIP_MCE_CMD_CC3_CTRL 0x82FFFF07
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#define TEGRA_SIP_MCE_CMD_ECHO_DATA 0x82FFFF08
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#define TEGRA_SIP_MCE_CMD_READ_VERSIONS 0x82FFFF09
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#define TEGRA_SIP_MCE_CMD_ENUM_FEATURES 0x82FFFF0A
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#define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE_TRBITS 0x82FFFF0B
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#define TEGRA_SIP_MCE_CMD_ENUM_READ_MCA 0x82FFFF0C
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#define TEGRA_SIP_MCE_CMD_ENUM_WRITE_MCA 0x82FFFF0D
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#define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE 0x82FFFF0E
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#define TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE 0x82FFFF0F
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#define TEGRA_SIP_MCE_CMD_ENABLE_LATIC 0x82FFFF10
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#define TEGRA_SIP_MCE_CMD_UNCORE_PERFMON_REQ 0x82FFFF11
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#define TEGRA_SIP_MCE_CMD_MISC_CCPLEX 0x82FFFF12
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#define TEGRA_SIP_SYSTEM_SHUTDOWN_STATE 0xC2FFFE01
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#define TEGRA_SIP_GET_ACTMON_CLK_COUNTERS 0xC2FFFE02
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#define TEGRA_SIP_MCE_CMD_ENTER_CSTATE 0xC2FFFF00
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#define TEGRA_SIP_MCE_CMD_UPDATE_CSTATE_INFO 0xC2FFFF01
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#define TEGRA_SIP_MCE_CMD_UPDATE_CROSSOVER_TIME 0xC2FFFF02
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#define TEGRA_SIP_MCE_CMD_READ_CSTATE_STATS 0xC2FFFF03
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#define TEGRA_SIP_MCE_CMD_WRITE_CSTATE_STATS 0xC2FFFF04
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#define TEGRA_SIP_MCE_CMD_IS_SC7_ALLOWED 0xC2FFFF05
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#define TEGRA_SIP_MCE_CMD_ONLINE_CORE 0xC2FFFF06
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#define TEGRA_SIP_MCE_CMD_CC3_CTRL 0xC2FFFF07
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#define TEGRA_SIP_MCE_CMD_ECHO_DATA 0xC2FFFF08
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#define TEGRA_SIP_MCE_CMD_READ_VERSIONS 0xC2FFFF09
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#define TEGRA_SIP_MCE_CMD_ENUM_FEATURES 0xC2FFFF0A
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#define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE_TRBITS 0xC2FFFF0B
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#define TEGRA_SIP_MCE_CMD_ENUM_READ_MCA 0xC2FFFF0C
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#define TEGRA_SIP_MCE_CMD_ENUM_WRITE_MCA 0xC2FFFF0D
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#define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE 0xC2FFFF0E
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#define TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE 0xC2FFFF0F
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#define TEGRA_SIP_MCE_CMD_ENABLE_LATIC 0xC2FFFF10
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#define TEGRA_SIP_MCE_CMD_UNCORE_PERFMON_REQ 0xC2FFFF11
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#define TEGRA_SIP_MCE_CMD_MISC_CCPLEX 0xC2FFFF12
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/*******************************************************************************
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* This function is responsible for handling all T186 SiP calls
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@ -90,8 +90,20 @@ int plat_sip_handler(uint32_t smc_fid,
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int impl, cpu;
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uint32_t base, core_clk_ctr, ref_clk_ctr;
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switch (smc_fid) {
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if (((smc_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_32) {
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/* 32-bit function, clear top parameter bits */
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x1 = (uint32_t)x1;
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x2 = (uint32_t)x2;
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x3 = (uint32_t)x3;
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}
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/*
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* Convert SMC FID to SMC64, to support SMC32/SMC64 configurations
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*/
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smc_fid |= (SMC_64 << FUNCID_CC_SHIFT);
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switch (smc_fid) {
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/*
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* Micro Coded Engine (MCE) commands reside in the 0x82FFFF00 -
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* 0x82FFFFFF SiP SMC space
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@ -120,7 +132,8 @@ int plat_sip_handler(uint32_t smc_fid,
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/* execute the command and store the result */
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mce_ret = mce_command_handler(smc_fid, x1, x2, x3);
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write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X0, mce_ret);
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write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X0,
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(uint64_t)mce_ret);
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return 0;
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@ -176,8 +189,10 @@ int plat_sip_handler(uint32_t smc_fid,
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ref_clk_ctr = mmio_read_32(base + (8 * cpu) + REF_CLK_OFFSET);
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/* return the counter values as two different parameters */
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write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X1, core_clk_ctr);
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write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X2, ref_clk_ctr);
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write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X1,
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(uint64_t)core_clk_ctr);
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write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X2,
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(uint64_t)ref_clk_ctr);
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return 0;
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