Merge pull request #775 from soby-mathew/sm/AArch32_stack_align
AArch32: Fix the stack alignment issue
This commit is contained in:
commit
9509f4f67a
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@ -168,8 +168,11 @@ func handle_smc
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mov r2, r0 /* handle */
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mov r2, r0 /* handle */
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ldcopr r0, SCR
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ldcopr r0, SCR
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/* Save SCR in stack */
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/*
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push {r0}
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* Save SCR in stack. r1 is pushed to meet the 8 byte
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* stack alignment requirement.
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*/
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push {r0, r1}
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and r3, r0, #SCR_NS_BIT /* flags */
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and r3, r0, #SCR_NS_BIT /* flags */
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/* Switch to Secure Mode*/
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/* Switch to Secure Mode*/
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@ -191,7 +194,7 @@ func handle_smc
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/* r0 points to smc context */
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/* r0 points to smc context */
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/* Restore SCR from stack */
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/* Restore SCR from stack */
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pop {r1}
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pop {r1, r2}
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stcopr r1, SCR
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stcopr r1, SCR
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isb
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isb
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@ -39,6 +39,7 @@
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#define SMC_CTX_GPREG_R2 0x8
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#define SMC_CTX_GPREG_R2 0x8
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#define SMC_CTX_GPREG_R3 0xC
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#define SMC_CTX_GPREG_R3 0xC
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#define SMC_CTX_GPREG_R4 0x10
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#define SMC_CTX_GPREG_R4 0x10
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#define SMC_CTX_GPREG_R5 0x14
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#define SMC_CTX_SP_USR 0x34
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#define SMC_CTX_SP_USR 0x34
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#define SMC_CTX_SPSR_MON 0x78
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#define SMC_CTX_SPSR_MON 0x78
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#define SMC_CTX_LR_MON 0x7C
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#define SMC_CTX_LR_MON 0x7C
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@ -38,22 +38,22 @@
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* contains the pointer to the `smc_context_t`.
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* contains the pointer to the `smc_context_t`.
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*/
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*/
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.macro smcc_save_gp_mode_regs
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.macro smcc_save_gp_mode_regs
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push {r0-r3, lr}
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push {r0-r4, lr}
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ldcopr r0, SCR
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ldcopr r0, SCR
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and r0, r0, #SCR_NS_BIT
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and r0, r0, #SCR_NS_BIT
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bl smc_get_ctx
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bl smc_get_ctx
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/* Save r4 - r12 in the SMC context */
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/* Save r5 - r12 in the SMC context */
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add r1, r0, #SMC_CTX_GPREG_R4
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add r1, r0, #SMC_CTX_GPREG_R5
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stm r1!, {r4-r12}
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stm r1!, {r5-r12}
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/*
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/*
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* Pop r0 - r3, lr to r4 - r7, lr from stack and then save
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* Pop r0 - r4, lr to r4 - r8, lr from stack and then save
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* it to SMC context.
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* it to SMC context.
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*/
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*/
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pop {r4-r7, lr}
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pop {r4-r8, lr}
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stm r0, {r4-r7}
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stm r0, {r4-r8}
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/* Save the banked registers including the current SPSR and LR */
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/* Save the banked registers including the current SPSR and LR */
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mrs r4, sp_usr
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mrs r4, sp_usr
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@ -72,7 +72,8 @@ endfunc cortex_a32_reset_func
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* ----------------------------------------------------
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* ----------------------------------------------------
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*/
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*/
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func cortex_a32_core_pwr_dwn
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func cortex_a32_core_pwr_dwn
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push {lr}
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/* r12 is pushed to meet the 8 byte stack alignment requirement */
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push {r12, lr}
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/* Assert if cache is enabled */
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/* Assert if cache is enabled */
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#if ASM_ASSERTION
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#if ASM_ASSERTION
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@ -92,7 +93,7 @@ func cortex_a32_core_pwr_dwn
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* Come out of intra cluster coherency
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* Come out of intra cluster coherency
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* ---------------------------------------------
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* ---------------------------------------------
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*/
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*/
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pop {lr}
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pop {r12, lr}
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b cortex_a32_disable_smp
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b cortex_a32_disable_smp
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endfunc cortex_a32_core_pwr_dwn
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endfunc cortex_a32_core_pwr_dwn
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@ -102,7 +103,8 @@ endfunc cortex_a32_core_pwr_dwn
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* -------------------------------------------------------
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* -------------------------------------------------------
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*/
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*/
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func cortex_a32_cluster_pwr_dwn
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func cortex_a32_cluster_pwr_dwn
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push {lr}
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/* r12 is pushed to meet the 8 byte stack alignment requirement */
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push {r12, lr}
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/* Assert if cache is enabled */
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/* Assert if cache is enabled */
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#if ASM_ASSERTION
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#if ASM_ASSERTION
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@ -135,7 +137,7 @@ func cortex_a32_cluster_pwr_dwn
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* Come out of intra cluster coherency
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* Come out of intra cluster coherency
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* ---------------------------------------------
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* ---------------------------------------------
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*/
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*/
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pop {lr}
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pop {r12, lr}
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b cortex_a32_disable_smp
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b cortex_a32_disable_smp
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endfunc cortex_a32_cluster_pwr_dwn
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endfunc cortex_a32_cluster_pwr_dwn
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@ -76,9 +76,10 @@ endfunc reset_handler
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*/
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*/
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.globl prepare_core_pwr_dwn
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.globl prepare_core_pwr_dwn
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func prepare_core_pwr_dwn
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func prepare_core_pwr_dwn
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push {lr}
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/* r12 is pushed to meet the 8 byte stack alignment requirement */
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push {r12, lr}
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bl _cpu_data
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bl _cpu_data
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pop {lr}
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pop {r12, lr}
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ldr r1, [r0, #CPU_DATA_CPU_OPS_PTR]
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ldr r1, [r0, #CPU_DATA_CPU_OPS_PTR]
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#if ASM_ASSERTION
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#if ASM_ASSERTION
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@ -98,9 +99,10 @@ endfunc prepare_core_pwr_dwn
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*/
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*/
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.globl prepare_cluster_pwr_dwn
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.globl prepare_cluster_pwr_dwn
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func prepare_cluster_pwr_dwn
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func prepare_cluster_pwr_dwn
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push {lr}
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/* r12 is pushed to meet the 8 byte stack alignment requirement */
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push {r12, lr}
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bl _cpu_data
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bl _cpu_data
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pop {lr}
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pop {r12, lr}
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ldr r1, [r0, #CPU_DATA_CPU_OPS_PTR]
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ldr r1, [r0, #CPU_DATA_CPU_OPS_PTR]
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#if ASM_ASSERTION
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#if ASM_ASSERTION
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@ -41,9 +41,10 @@
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* -----------------------------------------------------------------
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* -----------------------------------------------------------------
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*/
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*/
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func _cpu_data
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func _cpu_data
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push {lr}
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/* r12 is pushed to meet the 8 byte stack alignment requirement */
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push {r12, lr}
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bl plat_my_core_pos
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bl plat_my_core_pos
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pop {lr}
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pop {r12, lr}
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b _cpu_data_by_index
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b _cpu_data_by_index
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endfunc _cpu_data
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endfunc _cpu_data
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@ -93,7 +93,8 @@ endfunc psci_do_pwrdown_cache_maintenance
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* -----------------------------------------------------------------------
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* -----------------------------------------------------------------------
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*/
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*/
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func psci_do_pwrup_cache_maintenance
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func psci_do_pwrup_cache_maintenance
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push {lr}
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/* r12 is pushed to meet the 8 byte stack alignment requirement */
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push {r12, lr}
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/* ---------------------------------------------
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/* ---------------------------------------------
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* Ensure any inflight stack writes have made it
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* Ensure any inflight stack writes have made it
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@ -123,7 +124,7 @@ func psci_do_pwrup_cache_maintenance
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stcopr r0, SCTLR
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stcopr r0, SCTLR
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isb
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isb
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pop {pc}
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pop {r12, pc}
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endfunc psci_do_pwrup_cache_maintenance
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endfunc psci_do_pwrup_cache_maintenance
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/* ---------------------------------------------
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/* ---------------------------------------------
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